coreboot December 2017

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68 participants
177 discussions

Re: [coreboot] coreboot support for Minnowboard Turbot E3845
by Michael Graichen 17 Dec '17

17 Dec '17

Hey, I extracted 906 from original BIOS. But it still hangs on after POST 0x92 the same with 907. Aren't there any possibilities to get more debug information out of FSP? Best Regards Michael Am 16.12.2017 um 19:35 schrieb Zoran Stojsavljevic: > /proc/cpuinfo tells me that the original image is using microcode: 0x906 > but where can I find it? I do not have 0x906. Please, try 0x907 (attached .inc). Good Luck! Zoran On Sat, Dec 16, 2017 at 2:49 PM, Michael Graichen <michael.graichen(a)hotmail.com<mailto:michael.graichen@hotmail.com>> wrote: Hey Zoran, thanks for your help! Is there some place to look up the connection between CPUID and microcode? I tested M0130679905.inc but still with the same effect. So I flashed the original Image and booted Linux. /proc/cpuinfo tells me that the original image is using microcode: 0x906 but where can I find it? Best Regards Michael Am 14.12.2017 um 20:25 schrieb Zoran Stojsavljevic: > for a E3845 Family: 0x06 Model:0x37 Stepping: 0x09... This is CPUID 0x30679, which uses MCU M0130679901.h (ONLY this one). You can also try the following MCU: M0130679905.inc (attached). You need to convert it to .h Zoran _______ On Thu, Dec 14, 2017 at 6:15 PM, Michael Graichen <michael.graichen(a)hotmail.com<mailto:michael.graichen@hotmail.com>> wrote: Hey Piotr, I'm glad to read that somebody else is working on the Atoms as well. I'm not sure about my ucode config. At the moment I'm using 5 include files: M0130673322.h M0130678806.h M0130678817.h M0130679901.h and M0230672228.h for a E3845 Family: 0x06 Model:0x37 Stepping: 0x09. I copied the includes from various FSP's and the FSP_GOLD packages. I tried other combinations before but then i had no output on the serial line so I ended up using these five. What is your Familly/Model/Stepping and what are you using for ucode? Best Regards Michael Am 14.12.2017 um 00:04 schrieb Piotr Król: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA512 > > > > On 12/13/2017 07:29 PM, Michael Graichen wrote: >> Hey, > Hi Michael, > >> I've bought a Minnowboard Turbot (quad core / E3845) to start >> developing on the Atom's. >> >> I was hopping that it has support like the Minnowboard Max but it >> get stuck right after FspInitApi(&FspInitParams); in >> coreboot/src/drivers/intel/fsp1_0/fsp_util.c. The last output i can >> see is "POST: 0x92" which comes from >> post_code(POST_FSP_MEMORY_INIT); right before >> FspInitApi(&FspInitParams); > I'm not expert in MinnowBoard Turbot, but I play recently with E3826 > and saw similar behavior when incorrect microcode was used (or no > microcode). What are your ucode configuration ? > > Best Regards, > - -- > Piotr Król > Embedded Systems Consultant > https://3mdeb.com | @3mdeb_com > -----BEGIN PGP SIGNATURE----- > > iQIzBAEBCgAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAloxsggACgkQsu5x6Weq > nkzfPg/+PM8fk80pbmexWQw5IO4LbDOX4vw5LYkrkeTxh/3T6hAAjBt7KJ6OA4Ft > vW8d/Ll37/r7zutrOXemXZRtxulHy4FL/7aGcDdu8JPxnO4ysLGM0fOZxkZtuyNA > WYI7nS5mYcVdA69driI3rW0cSuGVAy7LiOBIzzV5Z8iWjQXop56cMJiP6In7zayr > 7B5XZ6Ix934AzYihK6hZ5Rz5jZyouKb0NJRQLnRB+MljuL4sLa18bnX5NUBqgDxu > cbw54UYgkgd6CsrbGw3XIGB63k7jYYOUayZwBaqg4QYIxPs798pX5MTe7VMJneFc > kmg+t8HHZxQkaF9YjoVwyS5y4/24FgwQ5bROo/ztNqZMz2q0nK6jd7vQjobFKTVb > Hc7w0jQIY37z3ZConHj9hHeVQ4AILFgpUl+NJj04hekcs4aAwJhbMun7YEAmchkp > cCsv+WvXmOUZwTZR+CoH1xTYSMIX6JkMDZlmlhR/UGlAdpIkxMKQ6MezJXgyihvn > rBBAMDKGvNxeZ00Cf35d+tI9OwDWw/YxYDMV3nx5MzeIkvho4Umg6ey824QlqxBF > D+3wYuiB4ZO/uEViYkW62jFOMHxeTZ9lBNdigPsnuclDiXhvAoA1uImsaLHjNHpQ > xndtfh+FPE3kB6c4koorgXxa3OZacd+4pGDmyjOy7Vl+TZk5hkA= > =r1Ls > -----END PGP SIGNATURE----- > -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Asus P2-99: PS2 keyboard, time stamps, double logs
by Keith Hui 17 Dec '17

17 Dec '17

Paul, I also have similar keyboard troubles with my P2B-LS, when I would not be able to use the keyboard to select an entry to boot at LILO prompt. Setting a PS/2 keyboard timeout and/or init in both coreboot and SeaBIOS seems to help, but not sure if it helps 100%. And how do I set up board variants? At this point we should be able to group the Asus P2B family into 4 boards plus variants: P2B+P2-99 (3 DIMM, served by asus/p2b) P2B-F+P2B-L/S/LS (4 DIMM, served by asus/p2b-ls, the "L"AN works fine without any work from coreboot; while I still haven't figured out terminations of the onboard Adaptec "S"CSI device) P3B-F (4 DIMM, served by asus/p3b-f, it needs extra code to enable SPD) P2B-D+P2B-DS (4 DIMM, SMP, served by asus/p2b-ds) > From: Paul Menzel <paulepanter(a)users.sourceforge.net> > To: Branden Waldner <scruffy99(a)gmail.com> > Cc: coreboot(a)coreboot.org > Bcc: > Date: Sat, 16 Dec 2017 11:08:22 +0100 > Subject: [coreboot] Asus P2-99: PS2 keyboard, time stamps, double logs > Dear Branden, > > > Thank you for uploading the results for your ASUS P2-99 to the board > status repository [1]. > > You configured your board as below. > > ``` > # This image was built using coreboot 4.6-2379-g0cc28d7e61 > CONFIG_VENDOR_ASUS=y > CONFIG_BOARD_ASUS_P2B=y > CONFIG_DRIVERS_PS2_KEYBOARD=y > CONFIG_SEABIOS_PS2_TIMEOUT=500 > # CONFIG_DRIVERS_INTEL_WIFI is not set > CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="P2-99" > CONFIG_SEABIOS_MASTER=y > ``` > > First, if the image built for the different board Asus P2B builds, we > should just add a variant for the Asus P2-99, so that the upload is not > so confusing. > > Second, as you use SeaBIOS as a payload you can deselect > `CONFIG_DRIVERS_PS2_KEYBOARD` as SeaBIOS can initialize that on its > own. > > I only know the time-out for SeaBIOS to be needed on laptops. Is > SeaBIOS unable to initialize the PS/2 keyboard, when you remove the > time-out? > > Despite time stamp collection being enabled > (`CONFIG_COLLECT_TIMESTAMPS=y`), there is no upload of the output > `cbmem -t`. Is that not working? > > Also, did your board reboot/reset in between? > > ``` > […] > SeaBIOS (version rel-1.11.0-4-g844b864) > […] > Booting from Hard Disk... > Booting from 0000:7c00 > > > coreboot-4.6-2379-g0cc28d7e61 Fri Dec 15 03:32:04 UTC 2017 romstage starting... > […] > ``` > > > Thanks, > > Paul > > > [1] asus/p2b/4.6-2379-g0cc28d7e61/2017-12-15T03_32_04Z

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broken links on www.coreboot.org
by Antony Pavlov 17 Dec '17

17 Dec '17

Hi! Several links on www.coreboot.org are broken. E.g. I can download no pdf files from https://www.coreboot.org/Distributed_and_Automated_Testsystem E.g. the link https://www.coreboot.org/PDFs/LinuxBIOS-testing/TestIntegrationManual.pdf leads to non-existent wiki page and the file TestIntegrationManual.pdf is unavailable anymore. Can anybody fix this situation please? -- Best regards, Antony Pavlov

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Re: [coreboot] Disabling Intel ME 11 via undocumented mode
by Denis 'GNUtoo' Carikli 17 Dec '17

17 Dec '17

On Thu, 14 Dec 2017 20:25:53 -0500 Youness Alaoui <kakaroto(a)kakaroto.homelinux.net> wrote: > In my opinion, the ME is indeed disabled because the entire ME > functionality is disabled, no ME processes are running, and the kernel > on its own is irrelevant, even if it keeps running. > However, I do not have anymore a strong counter opinion to your > statement that you don't consider the ME to be disabled as I > originally did. > It all depends on how we choose to see it, I consider it to be > disabled, and you consider that it's not. It will always differ on > each person's interpretation of the definition of the word "disabled". [...] > All I could find online about the actual definition of the word > "disabled" is either : [...] > * "rendered inoperative (as by being damaged or deliberately > altered)" (Merriam-Webster dictionary) [...] > * "to make ineffective or inoperative" (Merriam-Webster dictionary) > * "To deprive of capability or effectiveness, especially to impair I find it more interesting to try to explain what is really going on to people, by using some construct like that: "disabled/limited/etc" by <Setting the HAP BIT>, with the first part being a judgment of the person writing that over what is acceptable or not, and the last part that tries to explain what it really means, so the people reading it could still have their own judgment on whether they consider it acceptable or not. Denis.

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Asus P2-99: PS2 keyboard, time stamps, double logs
by Paul Menzel 17 Dec '17

17 Dec '17

Dear Branden, Thank you for uploading the results for your ASUS P2-99 to the board status repository [1]. You configured your board as below. ``` # This image was built using coreboot 4.6-2379-g0cc28d7e61 CONFIG_VENDOR_ASUS=y CONFIG_BOARD_ASUS_P2B=y CONFIG_DRIVERS_PS2_KEYBOARD=y CONFIG_SEABIOS_PS2_TIMEOUT=500 # CONFIG_DRIVERS_INTEL_WIFI is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="P2-99" CONFIG_SEABIOS_MASTER=y ``` First, if the image built for the different board Asus P2B builds, we should just add a variant for the Asus P2-99, so that the upload is not so confusing. Second, as you use SeaBIOS as a payload you can deselect `CONFIG_DRIVERS_PS2_KEYBOARD` as SeaBIOS can initialize that on its own. I only know the time-out for SeaBIOS to be needed on laptops. Is SeaBIOS unable to initialize the PS/2 keyboard, when you remove the time-out? Despite time stamp collection being enabled (`CONFIG_COLLECT_TIMESTAMPS=y`), there is no upload of the output `cbmem -t`. Is that not working? Also, did your board reboot/reset in between? ``` […] SeaBIOS (version rel-1.11.0-4-g844b864) […] Booting from Hard Disk... Booting from 0000:7c00 coreboot-4.6-2379-g0cc28d7e61 Fri Dec 15 03:32:04 UTC 2017 romstage starting... […] ``` Thanks, Paul [1] asus/p2b/4.6-2379-g0cc28d7e61/2017-12-15T03_32_04Z

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Re: [coreboot] coreboot support for Minnowboard Turbot E3845
by Zoran Stojsavljevic 16 Dec '17

16 Dec '17

> /proc/cpuinfo tells me that the original image is using microcode: 0x906 > but where can I find it? I do not have 0x906. Please, try 0x907 (attached .inc). Good Luck! Zoran On Sat, Dec 16, 2017 at 2:49 PM, Michael Graichen < michael.graichen(a)hotmail.com> wrote: > Hey Zoran, > > thanks for your help! > > Is there some place to look up the connection between CPUID and microcode? > > I tested M0130679905.inc but still with the same effect. > > So I flashed the original Image and booted Linux. > /proc/cpuinfo tells me that the original image is using microcode: 0x906 > > but where can I find it? > > Best Regards > > Michael > > > > > Am 14.12.2017 um 20:25 schrieb Zoran Stojsavljevic: > > > for a E3845 Family: 0x06 Model:0x37 Stepping: 0x09... > > This is CPUID 0x30679, which uses MCU M0130679901.h (ONLY this one). > > You can also try the following MCU: M0130679905.inc (attached). You need > to convert it to .h > > Zoran > _______ > > On Thu, Dec 14, 2017 at 6:15 PM, Michael Graichen < > michael.graichen(a)hotmail.com> wrote: > >> Hey Piotr, >> >> I'm glad to read that somebody else is working on the Atoms as well. >> I'm not sure about my ucode config. At the moment I'm using 5 include >> files: >> >> M0130673322.h >> M0130678806.h >> M0130678817.h >> M0130679901.h and >> M0230672228.h >> >> for a E3845 Family: 0x06 Model:0x37 Stepping: 0x09. >> I copied the includes from various FSP's and the FSP_GOLD packages. >> >> I tried other combinations before but then i had no output on the serial >> line so I ended up using these five. >> >> What is your Familly/Model/Stepping and what are you using for ucode? >> >> Best Regards >> >> Michael >> >> >> >> >> Am 14.12.2017 um 00:04 schrieb Piotr Król: >> > -----BEGIN PGP SIGNED MESSAGE----- >> > Hash: SHA512 >> > >> > >> > >> > On 12/13/2017 07:29 PM, Michael Graichen wrote: >> >> Hey, >> > Hi Michael, >> > >> >> I've bought a Minnowboard Turbot (quad core / E3845) to start >> >> developing on the Atom's. >> >> >> >> I was hopping that it has support like the Minnowboard Max but it >> >> get stuck right after FspInitApi(&FspInitParams); in >> >> coreboot/src/drivers/intel/fsp1_0/fsp_util.c. The last output i can >> >> see is "POST: 0x92" which comes from >> >> post_code(POST_FSP_MEMORY_INIT); right before >> >> FspInitApi(&FspInitParams); >> > I'm not expert in MinnowBoard Turbot, but I play recently with E3826 >> > and saw similar behavior when incorrect microcode was used (or no >> > microcode). What are your ucode configuration ? >> > >> > Best Regards, >> > - -- >> > Piotr Król >> > Embedded Systems Consultant >> > https://3mdeb.com | @3mdeb_com >> > -----BEGIN PGP SIGNATURE----- >> > >> > iQIzBAEBCgAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAloxsggACgkQsu5x6Weq >> > nkzfPg/+PM8fk80pbmexWQw5IO4LbDOX4vw5LYkrkeTxh/3T6hAAjBt7KJ6OA4Ft >> > vW8d/Ll37/r7zutrOXemXZRtxulHy4FL/7aGcDdu8JPxnO4ysLGM0fOZxkZtuyNA >> > WYI7nS5mYcVdA69driI3rW0cSuGVAy7LiOBIzzV5Z8iWjQXop56cMJiP6In7zayr >> > 7B5XZ6Ix934AzYihK6hZ5Rz5jZyouKb0NJRQLnRB+MljuL4sLa18bnX5NUBqgDxu >> > cbw54UYgkgd6CsrbGw3XIGB63k7jYYOUayZwBaqg4QYIxPs798pX5MTe7VMJneFc >> > kmg+t8HHZxQkaF9YjoVwyS5y4/24FgwQ5bROo/ztNqZMz2q0nK6jd7vQjobFKTVb >> > Hc7w0jQIY37z3ZConHj9hHeVQ4AILFgpUl+NJj04hekcs4aAwJhbMun7YEAmchkp >> > cCsv+WvXmOUZwTZR+CoH1xTYSMIX6JkMDZlmlhR/UGlAdpIkxMKQ6MezJXgyihvn >> > rBBAMDKGvNxeZ00Cf35d+tI9OwDWw/YxYDMV3nx5MzeIkvho4Umg6ey824QlqxBF >> > D+3wYuiB4ZO/uEViYkW62jFOMHxeTZ9lBNdigPsnuclDiXhvAoA1uImsaLHjNHpQ >> > xndtfh+FPE3kB6c4koorgXxa3OZacd+4pGDmyjOy7Vl+TZk5hkA= >> > =r1Ls >> > -----END PGP SIGNATURE----- >> > >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot >> > > >

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Re: [coreboot] coreboot support for Minnowboard Turbot E3845
by Michael Graichen 16 Dec '17

16 Dec '17

Hey Zoran, thanks for your help! Is there some place to look up the connection between CPUID and microcode? I tested M0130679905.inc but still with the same effect. So I flashed the original Image and booted Linux. /proc/cpuinfo tells me that the original image is using microcode: 0x906 but where can I find it? Best Regards Michael Am 14.12.2017 um 20:25 schrieb Zoran Stojsavljevic: > for a E3845 Family: 0x06 Model:0x37 Stepping: 0x09... This is CPUID 0x30679, which uses MCU M0130679901.h (ONLY this one). You can also try the following MCU: M0130679905.inc (attached). You need to convert it to .h Zoran _______ On Thu, Dec 14, 2017 at 6:15 PM, Michael Graichen <michael.graichen(a)hotmail.com<mailto:michael.graichen@hotmail.com>> wrote: Hey Piotr, I'm glad to read that somebody else is working on the Atoms as well. I'm not sure about my ucode config. At the moment I'm using 5 include files: M0130673322.h M0130678806.h M0130678817.h M0130679901.h and M0230672228.h for a E3845 Family: 0x06 Model:0x37 Stepping: 0x09. I copied the includes from various FSP's and the FSP_GOLD packages. I tried other combinations before but then i had no output on the serial line so I ended up using these five. What is your Familly/Model/Stepping and what are you using for ucode? Best Regards Michael Am 14.12.2017 um 00:04 schrieb Piotr Król: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA512 > > > > On 12/13/2017 07:29 PM, Michael Graichen wrote: >> Hey, > Hi Michael, > >> I've bought a Minnowboard Turbot (quad core / E3845) to start >> developing on the Atom's. >> >> I was hopping that it has support like the Minnowboard Max but it >> get stuck right after FspInitApi(&FspInitParams); in >> coreboot/src/drivers/intel/fsp1_0/fsp_util.c. The last output i can >> see is "POST: 0x92" which comes from >> post_code(POST_FSP_MEMORY_INIT); right before >> FspInitApi(&FspInitParams); > I'm not expert in MinnowBoard Turbot, but I play recently with E3826 > and saw similar behavior when incorrect microcode was used (or no > microcode). What are your ucode configuration ? > > Best Regards, > - -- > Piotr Król > Embedded Systems Consultant > https://3mdeb.com | @3mdeb_com > -----BEGIN PGP SIGNATURE----- > > iQIzBAEBCgAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAloxsggACgkQsu5x6Weq > nkzfPg/+PM8fk80pbmexWQw5IO4LbDOX4vw5LYkrkeTxh/3T6hAAjBt7KJ6OA4Ft > vW8d/Ll37/r7zutrOXemXZRtxulHy4FL/7aGcDdu8JPxnO4ysLGM0fOZxkZtuyNA > WYI7nS5mYcVdA69driI3rW0cSuGVAy7LiOBIzzV5Z8iWjQXop56cMJiP6In7zayr > 7B5XZ6Ix934AzYihK6hZ5Rz5jZyouKb0NJRQLnRB+MljuL4sLa18bnX5NUBqgDxu > cbw54UYgkgd6CsrbGw3XIGB63k7jYYOUayZwBaqg4QYIxPs798pX5MTe7VMJneFc > kmg+t8HHZxQkaF9YjoVwyS5y4/24FgwQ5bROo/ztNqZMz2q0nK6jd7vQjobFKTVb > Hc7w0jQIY37z3ZConHj9hHeVQ4AILFgpUl+NJj04hekcs4aAwJhbMun7YEAmchkp > cCsv+WvXmOUZwTZR+CoH1xTYSMIX6JkMDZlmlhR/UGlAdpIkxMKQ6MezJXgyihvn > rBBAMDKGvNxeZ00Cf35d+tI9OwDWw/YxYDMV3nx5MzeIkvho4Umg6ey824QlqxBF > D+3wYuiB4ZO/uEViYkW62jFOMHxeTZ9lBNdigPsnuclDiXhvAoA1uImsaLHjNHpQ > xndtfh+FPE3kB6c4koorgXxa3OZacd+4pGDmyjOy7Vl+TZk5hkA= > =r1Ls > -----END PGP SIGNATURE----- > -- coreboot mailing list: coreboot(a)coreboot.org<mailto:coreboot@coreboot.org> https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] Black screen during SeaBIOS boot
by Daniel K 16 Dec '17

16 Dec '17

Thanks for the replies! First I just wanted to clarify, I don't have an issue with the 30 seconds wait (yet). I will deal with that in due time haha. Just want to get something appearing on screen at the moment. On a side note, I do want GRUB2 as my main payload ultimately. Just thought I'd get started with SeaBIOS first. Looks like the lspci I provided earlier was wrong because lspci has different output when I'm on coreboot and when I'm on my manufacturer BIOS (been switching back and forth). Here's my coreboot booted lspci video devices: 01:00.0 VGA compatible controller: NVIDIA Corporation GF110 [GeForce GTX 570] (rev a1) -> PCIe VGA (want to use this one) 08:01.0 VGA compatible controller: ASPEED Technology, Inc. ASPEED Graphics Family (rev 10) -> Onboard VGA (don't want this one) > You might need to edit src/device/Kconfig with: > > config MULTIPLE_VGA_ADAPTERS > bool > default y Thank you so much for this. Why is this not in the coreboot configs? Is there a page that describes these settings similar to https://www.coreboot.org/Coreboot_Options ? I'm avoiding the use of a vgabios on purpose because I only want text-mode (trying to avoid all proprietary blobs). With the MULTIPLE_VGA_ADAPTERS Kconfig configuration, I now get the following output from cbmem -c: POST: 0x73 found VGA at PCI: 08:01.0 found VGA at PCI: 01:00.0 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device ... DOMAIN: 0000 assign_resources, bus 0 link: 0 VGA: vga_pri bus num = 1 bus range [0,8] VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device ... POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 0 usecs ... POST: 0x75 PCI: 08:01.0 init ... ASpeed AST2050: initializing video device ast_detect_chip: AST 1100 detected ast_detect_chip: VGA not enabled on entry, requesting chip POST ast_detect_chip: Analog VGA only ast_driver_load: dram 800000000 0 16 00800000 ASpeed VGA text mode initialized PCI: 08:01.0 init finished in 33167 usecs (Sorry for the lack of timestamps. I tried cbmem -t but I haven't turned time logging on in coreboot yet.) Looks like the device I want (PCI: 01:00.0) gets VGA set up in the first chunk, but in the last 2 chunks of the log, it's initialising video for my unwanted onboard device (PCI: 08:01.0) and skipping initialisation for my wanted device altogether! Is there a setting to turn off the unwanted PCI device (PCI: 08:01.0) or force the one I want to be used as the main device? Or get the device I want to even initialise?

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The OpenBMC port for the KGPE-D16 and KCMA-D8 is almost done - try the beta!
by Taiidan＠gmx.com 16 Dec '17

16 Dec '17

At last - not one but two easily obtainable, affordable, owner controlled, no-PSP/ME, libre firmware boards that are new enough to be useful and have 99% feature parity with commercial closed source systems. (100% if we had SR-IOV/ARI support) https://www.raptorengineering.com/coreboot/kgpe-d16-bmc-port-status.php The only thing missing from it now is serial over IPMI although you can use serial via SSH and screen at the moment, and of course the ability to change the password without re-compiling. Even if you don't need a BMC you still might want to install it for the OS-independent fan control, otherwise you can maybe send your ASMB module to someone else who needs one. It would be nice if someone is able to locate a source for the ASMB4/5 modules for those who do not have one. They appear quite simple - no reason they should cost $50 or w/e - perhaps a good samaritan could figure out how to make them?

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Re: [coreboot] Black screen during SeaBIOS boot
by Taiidan＠gmx.com 16 Dec '17

16 Dec '17

I would do what awokd said with the multiple vga adapters option, I would also consider using grub as a payload and/or selecting Coreboot Execute Option ROM's/VGA Option ROM's with the appropriate YABEL options/restrictions for security (more secure than SeaBIOS method) Youness he is using a KGPE-D16 which has no ME/PSP, so that issue can be ruled out. Tips: Reducing the serial log level to one or two will drastically speed the boot time. The OpenBMC beta is now available if you wish to have an open source BMC and use the ASMB4 module.

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coreboot December 2017