coreboot October 2016

coreboot@coreboot.org

55 participants
148 discussions

i2c_writeb vs i2c_raw_write output
by Haleigh Novak 07 Oct '16

07 Oct '16

Hello All, I am currently trying to send POST codes from Coreboot (downloaded approximately a month ago) to a Beagle I2C/SPI reader, specifically via i2c. I don't know the register needed for i2c_writeb() so I figured I would use i2c_raw_write(). In general since I have been unable to locate anything explaining the difference between the two functions I would really appriciate it if someone could explain it or direct me to where I can find documentation. I am hoping that the explaination/resource will either tell me where / or direct me to how I can figure out where the i2c_raw_write will write to (if it will just write directly to the Beagle or somewhere else)? Or would it be better to send it to a register with i2c_writeb()? I am running Coreboot on an ASROCK Mainboard, model IMB-A180. Thank you. HN

2 1

Re: [coreboot] Servo debug uart in Linux?
by Trammell Hudson 07 Oct '16

07 Oct '16

On Thu, Oct 06, 2016 at 11:27:01AM -0700, Duncan Laurie wrote: > I may be mis-remembering and this might come up as ttyS0 in linux for > skylake. (it is ttyS2 on apollolake...) Or just use a custom command line > like console=uart,mmio32,0xd1134000,115200n8 That commandline doesn't produce any output for me. Is that the right address? src/soc/intel/skylake/include/soc/iomap.h has: #define UART_DEBUG_BASE_ADDRESS 0xfe034000 Unfortunately using that address doesn't produce any output, either. For Xen I've hacked together a slow serial output using port 0x80 and recreating it from the ec console. This was very helpful to track down that it was hanging when trying to initialize the vga console, which doesn't exist since there is no VGA bios. Xen starts now, but the dom0 kernel doesn't show any signs of life with earlyprintk=xen or trying to send it to the mmio uart. It might be due to the 4.4 kernel not having all the skylake support. Still, it's progress since yesterday... (XEN) Xen version 4.6.3 (user@domain) (gcc (Ubuntu 5.2.1-22ubuntu2) 5.2.1 201510 10) debug=n 1970-01-01 (XEN) Latest ChangeSet: (XEN) Bootloader: kexec 2.0.12 (XEN) Command line: no-real-mode console=none reboot=no (XEN) Video information: (XEN) VGA is text mode 80x25, font 8x16 (XEN) Disc information: (XEN) Found 0 MBR signatures (XEN) Found 0 EDD information structures (XEN) Multiboot-e820 RAM map: (XEN) 0000000000000000 - 0000000000000fff type 2989 (XEN) 0000000000001000 - 000000000009ffff (usable) (XEN) 00000000000a0000 - 00000000000fffff type 2989 (XEN) 0000000000100000 - 000000007aaadfff (usable) (XEN) 000000007aaae000 - 000000007aefffff type 2989 (XEN) 000000007af00000 - 000000007fffffff type 2989 (XEN) 00000000e0000000 - 00000000efffffff type 2989 (XEN) 00000000fd000000 - 00000000ffffffff type 2989 (XEN) 0000000100000000 - 000000027effffff (usable) (XEN) ACPI: RSDP 000F0000, 0024 (r2 CORE ) (XEN) ACPI: XSDT 7AABF0E0, 005C (r1 CORE COREBOOT 0 CORE 0) (XEN) ACPI: FACP 7AAC3410, 00F4 (r5 CORE COREBOOT 0 CORE 1) (XEN) ACPI Error (tbfadt-0450): Required field "PmTimerBlock" has zero address a nd/or length: 0000000000000000/0 [20070126] (XEN) ACPI: DSDT 7AABF280, 4186 (r5 COREv4 COREBOOT 20110725 INTL 20160318) (XEN) ACPI: FACS 7AABF240, 0040 (XEN) ACPI: SSDT 7AAC3510, 106D (r2 CORE COREBOOT 2A CORE 2A) (XEN) ACPI: MCFG 7AAC4580, 003C (r1 CORE COREBOOT 0 CORE 0) (XEN) ACPI: TCPA 7AAC45C0, 0032 (r2 CORE COREBOOT 0 CORE 0) (XEN) ACPI: APIC 7AAC4600, 006C (r1 CORE COREBOOT 0 CORE 0) (XEN) ACPI: NHLT 7AAC4670, 00F6 (r5 CORE COREBOOT 0 CORE 0) (XEN) ACPI: HPET 7AAC6770, 0038 (r1 CORE COREBOOT 0 CORE 0) (XEN) System RAM: 8090MB (8284456kB) (XEN) Domain heap initialised (XEN) Processor #0 6:14 APIC version 21 (XEN) Processor #1 6:14 APIC version 21 (XEN) Processor #2 6:14 APIC version 21 (XEN) Processor #3 6:14 APIC version 21 (XEN) IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119 (XEN) Enabling APIC mode: Flat. Using 1 I/O APICs (XEN) xstate_init: using cntxt_size: 0x440 and states: 0x1f (XEN) CPU0 CMCI LVT vector (0xf9) already installed (XEN) Using scheduler: SMP Credit Scheduler (credit) (XEN) Detected 1104.094 MHz processor. (XEN) Initing memory sharing. (XEN) PCI: Not using MCFG for segment 0000 bus 00-ff (XEN) I/O virtualisation disabled (XEN) Enabled directed EOI with ioapic_ack_old on! (XEN) ENABLING IO-APIC IRQs (XEN) -> Using old ACK method (XEN) Platform timer is 23.999MHz HPET (XEN) Allocated console ring of 16 KiB. (XEN) VMX: Supported advanced features: (XEN) - APIC MMIO access virtualisation (XEN) - APIC TPR shadow (XEN) - Extended Page Tables (EPT) (XEN) - Virtual-Processor Identifiers (VPID) (XEN) - Virtual NMI (XEN) - MSR direct-access bitmap (XEN) - Unrestricted Guest (XEN) - VMCS shadowing (XEN) - VM Functions (XEN) - Virtualisation Exceptions (XEN) HVM: ASIDs enabled. (XEN) HVM: VMX enabled (XEN) HVM: Hardware Assisted Paging (HAP) detected (XEN) HVM: HAP page sizes: 4kB, 2MB, 1GB (XEN) Brought up 4 CPUs (XEN) Dom0 has maximum 696 PIRQs (XEN) NX (Execute Disable) protection active (XEN) *** LOADING DOMAIN 0 *** (XEN) Xen kernel: 64-bit, lsb, compat32 (XEN) Dom0 kernel: 64-bit, PAE, lsb, paddr 0x1000000 -> 0x2055000 (XEN) PHYSICAL MEMORY ARRANGEMENT: (XEN) Dom0 alloc.: 000000026c000000->0000000270000000 (1980530 pages to be allocated) (XEN) Init. ramdisk: 000000027a79b000->000000027ee00000 (XEN) VIRTUAL MEMORY ARRANGEMENT: (XEN) Loaded kernel: ffffffff81000000->ffffffff82055000 (XEN) Init. ramdisk: 0000000000000000->0000000000000000 (XEN) Phys-Mach map: 0000008000000000->0000008000f5f6b8 (XEN) Start info: ffffffff82055000->ffffffff820554b4 (XEN) Page tables: ffffffff82056000->ffffffff8206b000 (XEN) Boot stack: ffffffff8206b000->ffffffff8206c000 (XEN) TOTAL: ffffffff80000000->ffffffff82400000 (XEN) ENTRY ADDRESS: ffffffff81d521f0 (XEN) Dom0 has maximum 4 VCPUs (XEN) Scrubbing Free RAM on 1 nodes using 2 CPUs (XEN) ........................................done. (XEN) Initial low memory virq threshold set at 0x4000 pages. (XEN) Std. Loglevel: Errors and warnings (XEN) Guest Loglevel: Nothing (Rate-limited: Errors and warnings) (XEN) *** Serial input -> DOM0 (type 'CTRL-a' three times to switch input to Xen) (XEN) Freed 320kB init memory. -- Trammell

2 1

What are the ncore gpios on Baytrail (E3827) ?
by benoit 07 Oct '16

07 Oct '16

I checked out the coreboot code last time with debug traces that I have on my platform. In addition I read the atom e3800 family datasheet (from intel website). I look at these files: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/fsp_baytra… https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/fsp_baytra… https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/fsp_baytra… Where these defines are used : #define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) #define IO_BASE_ADDRESS 0xfed0c000 #define IO_BASE_OFFSET_GPNCORE 0x1000 #define GPNCORE_COUNT 27 I saw in the intel atom datasheet the GPSCORE (from state S0) @0xfed0c000 and the GPSSUS (from state S5) @0xfed0e000. But I have never seen GPNCORE @0xfed0d000 (0xfed0c000 + 0x1000) in the Intel atom datasheet. Nevertheless these registers are initialized. Can someone is aware about the GPIO GPNCORE registers on the atom E3800 family? Are they used on atom E3800 family ? If GPIOs GPNCORE are used where are they located ? Thanks in advance for helping me Benoit

1 0

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 07 Oct '16

07 Oct '16

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 49 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1364082: Integer handling issues (NO_EFFECT) /src/soc/rockchip/common/spi.c: 170 in rockchip_spi_set_sample_delay() ________________________________________________________________________________________________________ *** CID 1364082: Integer handling issues (NO_EFFECT) /src/soc/rockchip/common/spi.c: 170 in rockchip_spi_set_sample_delay() 164 assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves)); 165 struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; 166 unsigned int rsd; 167 168 /* Rxd Sample Delay */ 169 rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8); >>> CID 1364082: Integer handling issues (NO_EFFECT) >>> This greater-than-or-equal-to-zero comparison of an unsigned value is always true. "rsd >= 0U". 170 assert(rsd >= 0 && rsd <= 3); 171 clrsetbits_le32(&regs->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, 172 rsd << SPI_RXDSD_OFFSET); 173 } 174 175 int spi_claim_bus(struct spi_slave *slave) ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

1 0

Re: [coreboot] [baytrail_FSP] question about lpss device with ACPI mode in win8
by szr 07 Oct '16

07 Oct '16

1 0

Re: [coreboot] [coreboot-announce] SHORT NOTICE: coreboot.berlin next weekend, Oct. 7-9
by Stefan Reinauer 06 Oct '16

06 Oct '16

Have fun, folks! Wish I could be there. Send updates and pictures! Stefan * ron minnich <rminnich(a)gmail.com> [161001 05:23]: > See you there! I just registered and am really looking forward to seeing > everyone! Thanks Peter! > > ron > > On Fri, Sep 30, 2016 at 9:41 AM Peter Stuge <peter(a)stuge.se> wrote: > > Hello all, > > I'm happy to *finally* have the information and registration page online: > > https://coreboot.berlin/ > > > Yes, it's very late, but I hope that we will still be a good number > of people meeting up next weekend. > > Quick feedback helps me make sure that everyone will get food. > > If you are interested in attending, but unable to register at the > Community Registration Fee cost then please get in touch with me, > so that we can try to work something out. > > > Thank you very much, and hope to see you in Berlin on the 7:th! > > //Peter > > _______________________________________________ > coreboot-announce mailing list > coreboot-announce(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot-announce > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot

1 0

Re: [coreboot] How to pass custom defined data from Coreboot to GRUB2
by Stefan Reinauer 06 Oct '16

06 Oct '16

* Mohan Shanmuga Sundaram <mohan.sundaram(a)aricent.com> [161005 09:55]: > Paul, Thanks for the info! > I looked into CBTABLES, but cannot understand others than CMOS table. It looks simple to me to use CMOS table that I have to define some region for user data in the 'cmos.layout' and use it at GRUB or Ubuntu Linux. But where does CMOS tables really reside? On the boot flash or DDR3? > > Regards, > Mohan Hi Mohan, check out lib/coreboot_table.c:lb_gpios() - This is what Chrome OS devices use to pass GPIO information to the payload. It might be usable for the problem you are trying to solve. Stefan

1 0

Re: [coreboot] Servo debug uart in Linux?
by Duncan Laurie 06 Oct '16

06 Oct '16

On Thu, Oct 6, 2016 at 11:08 AM, Duncan Laurie <dlaurie(a)chromium.org> wrote: > On Thu, Oct 6, 2016 at 10:56 AM, Trammell Hudson <hudson(a)trmm.net> wrote: > >> Is it possible to use the Skylake Servo debug UART in Linux or Xen? >> It doesn't show up as a normal 16550 (setserial reports "uart type >> unknown"), which is making debugging the payload kernel a little >> frustrating. >> >> I've added lots of "outb $0x80" calls to trace the Xen hypervisor and >> have figured out that the Skylake doesn't work with the x2apic, the xsave >> instruction or the MCE handler, but would prefer a higher bandwidth way >> to report progress/errors. >> >> > The debug UART on Skylake is 32bit MMIO based, so it does not work with > most existing serial drivers. It should work in recent Linux kernels and > come up as ttyS2, but you can also force it with earlyprintk using the > 'mmio32' directive and the base address. > > I may be mis-remembering and this might come up as ttyS0 in linux for skylake. (it is ttyS2 on apollolake...) Or just use a custom command line like console=uart,mmio32,0xd1134000,115200n8 -duncan > The device can be put into 16550/8-bit compatible mode, there is some code > to do this on broadwell at soc/intel/skylake/broadwell/romstage/uart.c > but on Skylake we left it in 32bit mode as putting it in compatible mode > made it unable to suspend properly. > > I *think* for skylake you can set the device PchSerialIoIndexUart2 to > PchSerialIoLegacyUart (in devicetree.cb) and FSP will configure it for > 16500 byte mode. You will then need to update coreboot to use the uart in > 8-bit mode instead of 32bit mode. > > That still leaves the issue that it is mmio based and not IO based, so it > will still have a hard time in things like seabios. However I think Xen > does support MMIO UART so it might work there... > > -duncan > >

1 0

Servo debug uart in Linux?
by Trammell Hudson 06 Oct '16

06 Oct '16

Is it possible to use the Skylake Servo debug UART in Linux or Xen? It doesn't show up as a normal 16550 (setserial reports "uart type unknown"), which is making debugging the payload kernel a little frustrating. I've added lots of "outb $0x80" calls to trace the Xen hypervisor and have figured out that the Skylake doesn't work with the x2apic, the xsave instruction or the MCE handler, but would prefer a higher bandwidth way to report progress/errors. -- Trammell

2 1

Re: [coreboot] PCI passthrough on ASUS KGPE-D16
by Taiidan＠gmx.com 06 Oct '16

06 Oct '16

I would really love to find a legit answer Re: what chipsets/mobos support gfx i/o fwd before I splash out hundreds of dollars. AFIAK forwarding graphics devices requires a lot more special sauce than regular pci devices (like network interfaces) On my propitiatory-firmware intel laptop dmesg says "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics" So apparently you need a shadow gart for it to work, something that is above my paygrade. It would be really great if there was an IOMMU/GFX bit on the coreboot supported motherboards page as this is a common question that never finds anything more than anecdotal evidence. I am grateful for your help mike but running grep commands on the source files provides nothing more than just that. On 10/03/2016 07:09 PM, Mike Banon wrote: > Correct me if I am wrong, but I think: IOMMU support means that a > graphics card passthrough is possible (this is binary: IOMMU yes ==> > possible / no ==> not possible). If IOMMU support is buggy (which > seems to be commonly found with proprietary BIOS) maybe your system > could experience some bugs while you are using this feature. Of course > the most reliable way to find out is to try it, but I am pretty sure > that coreboot's IOMMU support is good > > On Sun, Oct 2, 2016 at 9:04 PM, Zoran Stojsavljevic > <zoran.stojsavljevic(a)gmail.com> wrote: >>> Would it be possible to passthrough a graphics card to a virtual machine >>> while using Coreboot/Libreboot? >> Hello opteron/AMD supporter, >> >> You did ask very (very, should say extremely) tricky question, you do know >> this (I betcha you do, don't you)??? ;-) >> >> Zoran >> _______ >> >> On Sun, Oct 2, 2016 at 6:22 PM, <opteron(a)keemail.me> wrote: >>> Hi, >>> >>> would it be possible to passthrough a graphics card to a virtual machine >>> while using Coreboot/Libreboot? The libreboot website says that the >>> motherboard offers full IOMMU-support when using a CPU from the Opteron >>> 6200/6300 series. >>> >>> https://wiki.archlinux.org/index.php/PCI_passthrough_via_OVMF >>> https://libreboot.org/docs/hcl/kgpe-d16.html >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> https://www.coreboot.org/mailman/listinfo/coreboot >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot

2 1

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot October 2016