coreboot March 2015

coreboot@coreboot.org

62 participants
166 discussions

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 28 Mar '15

28 Mar '15

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 5 new defect(s) introduced to coreboot found with Coverity Scan. 8 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 5 of 5 defect(s) ** CID 1291956: Incorrect expression (SIZEOF_MISMATCH) /src/arch/arm64/c_entry.c: 77 in prepare_secondary_cpu_startup() ________________________________________________________________________________________________________ *** CID 1291956: Incorrect expression (SIZEOF_MISMATCH) /src/arch/arm64/c_entry.c: 77 in prepare_secondary_cpu_startup() 71 } 72 73 extern void arm64_cpu_startup(void); 74 void *prepare_secondary_cpu_startup(void) 75 { 76 c_entry = &secondary_cpu_start; >>> CID 1291956: Incorrect expression (SIZEOF_MISMATCH) >>> Passing argument "c_entry" of type "void (*)(void)" and argument "8UL /* sizeof (c_entry) */" to function "dcache_clean_invalidate_by_mva" is suspicious. 77 dcache_clean_invalidate_by_mva(c_entry, sizeof(c_entry)); 78 79 return &arm64_cpu_startup; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://scan.coverity.com/projects/1016?tab=overview To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://scan.coverity.com/subscriptions/edit?email=coreboot%40coreboot.org&… .

1 0

Re: [coreboot] [Rangeley C2000] Can't step when in romstage main function of MohonPeak
by 郭佳 27 Mar '15

27 Mar '15

Hi Patrick, understood and thanks anyway. Regards, Hook Guo On Fri, Mar 27, 2015 at 6:33 PM, Patrick Georgi <pgeorgi(a)google.com> wrote: > Hi Hook Guo, > > 2015-03-27 11:11 GMT+01:00 郭佳 <yunyuaner(a)gmail.com>: >> At the time this main function has been called, the Cache as RAM has been setup >> by FSP, and the MTRR_PHYSBASE0 is FEF0_0006. > >> BTW: (1) Using the debugger's memory window, I can see Cache as RAM region of >> temporary stack are full of A5 5A, is it the correct case? > > For FSP related questions you should ask your Intel developer > relations contact or sales representative. > FSP isn't open source, and so we can't help you since we have no idea > what it does either, and even if people knew, there also isn't a lot > of interest within the coreboot community to provide free support for > components like these. > > > Thank you for your understanding, > Patrick > -- > Google Germany GmbH, ABC-Str. 19, 20354 Hamburg > Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg > Geschäftsführer: Graham Law, Christine Elizabeth Flores

1 0

Re: [coreboot] [Rangeley C2000] Can't step when in romstage main function of MohonPeak
by Patrick Georgi 27 Mar '15

27 Mar '15

Hi Hook Guo, 2015-03-27 11:11 GMT+01:00 郭佳 <yunyuaner(a)gmail.com>: > At the time this main function has been called, the Cache as RAM has been setup > by FSP, and the MTRR_PHYSBASE0 is FEF0_0006. > BTW: (1) Using the debugger's memory window, I can see Cache as RAM region of > temporary stack are full of A5 5A, is it the correct case? For FSP related questions you should ask your Intel developer relations contact or sales representative. FSP isn't open source, and so we can't help you since we have no idea what it does either, and even if people knew, there also isn't a lot of interest within the coreboot community to provide free support for components like these. Thank you for your understanding, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Graham Law, Christine Elizabeth Flores

1 0

[Rangeley C2000] Can't step when in romstage main function of MohonPeak
by 郭佳 27 Mar '15

27 Mar '15

Hi, I'm debugging with Arium XDP3e debugger on ADI target board(MohonPeak based). The coreboot.rom can bring target board up successfully in case of XDP not plugged. However, when stepping with debugger, the C code main function of romstage can't be stepped, it always failed and the cpu goes into uncertain state. The main function of C code is at src/southbridge/intel/fsp_rangeley/romstage.c. At the time this main function has been called, the Cache as RAM has been setup by FSP, and the MTRR_PHYSBASE0 is FEF0_0006. The following is show in debugger: void main(FSP_INFO_HEADER *fsp_info_header) 45 { main: 0008:FFC074E5 55 PUSH EBP 0008:FFC074E6 89E5 MOV EBP,ESP 0008:FFC074E8 56 PUSH ESI 0008:FFC074E9 53 PUSH EBX 0008:FFC074EA 83E4F0 AND ESP,fffffff0 0008:FFC074ED 83EC20 SUB ESP,00000020 46 uint32_t pm1_cnt; 47 uint16_t pm1_sts; 48 uint32_t fd_mask = 0; 0008:FFC074F0 C744241C00000000 MOV dword ptr [ESP]+1c,00000000 when step line 48: uint32_t fd_mask = 0, the cpu goes into uncertain state. Since temporary stack has been setup, why should this instruction fail? You can see the assembly form: MOV dword ptr [ESP] + 1c, 00000000, The value of [ESP] + 1c is FEF03FDC, it's the cache region, and I can even modify this address in debugger's memory window, but it's wired that the debugger can step and go through :-(. BTW: (1) Using the debugger's memory window, I can see Cache as RAM region of temporary stack are full of A5 5A, is it the correct case? (2) When using debugger, does the PCH_Straps in SPI Flash descriptor executed as normal start up case? Please help me, thanks! Sincerely, Hook Guo

1 0

[GSoC] End user flash tool - GUI framework/library
by Łukasz Dmitrowski 26 Mar '15

26 Mar '15

Hello, To provide easy and clear interface for end user flash tool(http://www.coreboot.org/Project_Ideas#End_user_flash_tool) I plan to implement GUI with use of Qt framework. I decided to go with Qt because I already have experience with writing Qt applications, it is multi-platform and easy to use, development with Qt goes fast and it also has nice documentation. I tried wxWidgets once, but did not like it. Maybe you have another look at it and think that Qt is for some reason not suitable? Please share your opinions. Thanks in advance. Regards, Lukasz

2 1

Re: [coreboot] 're:
by Timothy Pearson 26 Mar '15

26 Mar '15

On 03/26/2015 01:43 AM, Kushagra Kumar wrote: > :) > Can we just ban this troll already? He's earned a one-way ticket to the trash bin via filter; hopefully his name doesn't match anyone else's traffic... -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 http://www.raptorengineeringinc.com

1 0

Re: [coreboot] I like u
by ron minnich 26 Mar '15

26 Mar '15

Does someone have 1234 as a password? On Wed, Mar 25, 2015, 23:41 Kushagra Kumar <kushagra.nasa(a)gmail.com> wrote: > Love u all m dying to cm back > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

1 0

'power on after fail' on Panther (Haswell/Lynxpoint)
by Matt DeVillier 26 Mar '15

26 Mar '15

Greetings all! I was wondering if it's possible to have Panther (Asus ChromeBox - Haswell/Lynxpoint) power on when AC power connected regardless of the previous power state. Currently, the box will power on if AC power is lost and the device was powered on, but not if powered off. I have a use case where it would be convenient to be able to power on the boxes by toggling AC power (eg, the boxes are not within physical reach). I modified the CMOS default setting for 'power_on_after_fail' to be enabled and verified its status with nvramtool. I also tried modifying lpc.c/smihandler.c in the southbridge code to force MAINBOARD_POWER_ON (rather than MAINBOARD_POWER_KEEP) in all cases, to no avail. Am I approaching this from the wrong angle, or is it perhaps not possible with these boxes? thanks, Matt

2 1

Re: [coreboot] GRUB2 is too big as a payload in ThinkPad X201
by Zaolin 26 Mar '15

26 Mar '15

Hi, simply fix this problems by increasing the cbfs size in menuconfig under the chipset section. Regards Zaolin > Dear Iru, > > > welcome to coreboot! > > > Am Donnerstag, den 26.03.2015, 09:33 +0800 schrieb Iru Cai: > > I tried to use GRUB2 as a payload when building coreboot for ThinkPad X201, > > but it's too big to fit into the rom. The GRUB2 coreboot image without > > modules is 2.8M and >800K after compressing, it's still too big. > > building GRUB directly, I get a different result. > > $ git describe > grub-2.02-beta2-372-g5974d4b > $ ./autogen.sh > $ ./configure --with-platform=coreboot --enable-boot-time --enable-cache-stats > $ make > $ edit Makefile > > Now adapt the rule `default_payload.elf`. > > default_payload.elf: grub-mkstandalone grub-mkimage > pkgdatadir=. ./grub-mkstandalone --grub-mkimage=./grub-mkimage -O i386-coreboot -o $@ --modules='ahci pata ehci uhci ohci usb_keyboard usbms part_msdos xfs ext2 fat at_keyboard part_gpt usbserial_usbdebug cbfs' --install-modules='ls linux search configfile normal cbtime cbls memrw iorw minicmd lsmmap lspci halt reboot hexdump pcidump regexp setpci lsacpi chain test serial multiboot cbmemc linux16 gzio echo help' --fonts= --themes= --locales= -d grub-core/ /boot/grub/grub.cfg=$(srcdir)/coreboot.cfg > > Remove the modules you don’t need. With *my* ASRock E350M1 setup, I > don’t need `pata`, `usbms`, `xfs`, `fat`, `at_keyboard`, `part_gpt` and > `usbserial_usbdebug`. I then add `boottime` and `cacheinfo`. > > $ make default_payload.elf > > The file is now 578K big and in CBFS the compressed size is a little > over 200 KB. > > $ build/cbfstool build/coreboot.rom print > […] > fallback/payload 0x5c400 payload > 205851 > […] > > […] > > > Thanks, > > Paul > > > PS: I’d be great if you could just send plain text messages with no HTML > parts to mailing lists. > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

2 1

GSoC 2015 application from Kushagra (was: the key to ultimate solution)
by Paul Menzel 26 Mar '15

26 Mar '15

Dear Kushagra, only by chance I looked at the untitled attachment, which contains your GSoC 2015 application. I think you need to use the Melange(?) Web interface to turn in your application. Thanks and good luck, Paul PS: You wrote a lot of messages to the mailing list in the last days. Unfortunately most of those were hard to understand and the use of the content for all the subscribers was not obvious. At least to myself. Please think more about what messages actually concern all the list subscribers. PPS: Please send just plain text message with no HTML parts to mailing lists. PPPS: Please use descriptive subject lines!

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2015