On 09/17/14 21:26, Aaron Durbin wrote:
> On Wed, Sep 17, 2014 at 4:29 AM, DM365 <1395158558(a)qq.com> wrote:
>> I'm trying to investigate Coreboot and intel FSP in minnowmax board
>> ,followed by
>> But ,the uart log show :
>> Payload being loaded below 1MiB without region being marked as RAM
>> Could not find a bounce buffer...
>> Could not load payload
This happens if you make a ROM image without the IFD (Intel Flash
I had the same problem.
We need to preserve the existing Intel Flash Descriptor & TXE binary.
Our current ASrock H81 Pro BTC mainboard have faulty firmware. Using
acpidump, ACPI FADT declares that PCIe ASPM Not Supported in Boot Flags
bit #4. Despite that the PCIe hardware does support ASPM when flipping
the PCI registers manually.
Asrock does not seem to understand and/or is not willing to turn this
bit to off (=fix the issue) in their AMI based BIOS/firmware.
When having Coreboot and Linux as payload how will that affect ACPI
(FADT table) boot flags?
On Wed, Sep 17, 2014 at 10:05 AM, ron minnich <rminnich(a)gmail.com> wrote:
> So, in other words, this is one of those chipsets that is impossible
> to make free of blobs, even if we do a full non-FSP coreboot port?
That's orthogonal to this discussion, but I wouldn't dream of running
baytrail w/o all these firmwares. I think you'd be lucky if anything
worked w/o loading all this code.
I am currently working on helping the Chromium team get their coreboot
patches upstreamed so I thought I should introduce myself to the community.
My name is Isaac Christensen and I've been working for Sage Electronic
Engineering since October. These will be my first pushes up to coreboot.org
so if you have any comments on process or workflow feel free to let me know
as I'm still learning.
I have created a review for this on Gerrit.
On Wed, Sep 17, 2014 at 11:57 AM, Chauhan, Himanshu <hschauhan(a)nulltrace.org
> Yes, this is for FILO.
> On Wed, Sep 17, 2014 at 11:53 AM, ron minnich <rminnich(a)gmail.com> wrote:
>> Is this for filo?
> = Himanshu =
= Himanshu =