coreboot April 2014

coreboot@coreboot.org

42 participants
85 discussions

Re: [coreboot] Bug in your code
by ron minnich 18 Apr '14

18 Apr '14

Fooey. Now they all look wrong. I think the macro maybe should be defined as makemagic(b0,b1,b2,b3) the thing I can't figure out is why this ever worked. OK, off to the dentist, ... ron On Fri, Apr 18, 2014 at 8:34 AM, ron minnich <rminnich(a)gmail.com> wrote: > Which of course means my code IS wrong, but the suggested fix is wrong > too I think. > > ron > > On Fri, Apr 18, 2014 at 8:34 AM, ron minnich <rminnich(a)gmail.com> wrote: >> Still not seeing it. >> >> I think the order should be >> ' ', 'S', 'S', 'B' >> >> not ' ', 'B'','S','S' >> or 'B','S','S',' ' >> >> i.e. space is the high order byte. >> >> ron >> >> >> >> On Fri, Apr 18, 2014 at 8:21 AM, Nico Huber <nico.h(a)gmx.de> wrote: >>> On 18.04.2014 16:49, ron minnich wrote: >>>> >>>> Can somebody give me a sanity check? I can't see the error with the macro. >>>> I won't say too much here -- just take a look. I'm not convinced the >>>> code is wrong. >>> >>> Well, I'm convinced :P >>> Have a closer look at the placement of the space. It was next to the latter >>> S (0x2053...) now it stands before the B (' ', 'B', ...). >>> >>> Nico >>> >>> >>>> >>>> thanks >>>> >>>> ron >>>> >>>> On Fri, Apr 18, 2014 at 7:39 AM, WANG FEI <wangfei.jimei(a)gmail.com> wrote: >>>>> >>>>> Ronald, >>>>> >>>>> I just noticed a bug in your code, I've added the comment to coreboot >>>>> review >>>>> syste, but I'm not farmilar with this system, not sure if it will send >>>>> you a >>>>> notice mail automatically, so I just send you a mail to inform you this. >>>>> >>>>> Here is the link of comment, >>>>> http://review.coreboot.org/#/c/5098/ >>>>> >>>>> -Fei >>>> >>>> >>>

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Re: [coreboot] Bug in your code
by ron minnich 18 Apr '14

18 Apr '14

Which of course means my code IS wrong, but the suggested fix is wrong too I think. ron On Fri, Apr 18, 2014 at 8:34 AM, ron minnich <rminnich(a)gmail.com> wrote: > Still not seeing it. > > I think the order should be > ' ', 'S', 'S', 'B' > > not ' ', 'B'','S','S' > or 'B','S','S',' ' > > i.e. space is the high order byte. > > ron > > > > On Fri, Apr 18, 2014 at 8:21 AM, Nico Huber <nico.h(a)gmx.de> wrote: >> On 18.04.2014 16:49, ron minnich wrote: >>> >>> Can somebody give me a sanity check? I can't see the error with the macro. >>> I won't say too much here -- just take a look. I'm not convinced the >>> code is wrong. >> >> Well, I'm convinced :P >> Have a closer look at the placement of the space. It was next to the latter >> S (0x2053...) now it stands before the B (' ', 'B', ...). >> >> Nico >> >> >>> >>> thanks >>> >>> ron >>> >>> On Fri, Apr 18, 2014 at 7:39 AM, WANG FEI <wangfei.jimei(a)gmail.com> wrote: >>>> >>>> Ronald, >>>> >>>> I just noticed a bug in your code, I've added the comment to coreboot >>>> review >>>> syste, but I'm not farmilar with this system, not sure if it will send >>>> you a >>>> notice mail automatically, so I just send you a mail to inform you this. >>>> >>>> Here is the link of comment, >>>> http://review.coreboot.org/#/c/5098/ >>>> >>>> -Fei >>> >>> >>

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Re: [coreboot] Bug in your code
by Nico Huber 18 Apr '14

18 Apr '14

On 18.04.2014 16:49, ron minnich wrote: > Can somebody give me a sanity check? I can't see the error with the macro. > I won't say too much here -- just take a look. I'm not convinced the > code is wrong. Well, I'm convinced :P Have a closer look at the placement of the space. It was next to the latter S (0x2053...) now it stands before the B (' ', 'B', ...). Nico > > thanks > > ron > > On Fri, Apr 18, 2014 at 7:39 AM, WANG FEI <wangfei.jimei(a)gmail.com> wrote: >> Ronald, >> >> I just noticed a bug in your code, I've added the comment to coreboot review >> syste, but I'm not farmilar with this system, not sure if it will send you a >> notice mail automatically, so I just send you a mail to inform you this. >> >> Here is the link of comment, >> http://review.coreboot.org/#/c/5098/ >> >> -Fei >

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Re: [coreboot] Bug in your code
by ron minnich 18 Apr '14

18 Apr '14

Can somebody give me a sanity check? I can't see the error with the macro. I won't say too much here -- just take a look. I'm not convinced the code is wrong. thanks ron On Fri, Apr 18, 2014 at 7:39 AM, WANG FEI <wangfei.jimei(a)gmail.com> wrote: > Ronald, > > I just noticed a bug in your code, I've added the comment to coreboot review > syste, but I'm not farmilar with this system, not sure if it will send you a > notice mail automatically, so I just send you a mail to inform you this. > > Here is the link of comment, > http://review.coreboot.org/#/c/5098/ > > -Fei

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Re: [coreboot] Blog post by Scott D.: Small Integers: Big Penalty
by mrnuke 18 Apr '14

18 Apr '14

On Thursday, April 17, 2014 12:41:39 PM ron minnich wrote: > Paul, very nice, thanks. It's not real surprising, actually, at least > in my old scientific computing world. > > Since that is AMD code, maybe we can get the guys who wrote it to read > that nice book written by AMD :-) > OUCH! Right under the belt. ;) Alex

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Blog post by Scott D.: Small Integers: Big Penalty
by Paul Menzel 17 Apr '14

17 Apr '14

Dear coreboot folks, in the IRC channel #coreboot, Patrick linked to an interesting blog post from Scott from 2012 with the title *Small Integers: Big Penalty* [1]. At least to me the results were unexpected. Thanks, Paul [1] http://notabs.org/coding/smallIntsBigPenalty.htm

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So, you want to try coreboot? Here are a few hints
by mrnuke 17 Apr '14

17 Apr '14

Installing coreboot can be an either enthralling or appalling experience. If you're new to coreboot and want to give it a try, following a few simple steps can save you a ton of time and frustration. Ask around first ================ Let the "coreboot people" know you want to try coreboot on board 'xyz'. You may find someone with the same board, who may be able to give you hints on flashing. This is especially useful on laptops, where a brick will most likely result in the need for disassembly to access the flash chip, and external flashing. Prebuilt images =============== If you're lucky enough to find someone with the same board as you, they may be able to provide a pre-built coreboot image. This eliminates issues where flashing is done correctly, but a mysterious bug prevents the system for booting. Binary coreboot distributions ============================= Sometimes people get together and create tested binaries binaries for a subset of boards. They can give you help on flashing, and making sure your board works as expected. This is by far the best way to try coreboot. If you have a Lenovo X60, give the libreboot[1] guys a holler. That's libre- boot, not lib-reboot. You may also be able to find, for a fee, prebuilt binaries for your board from Sage Electronics' SageBios[2]. I am not sure how Sage conducts its business, so Marc, feel free to correct me on this one. [1] http://libreboot.org/ [2] http://www.se-eng.com/sage-bios.html

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Re: [coreboot] [proposal] EC-mainboard interaction at ASL level
by mrnuke 16 Apr '14

16 Apr '14

On Tuesday, April 08, 2014 08:32:46 AM Duncan Laurie wrote: > If we do go the route of having lots of mainboard handlers I think we > should keep the method names consistent with the ACPI spec and use a > mainboard namespace to separate them. Conditional references are > already a headache in ASL and I think relying on the preprocessor > would make things worse. > > Scope (\_SB.MB) > // Lid open > Method (LIDO) { ... } > // Lid closed > Method (LIDC) { ... } > // Increase brightness > Method (BRTI) { ... } > } > Duncan, this is genius. It simplifies the ASL quite a bit, even if some of said methods are stubs. Looking at some code actual code [1][2], this method is very clean and straightforward. I vote for this approach. Alex [1] http://review.coreboot.org/#/c/5515/ [2] http://review.coreboot.org/#/c/5517/1/src/mainboard/hp/pavilion_m6_1035dx/a…

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Re: [coreboot] Fans and BIOS
by Stefan Reinauer 15 Apr '14

15 Apr '14

* Vitor Augusto <vitorafsr(a)gmail.com> [140412 03:04]: > Hello. > > I'm searching for any information about where (memory, IO port, etc.) > the status (on or off) of the fans of a laptop are stored. Anything is > very welcome! This is to improve the compatibility of i8kutils package > at Linux. The site of the development is > "https://launchpad.net/i8kutils". Hi Vitor, FAN speed is usually controlled by the EC / SuperIO. There is no generally available unified interface for that like Dell's SMM interface. You might want to look at the ACPI interface to get something more unified. Controlling hardware directly will be a lot of work for all the devices out there. Stefan

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Re: [coreboot] ASRock E350M1 start automatically after a electric cut
by Felix Held 15 Apr '14

15 Apr '14

>> Have a look at the power loss control bits inside the superio chip. They >> specify what to do when the mainboard gets its standby power. > Okay, but how please? Haven't read enough of the coreboot source code to be able to say if and where those bits are written by coreboot. They are in the LDN A of the SIO chip, bits 5 and 6 in CR E4h. See the SIO datasheet. Since VRTC is the power well for that unit of the chip, removing the power and the BIOS battery for a minute should reset those bits to 0. Regards Felix I wonder why my mail client doesn't use the address the mails from the mailing list are delivered to as address in the from field...

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coreboot April 2014