coreboot April 2014

coreboot@coreboot.org

42 participants
85 discussions

Re: [coreboot] USB tick in SMM?
by David Hubbard 29 Apr '14

29 Apr '14

On Tue, Apr 29, 2014 at 11:36 AM, ron minnich <rminnich(a)gmail.com> wrote: > Anybody out there know typical numbers for the timer tick if USB is > active as part of SMM? > > I just heard one number for one product line, 8 HZ. We're seeing a > mysterious 18 HZ tick on one system. Any other numbers people know? > 18.2 Hz is legacy stuff, http://wiki.osdev.org/Programmable_Interval_Timer- but the particulars of an SMM implementation might just as well be a copy-paste error, for all I know. An OHCI driver might use a timer tick to recover after a timeout. The USB spec doesn't specify all the timeouts, though multiples of 100ms are common (so a ~10HZ timer might be useful). Hope that helps, David

1 0

USB tick in SMM?
by ron minnich 29 Apr '14

29 Apr '14

Anybody out there know typical numbers for the timer tick if USB is active as part of SMM? I just heard one number for one product line, 8 HZ. We're seeing a mysterious 18 HZ tick on one system. Any other numbers people know? thanks ron

1 0

Re: [coreboot] Fans and BIOS
by WANG Siyuan 28 Apr '14

28 Apr '14

Hi Vitor, Amd Parmer and Olivehill support FAN control. EC is used in these boards to control fan speed. Yours sincerely, WANG Siyuan On Sat, Apr 12, 2014 at 9:04 AM, Vitor Augusto <vitorafsr(a)gmail.com> wrote: > Hello. > > I'm searching for any information about where (memory, IO port, etc.) > the status (on or off) of the fans of a laptop are stored. Anything is > very welcome! This is to improve the compatibility of i8kutils package > at Linux. The site of the development is > "https://launchpad.net/i8kutils". > > Thanks in advance. > > Vitor Augusto > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

1 0

IMB-A180E H coreboot won't boot
by Mark C. Mason 28 Apr '14

28 Apr '14

I'm new to coreboot, and I'm working to use it with an ASROCK IMB-A180, the H version with the LVDS port. I've read previous posts regarding the "IMB-A180 won't boot" on this group, and tried the .config that was posted, but the result is the same. The debugging output shows things progressing until agesawwrapper_amdinitmid is called, then the boot restarts, then stops cold at the same point: PCI: 00:18.4 PCI: 00:18.5 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1095130 exit 0 POST: 0x74 Enabling resources... Fam16 - domain_enable_resources: AmdInitMid. agesawrapper_amdinitmid ^@^@^@^@§H¨Hh½É<95><89>½½Ñµ4.0-5169-g9d1d740 Tue Feb 4 16:46:38 PST 2014 starting... Any help with this would be greatly appreciated. Full serial debug output then .config are attached below. Best regards, Mark Mason Engineering Design Team

2 1

S3 Resume on AMD Trinity APU
by mrnuke 28 Apr '14

28 Apr '14

For those of you with Trinity CPUs, coreboot, and working S3 resume, is it necessary to run the VGA option ROM on S3 resume to get video back? Which output are you using (VGA, DP, etc) ? Alex

3 2

Opensource programs. ReactOS Community Edition.
by Victor Martinez 28 Apr '14

28 Apr '14

As you may know ReactOS is now working in the new ReactOS Community Edition. It's a new OS, with new features, redesigned image, powered by the new ReactOS kernel which boosts its compatibility with apps and drivers. You can see a comparative, and the new site here: http://community.reactos.org/index.php/features/reactos-0-4 In the spirit of open source we created a special "Open Source Support Program" available only for open source projects. And, of course, absolutely free. Its main objective is to promote your app and show the users that there are "other" alternatives out there and apps waiting to be discovered! But not only that, there are other nice features that you shouldn't miss, because they are free after all. We've (literally) chained a designer into a dark wet basement for a week to create some designs which explain not just the "Opensource Support Program", but also the "Official Software Support" program, which you can join for free too. Make him happy by watching his artwork! http://community.reactos.org/programs/opensource.pdf We hope you will like and consider joining any of these new programs. Since we're planning ahead, we had to set some deadlines in the doc. Don't miss the date! Any comments, suggestions and enhancements are really appreciated so we can expand the features and make them even better. Also we're crowdfunding right now to make ReactOS Community Edition happen ASAP, so any help in spreading the word is most welcome! http://igg.me/at/reactos/x/6842466 Thank you for reading and for "reacting" to the email ;) Disclaimer: No designer was harmed in the making of the attached document. He is recovering well! ;) Víctor Martínez Calvo (EN/ES/DE/FR) Programs & Partnerships Coordinator http://community.reactos.org

1 0

Re: [coreboot] ASRock E350M1 start automatically after a electric cut
by HacKurx 26 Apr '14

26 Apr '14

Hi, Sorry for the late reply. Tue Apr 15 08:42:36 CEST 2014, Paul : > The problem is probably that you have `USE_OPTION_TABLE` selected, where > the default is to restart on powerloss. The default option is "# CONFIG_USE_OPTION_TABLE is not set". I activated this option "CONFIG_USE_OPTION_TABLE=y" and I encounter no problems since :) Thanks you very much, best regards

1 0

Thoughts or conclusions on coreboot and link time optimization (LTO)?
by Paul Menzel 24 Apr '14

24 Apr '14

Dear coreboot folks, in #coreboot on <irc.freenode.net> Stefan mentioned that link time optimization (LTO) [1] might yield some speed improvements for coreboot as the resulting firmware image might be smaller and therefore it takes less time to read it from flash. As LTO has been greatly improved in GCC 4.9.0 and is all over the news, has somebody already experimented with LTO or created patches or tools for testing? Is somebody able to share conclusions already? That’d be very interesting. Thanks, Paul [1] http://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html (search for `lto`)

1 1

Coreboot crossgcc won't build without allow other toolchains enabled
by lists＠derpeter.net 22 Apr '14

22 Apr '14

Hi, if i try to build the cross gcc (make crossgcc) make tells me to use the coreboot tool chain. This behavior seems to be a result of comit 9b0de . With "allow other toolchains" enabled i can build crossgcc. I assume the toolchain check needs to be disabled for cross gcc or only enabled for coreboot itself and payloads. cheers derpeter

1 0

Re: [coreboot] Life hack #37: how to make a great touchpad
by David Hendricks 21 Apr '14

21 Apr '14

On Mon, Apr 21, 2014 at 8:55 AM, David Hubbard < david.c.hubbard+coreboot(a)gmail.com> wrote: > Agree 100%. On a slightly related note, the touchpad identifies itself as >> "SynPS/2 Synaptics Touchpad," though I'm not 100% sure it's a synaptics >> device. >> > It depends which Chromebook you are using, as there are a variety of touchpads used from Synaptics, Cypress, Atmel, etc. Also, make sure the chromeos_laptop kernel module is loaded. As Ron pointed out, this is really not an appropriate forum to get help on touchpad issues. I suggest chromium-os-discuss mailing list for that: https://groups.google.com/a/chromium.org/forum/#!forum/chromium-os-discuss > I foundnd the mouse moved ever so slightly when I touched or released the > pad -- so I changed the expected finger size: > > xinput | grep 'SynPS/2' # to get the device id, should be 11 > xinput list-props 11 > > # change "Synaptics Finger (271)" > xinput --set-prop 11 37 42 0 # 37=min size of a finger, 42=max size of a > finger > > # the previous value was: xinput --set-prop 11 25 30 0 > > David > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

1 0

← Newer
1
2
3
4
5
6
7
8
9
Older →

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2014