Am Mittwoch, den 12.06.2013, 01:00 +0300 schrieb matti christensen:
> how about - say - wyse s50 thin client that is supported according to
> your pages ?
> i would like to find something cheap, small power consumption, small size ...
I can also recommend the ASRock E350M1 .
Hi, try to collect information about the chromebooks to write things up
in the wiki.
Which of the following things are true (for the lastest coreboot version):
0. all 5 Chromebooks are supported by coreboot
(http://www.google.com/intl/en/chrome/devices/chromebooks.html) Ok 5
names show in the config menu, so are there maybe unsupported older
version of the chromebooks (ones with other working names then
1. Butterfly (BOARD_GOOGLE_BUTTERFLY) (NEW)
2. Link (BOARD_GOOGLE_LINK) (NEW)
3. Parrot (BOARD_GOOGLE_PARROT) (NEW)
4. Snow (BOARD_GOOGLE_SNOW) (NEW)
5. Stout (BOARD_GOOGLE_STOUT) (NEW)!
1. all chromebooks need to be flashed by an external programmer to get
your own coreboot version (and payload) running (but it is doable
without breaking things)
Is there information about where the spi chips can be found?
which ones don't require any proprietary drivers?
I have some troubles with southbridge i82801gx.
I can boot Windows on my board, but S3 from OS doesn't work properly if i resume with USB keyboard.
In this case, i have Wake signal and coreboot starts to boot, but it stucks with endless messages about SMI# "GPE0_STS: USB1":
These messages come from file "\southbridge\intel\i82801gx\smihandler.c", function "dump_gpe0_status".
According to i82801gx datasheet:
USB1_STS - R/WC. Software clears this bit by writing a 1 to it.
0 = USB UHCI controller 1 does Not need to cause a wake.
1 = Set by hardware when USB UHCI controller 1 needs to cause a wake. Wake event
will be generated if the corresponding USB1_EN bit is set.
Clearing of GPE0_STS bits properly done in function reset_gpe0_status
* @brief read and clear GPE0_STS
* @return GPE0_STS register
static u32 reset_gpe0_status(void)
reg32 = inl(pmbase + GPE0_STS);
/* set status bits are cleared by writing 1 to them */
outl(reg32, pmbase + GPE0_STS);
So... i can't really understand, why does this SMI# appear again and again?
i would like to have an open source system - that is the issue.
i'm a minimalist = there is no need for gigahetzes
there may not be a single intel branded chip or gizmo on the board ( via,
amd or whatever else )
Many thanks for your comments
matti christensen wrote:
> i broke the motherboard = once again tried to change the bios chip
> and ripped socket off the board
> i really am nearly crying - i am 56 years old and it appears that i
> am never gonna have a truly free system
It might still be possible to repair the mainboard, but it is always
easiest to start out with a mainboard that is already well supported
and then go further from there.
so, what is ur question?
can u please tell which is properly the cpu and mobo?
On 10 June 2013 03:00, 朱晓元 <rogerzhu1127(a)gmail.com> wrote:
> CPU: haswell
> chipset:lynxpoint c226
> I use Intel wtm2 board.
> SATA controller in ahci mode.
> disk can be detect but no phy link.
> log file see attach.
> coreboot mailing list: coreboot(a)coreboot.org
> - the basic issue is that after following your pages, coreboot won't boot
I'm sorry to hear that. There can be many things going wrong (configuration,
missing files, toolchain failing). I'm not familiar with the PC2500E but
maybe I can help checking your configuration. Please paste your coreboot's
.config, and .config of libpayload (normally in payloads/libpayload/), and
.config of FILO (payloads/external/FILO/filo/).
Did you add a VGA BIOS to coreboot? If not, you might just not seeing
anything, even if coreboot boots. AFAIK, without a VGA BIOS, you won't
see anything until Linux loads the openchrome driver.
> - i have not yet tried to get output w serial console but try to
> follow previous hint to do 'make crossgcc'
The serial output of coreboot is always worth a look if something goes
wrong. If rebuilding coreboot with the reference toolchain doesn't help,
this is where to start, IMO.
> - as i try to do 'make crossgcc' the system appears to go to loop =
> now it has been trying for an hour with only output on attached
> make_crossgcc_out / make_crossgcc_err
There was a bug just fixed in upstream coreboot . I guess, it is what
was causing the loop you experienced.
Please try again with current coreboot master. If you didn't change any
coreboot source, you can just do
in your coreboot directory. If you did changes, commit them and try to
git fetch origin master
git rebase FETCH_HEAD
Then build crossgcc and rebuild coreboot:
make crossgcc # Takes some time, but you should see more output
I hope that helps,