coreboot June 2013

coreboot@coreboot.org

45 participants
86 discussions

Re: [coreboot] Native init for AMD cards
by David Hubbard 20 Jun '13

20 Jun '13

Hi Ron, Rudolf, I've attached a shell script that does the first part of preparing the in-kernel radeon driver for coreboot. I settled on a shell script after thinking about what coccinelle is best used for. It does look like coccinelle could do what ctags does, namely, find function definitions. However ctags has the advantage of automatically filtering out function calls that refer to any other part of the kernel (ctags only lists where the function is *defined* in the 'tags' file it outputs). The output of this script is a coccinelle .spatch that I don't actually expect to work yet. I'll become more confident with coccinelle as I use it more. I wanted to send this as a question -- What do you think is the best way to slice up the in-kernel radeon driver? This script relies on very few special cases which should hopefully make the code reuse as painless as possible. The special cases: 1. Rename the #define radeon_init() in drivers/gpu/drm/radeon/radeon.h 2. Find struct radeon_asic initializers in drivers/gpu/drm/radeon/radeon_asic.c After this auto-generated coccinelle .spatch, the source tree needs manual spatches applied to change kernel API calls to coreboot API calls. After looking for any pitfalls, that would be the next thing to do. Regards, David

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Re: [coreboot] Fixed the bug of rs780 gfx port A
by Denis 'GNUtoo' Carikli 20 Jun '13

20 Jun '13

On Tue, 18 Jun 2013 14:53:09 -0600 David Hubbard <david.c.hubbard+coreboot(a)gmail.com> wrote: > ASUS M4A785T-M: contact GNUtoo I cannot test right now: I'm relocating and while I took my mainboard, I don't have a power supply for it. Denis.

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ACPI: S3 wakeup from USB keyboard
by Константин Аладышев 20 Jun '13

20 Jun '13

I am trying to enable S3 wakeup from USB keyboard in Linux. After boot, if i execute in terminal command <cat /proc/acpi/wakeup> i get: Device S-state Status Sysfs node PCI0 S5 disabled no-bus:pci0000:00 HDEF S4 disabled pci:0000:00:1b.0 RP01 S5 disabled pci:0000:00:1c.0 RP02 S5 disabled pci:0000:00:1c.1 RP03 S5 disabled pci:0000:00:1c.2 RP04 S5 disabled pci:0000:00:1c.3 RP05 S5 disabled pci:0000:00:1c.4 RP06 S5 disabled pci:0000:00:1c.5 USB1 S3 disabled pci:0000:00:1d.0 USB2 S3 disabled pci:0000:00:1d.1 USB3 S3 disabled pci:0000:00:1d.2 USB4 S3 disabled pci:0000:00:1d.3 EHC1 S3 disabled pci:0000:00:1d.7 MODM S4 disabled COMA S3 disabled pnp:00:08 COMB S3 disabled pnp:00:09 At my guess, current devices are devices from DSDT table with _PRW method. But for some reason (why?) wakeup for them disabled by default. I can enable wakeup for keyboard (in my case it is USB1) with: echo PCI0 > /proc/acpi/wakeup echo USB1 > /proc/acpi/wakeup Throught some experiments i figured out, that these commands says to OS, that it should enable appropriate bits in ACPI GPE0_EN register before going to S3 (what bits exactly is defined in PCI0._PRW and USB1._PRW) But this is not the end. I think OS power off USB controller when it goes to S3. To fix this i found device USB number from dmesg: [ 2.724374] input: LITEON Technology USB Multimedia Keyboard as /devices/pci0000:00/0000:00:1d.0/usb2/2-2/2-2:1.0/input/input6 And executed command <echo enabled > /sys/bus/usb/devices/2-2/power/wakeup> And only now wakeup from USB fully works. My question is, how i should change DSDT/BIOS, to avoid all of these commands? I think main problem is a lack of something in DSDT. Some fragments from current DSDT: ... Device (USB1) { Name(_ADR, 0x001D0000) Name(_PRW, Package(0x02){ 0x03, 0x03 }) Method(_S3D,0) { Return(2) } } ... Scope (\_GPE) { .. // USB1 Method (_L03, 0) { Notify (\_SB.PCI0.USB1, 0x02) } .. }

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Fixed the bug of rs780 gfx port A
by yili0568＠gmail.com 18 Jun '13

18 Jun '13

I've tested it on loongson 3aserver mainboard, but I don't have a x86 mainboard, is there anyone test the patch for me on a x86 mainboard, thanks.

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Re: [coreboot] Haswell support
by 朱晓元 18 Jun '13

18 Jun '13

z87 chipset may work,but need some work on coreboot code. use intel/wtm2 mobo. 2013/6/17 ron minnich <rminnich(a)gmail.com> > looking at the current tree, Z87 would appear to be in there. > > What board are you looking at? > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] coreboot project analysis request
by ron minnich 17 Jun '13

17 Jun '13

coverity sounds good

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Re: [coreboot] Welcome GSoC Students!
by Marc Jones 17 Jun '13

17 Jun '13

Hello students and mentors: I hope that you are all starting to engage your mentors and refine your GSoC plans during the "get acquainted" phase. Students should be exchanging emails with mentors and in IRC to participate in the development process. Thanks for the introductory blog posts. I really liked the posts from kmalkki and mrnuke. First blog post done: Kyösti (kmalkki) Stefan (stefanct) Alex G (mrnuke) Need to do a blog post: Alex Ayush Sagar Marc -- http://se-eng.com

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Re: [coreboot] coreboot project analysis request
by Антон Кочков 17 Jun '13

17 Jun '13

Hello! Sadly no answer from Klocwork... Ok, what do you think about Coverity? I mean this one http://scan.coverity.com/ It could be a good addition to this https://www.google-melange.com/gsoc/project/google/gsoc2013/alex_animux/760… Radare2 is already scanning by Coverity (a few days). Best regards, Anton Kochkov. On Fri, Apr 12, 2013 at 1:32 PM, Антон Кочков <anton.kochkov(a)gmail.com> wrote: > Good day! > > As I did not get a reply to my message from April 3rd I am trying it again. > > Is it possible to add the coreboot project https://www.coreboot.org to your > free analysis of FOSS projects? > > As an alternative to the BIOS and UEFI, coreboot and its payloads need and > want to be as secure as possible to also outdo UEFI in the security aspect. > So code analysis to find out any issues would help coreboot very much. > > Here is the code > > git clone http://review.coreboot.org/p/coreboot.git > > Under the directory `payloads/` there are some programs which are started > after coreboot has finished. Under the directory `util/` there are several > utilities needed for image creation or for board porting. > > As a build system, a customized Kconfig is used and there is also the build > tool named abuild.. > > If you have any question, please do not hesitate to ask us. Either on our > mailing list http://www.coreboot.org/Mailinglist or myself. > > The coreboot project and I hope, you are going to help us and are looking > forward to what you are going to find. > > > Best regards, > > Anton Kochkov. > > > PS: If you know any students interested in low level stuff please tell them, > that coreboot is participating in Google Summer of Code 2013 > http://www.coreboot.org/GSoC . >

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Haswell support
by Eric Sherouse 16 Jun '13

16 Jun '13

Per advice of the #coreboot channel, I will ask this question here. Does coreboot support intel's haswell arch, specifically the z87 chipset?

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Problem with coreboot+SeaBIOS on Samsung Chromebox (stumpy)
by Robert Ou 15 Jun '13

15 Jun '13

Hello, I tried to build and flash coreboot and SeaBIOS onto a Samsung Chromebox. I built coreboot from master of the coreboot tree (no chromiumos patches). My problem is that the Chromebox now only boots from a complete cold boot. In other words, I need to unplug both the AC power and the RTC battery, then plug in the AC power, and then push the power button. If I run "shut down" from Ubuntu and try to press the power button, the board does not boot. If I hold the power button until the box shuts off and push the power button again, it also does not boot. If I suspend from Ubuntu, the box suspends and the blue LED starts blinking. However, if I push the power, it doesn't resume. One thing I observed is that all the boots that don't work involve the power LED either never turning on or turning on instantly. The complete cold boot that does work has the power LED blinking very briefly, turning off for several seconds, and then turning back on. Does anybody know what is going on here? Attached is a cbmem console log of a successful boot, but I don't know how to get console logs from failed boots. Robert

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coreboot June 2013