coreboot November 2012

coreboot@coreboot.org

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895 discussions

Patch set updated for coreboot: 3665ace libpayload: Remove unused FLAG_USED from memory allocator
by gerrit＠coreboot.org 30 Nov '12

30 Nov '12

just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1949 -gerrit commit 3665ace13de68e798de31499197cc600d2426967 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Oct 8 15:03:35 2012 +0200 libpayload: Remove unused FLAG_USED from memory allocator The FLAG_USED bit in the memory allocator's header type was never read. This removes it to save one bit for the region size so we can have heaps of up to 32MiB. Change-Id: Ibd78e67d79e872d6df426516667c795fd52326d5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/1942 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/libpayload/libc/malloc.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 82bae3c..7756a3b 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -37,6 +37,9 @@ * We're also susceptible to the usual buffer overrun poisoning, though the * risk is within acceptable ranges for this implementation (don't overrun * your buffers, kids!). + * + * The header format (hdrtype_t) supports heaps of up to 32MiB (given that int + * is 32 bits long). */ #define IN_MALLOC_C @@ -51,14 +54,15 @@ typedef unsigned int hdrtype_t; #define MAGIC (0x2a << 26) #define FLAG_FREE (1 << 25) -#define FLAG_USED (1 << 24) +#define SIZE_BITS 25 +#define MAX_SIZE ((1 << SIZE_BITS) - 1) -#define SIZE(_h) ((_h) & 0xFFFFFF) +#define SIZE(_h) ((_h) & MAX_SIZE) -#define _HEADER(_s, _f) ((hdrtype_t) (MAGIC | (_f) | ((_s) & 0xFFFFFF))) +#define _HEADER(_s, _f) ((hdrtype_t) (MAGIC | (_f) | ((_s) & MAX_SIZE))) #define FREE_BLOCK(_s) _HEADER(_s, FLAG_FREE) -#define USED_BLOCK(_s) _HEADER(_s, FLAG_USED) +#define USED_BLOCK(_s) _HEADER(_s, 0) #define HDRSIZE (sizeof(hdrtype_t)) @@ -91,7 +95,7 @@ static void *alloc(int len) /* Align the size. */ len = (len + 3) & ~3; - if (!len || len > 0xffffff) + if (!len || len > MAX_SIZE) return (void *)NULL; /* Make sure the region is setup correctly. */

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ASUS m5a88-v AGESA progress
by darkdefende＠gmail.com 30 Nov '12

30 Nov '12

I've managed to get it to boot into grub now. Seems like the problem was that I forgot to init rs780 in romstage. However now the linux kernel panics because it seems like it can find the hdds. I also managed to solve the AGESA arrests that was happening. But it doesn't seem to have any effect on the boot process. I've attatched the boot log. It would be really helpful if I could get some help as I have no idea why it can load grub and read the kernel image from disk but not read the disk themselfs for the linux kernel. Note also that it doesn't matter if I boot the disks in IDE or AHCI mode. The same error happens.

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Patch merged into coreboot/master: 3665ace libpayload: Remove unused FLAG_USED from memory allocator
by gerrit＠coreboot.org 30 Nov '12

30 Nov '12

the following patch was just integrated into master: commit 3665ace13de68e798de31499197cc600d2426967 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Oct 8 15:03:35 2012 +0200 libpayload: Remove unused FLAG_USED from memory allocator The FLAG_USED bit in the memory allocator's header type was never read. This removes it to save one bit for the region size so we can have heaps of up to 32MiB. Change-Id: Ibd78e67d79e872d6df426516667c795fd52326d5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/1942 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/1942 for details. -gerrit

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Patch merged into coreboot/master: 0227dec libpayload: Fix lookup by label in CMOS layouts
by gerrit＠coreboot.org 30 Nov '12

30 Nov '12

the following patch was just integrated into master: commit 0227dec291ac825aae514b7841bb39a936bcec77 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Nov 9 18:12:21 2012 +0100 libpayload: Fix lookup by label in CMOS layouts The condition to compare the labels was twisted. Change-Id: I34a665aa87e2ff0480eda0f249bbbea8a8fe68d8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/1941 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/1941 for details. -gerrit

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Patch set updated for coreboot: 04f11c9 Create a a new configuration variable for PCI
by Ronald G. Minnich 30 Nov '12

30 Nov '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1947 -gerrit commit 04f11c9fcd510990558dcbf4e1b0ff0eb00d0297 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Nov 29 16:28:21 2012 -0800 Create a a new configuration variable for PCI Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/Kconfig | 5 +++++ src/devices/Kconfig | 14 ++++++++++++-- src/devices/Makefile.inc | 8 ++++---- src/devices/pci_device.c | 20 ++++++++++---------- 4 files changed, 31 insertions(+), 16 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 6bb8135..29731b3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -203,6 +203,11 @@ source src/mainboard/Kconfig config ARCH_X86 bool default n + select PCI + +config ARCH_ARM + bool + default n config ARCH_ARMV7 bool diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 72e8a53..ce55392 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -175,28 +175,38 @@ config MULTIPLE_VGA_ADAPTERS bool default n -config PCI_64BIT_PREF_MEM +config PCI bool default n +config PCI_64BIT_PREF_MEM + bool + depends on PCI + default y + config HYPERTRANSPORT_PLUGIN_SUPPORT bool - default n + depends on PCI + default Y config PCIX_PLUGIN_SUPPORT bool + depends on PCI default y config PCIEXP_PLUGIN_SUPPORT bool + depends on PCI default y config AGP_PLUGIN_SUPPORT bool + depends on PCI default y config CARDBUS_PLUGIN_SUPPORT bool + depends on PCI default y config PCIEXP_COMMON_CLOCK diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9d4b391..a50926a 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -2,14 +2,14 @@ ramstage-y += device.c ramstage-y += root_device.c ramstage-y += cpu_device.c ramstage-y += device_util.c -ramstage-y += pci_device.c +ramstage-$(CONFIG_PCI) += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c -ramstage-y += pciexp_device.c +ramstage-$(CONFIG_PCI) += pciexp_device.c ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c -ramstage-y += pnp_device.c -ramstage-y += pci_ops.c +ramstage-$(CONFIG_ARCH_X86) += pnp_device.c +ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-y += smbus_ops.c romstage-y+= device_romstage.c diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index d9e6b27..ff334fe 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -756,11 +756,10 @@ struct device_operations default_pci_ops_bus = { */ static struct device_operations *get_pci_bridge_ops(device_t dev) { - unsigned int pos; - #if CONFIG_PCIX_PLUGIN_SUPPORT - pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); - if (pos) { + unsigned int pcixpos; + pcixpos = pci_find_capability(dev, PCI_CAP_ID_PCIX); + if (pcixpos) { printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev)); return &default_pcix_ops_bus; } @@ -769,10 +768,10 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) /* How do I detect a PCI to AGP bridge? */ #endif #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT - pos = 0; - while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) { + unsigned int htpos = 0; + while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) { u16 flags; - flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); + flags = pci_read_config16(dev, htpos + PCI_CAP_FLAGS); if ((flags >> 13) == 1) { /* Host or Secondary Interface */ printk(BIOS_DEBUG, "%s subordinate bus HT\n", @@ -782,10 +781,11 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) } #endif #if CONFIG_PCIEXP_PLUGIN_SUPPORT - pos = pci_find_capability(dev, PCI_CAP_ID_PCIE); - if (pos) { + unsigned int pciexpos; + pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (pciexpos) { u16 flags; - flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS); + flags = pci_read_config16(dev, pciexpos + PCI_EXP_FLAGS); switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) { case PCI_EXP_TYPE_ROOT_PORT: case PCI_EXP_TYPE_UPSTREAM:

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Patch set updated for coreboot: 394490d Create a a new configuration variable for PCI
by Ronald G. Minnich 30 Nov '12

30 Nov '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1947 -gerrit commit 394490dd032de7928f0002b7791c0d0c0b9c9cc6 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Nov 29 16:28:21 2012 -0800 Create a a new configuration variable for PCI Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/Kconfig | 5 +++++ src/devices/Kconfig | 14 ++++++++++++-- src/devices/Makefile.inc | 8 ++++---- src/devices/pci_device.c | 19 +++++++++---------- 4 files changed, 30 insertions(+), 16 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 6bb8135..29731b3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -203,6 +203,11 @@ source src/mainboard/Kconfig config ARCH_X86 bool default n + select PCI + +config ARCH_ARM + bool + default n config ARCH_ARMV7 bool diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 72e8a53..ce55392 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -175,28 +175,38 @@ config MULTIPLE_VGA_ADAPTERS bool default n -config PCI_64BIT_PREF_MEM +config PCI bool default n +config PCI_64BIT_PREF_MEM + bool + depends on PCI + default y + config HYPERTRANSPORT_PLUGIN_SUPPORT bool - default n + depends on PCI + default Y config PCIX_PLUGIN_SUPPORT bool + depends on PCI default y config PCIEXP_PLUGIN_SUPPORT bool + depends on PCI default y config AGP_PLUGIN_SUPPORT bool + depends on PCI default y config CARDBUS_PLUGIN_SUPPORT bool + depends on PCI default y config PCIEXP_COMMON_CLOCK diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9d4b391..a50926a 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -2,14 +2,14 @@ ramstage-y += device.c ramstage-y += root_device.c ramstage-y += cpu_device.c ramstage-y += device_util.c -ramstage-y += pci_device.c +ramstage-$(CONFIG_PCI) += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c -ramstage-y += pciexp_device.c +ramstage-$(CONFIG_PCI) += pciexp_device.c ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c -ramstage-y += pnp_device.c -ramstage-y += pci_ops.c +ramstage-$(CONFIG_ARCH_X86) += pnp_device.c +ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-y += smbus_ops.c romstage-y+= device_romstage.c diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index d9e6b27..667d734 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -756,11 +756,9 @@ struct device_operations default_pci_ops_bus = { */ static struct device_operations *get_pci_bridge_ops(device_t dev) { - unsigned int pos; - #if CONFIG_PCIX_PLUGIN_SUPPORT - pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); - if (pos) { + pcixpos = pci_find_capability(dev, PCI_CAP_ID_PCIX); + if (pcixpos) { printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev)); return &default_pcix_ops_bus; } @@ -769,10 +767,10 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) /* How do I detect a PCI to AGP bridge? */ #endif #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT - pos = 0; - while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) { + unsigned int htpos = 0; + while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) { u16 flags; - flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); + flags = pci_read_config16(dev, htpos + PCI_CAP_FLAGS); if ((flags >> 13) == 1) { /* Host or Secondary Interface */ printk(BIOS_DEBUG, "%s subordinate bus HT\n", @@ -782,10 +780,11 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) } #endif #if CONFIG_PCIEXP_PLUGIN_SUPPORT - pos = pci_find_capability(dev, PCI_CAP_ID_PCIE); - if (pos) { + unsigned int pciexpos; + pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (pciexpos) { u16 flags; - flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS); + flags = pci_read_config16(dev, pciexpos + PCI_EXP_FLAGS); switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) { case PCI_EXP_TYPE_ROOT_PORT: case PCI_EXP_TYPE_UPSTREAM:

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Patch set updated for coreboot: 954c3e1 Create a a new configuration variable for PCI
by Ronald G. Minnich 30 Nov '12

30 Nov '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1947 -gerrit commit 954c3e11225cecbc5b9c2af1e1565ff474218f73 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Nov 29 16:28:21 2012 -0800 Create a a new configuration variable for PCI Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/Kconfig | 5 +++++ src/devices/Kconfig | 14 ++++++++++++-- src/devices/Makefile.inc | 8 ++++---- src/devices/pci_device.c | 19 +++++++++---------- 4 files changed, 30 insertions(+), 16 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 6bb8135..29731b3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -203,6 +203,11 @@ source src/mainboard/Kconfig config ARCH_X86 bool default n + select PCI + +config ARCH_ARM + bool + default n config ARCH_ARMV7 bool diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 72e8a53..ce55392 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -175,28 +175,38 @@ config MULTIPLE_VGA_ADAPTERS bool default n -config PCI_64BIT_PREF_MEM +config PCI bool default n +config PCI_64BIT_PREF_MEM + bool + depends on PCI + default y + config HYPERTRANSPORT_PLUGIN_SUPPORT bool - default n + depends on PCI + default Y config PCIX_PLUGIN_SUPPORT bool + depends on PCI default y config PCIEXP_PLUGIN_SUPPORT bool + depends on PCI default y config AGP_PLUGIN_SUPPORT bool + depends on PCI default y config CARDBUS_PLUGIN_SUPPORT bool + depends on PCI default y config PCIEXP_COMMON_CLOCK diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9d4b391..69d7839 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -2,14 +2,14 @@ ramstage-y += device.c ramstage-y += root_device.c ramstage-y += cpu_device.c ramstage-y += device_util.c -ramstage-y += pci_device.c +ramstage-$(CONFIG_PCI) += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c -ramstage-y += pciexp_device.c +ramstage-$(CONFIG_PCI) += pciexp_device.c ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c -ramstage-y += pnp_device.c -ramstage-y += pci_ops.c +ramstage-$(CONFIG_PCI) += pnp_device.c +ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-y += smbus_ops.c romstage-y+= device_romstage.c diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index d9e6b27..667d734 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -756,11 +756,9 @@ struct device_operations default_pci_ops_bus = { */ static struct device_operations *get_pci_bridge_ops(device_t dev) { - unsigned int pos; - #if CONFIG_PCIX_PLUGIN_SUPPORT - pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); - if (pos) { + pcixpos = pci_find_capability(dev, PCI_CAP_ID_PCIX); + if (pcixpos) { printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev)); return &default_pcix_ops_bus; } @@ -769,10 +767,10 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) /* How do I detect a PCI to AGP bridge? */ #endif #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT - pos = 0; - while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) { + unsigned int htpos = 0; + while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) { u16 flags; - flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); + flags = pci_read_config16(dev, htpos + PCI_CAP_FLAGS); if ((flags >> 13) == 1) { /* Host or Secondary Interface */ printk(BIOS_DEBUG, "%s subordinate bus HT\n", @@ -782,10 +780,11 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) } #endif #if CONFIG_PCIEXP_PLUGIN_SUPPORT - pos = pci_find_capability(dev, PCI_CAP_ID_PCIE); - if (pos) { + unsigned int pciexpos; + pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (pciexpos) { u16 flags; - flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS); + flags = pci_read_config16(dev, pciexpos + PCI_EXP_FLAGS); switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) { case PCI_EXP_TYPE_ROOT_PORT: case PCI_EXP_TYPE_UPSTREAM:

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New patch to review for coreboot: c5f3a09 Create a a new configuration variable for PCI
by Ronald G. Minnich 30 Nov '12

30 Nov '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1947 -gerrit commit c5f3a0969ba71a01df10954dd1e7c2db7afad2cb Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Nov 29 16:28:21 2012 -0800 Create a a new configuration variable for PCI Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/Kconfig | 5 +++++ src/devices/Kconfig | 16 ++++++++++++---- src/devices/Makefile.inc | 8 ++++---- src/devices/pci_device.c | 19 +++++++++---------- 4 files changed, 30 insertions(+), 18 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 6bb8135..29731b3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -203,6 +203,11 @@ source src/mainboard/Kconfig config ARCH_X86 bool default n + select PCI + +config ARCH_ARM + bool + default n config ARCH_ARMV7 bool diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 72e8a53..e58ac50 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -175,6 +175,10 @@ config MULTIPLE_VGA_ADAPTERS bool default n +config PCI + bool + default n + config PCI_64BIT_PREF_MEM bool default n @@ -185,19 +189,23 @@ config HYPERTRANSPORT_PLUGIN_SUPPORT config PCIX_PLUGIN_SUPPORT bool - default y + depends on PCI + default n config PCIEXP_PLUGIN_SUPPORT bool - default y + depends on PCI + default n config AGP_PLUGIN_SUPPORT bool - default y + depends on PCI + default n config CARDBUS_PLUGIN_SUPPORT bool - default y + depends on ARCH_X86 + default n config PCIEXP_COMMON_CLOCK prompt "Enable PCIe Common Clock" diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc index 9d4b391..69d7839 100644 --- a/src/devices/Makefile.inc +++ b/src/devices/Makefile.inc @@ -2,14 +2,14 @@ ramstage-y += device.c ramstage-y += root_device.c ramstage-y += cpu_device.c ramstage-y += device_util.c -ramstage-y += pci_device.c +ramstage-$(CONFIG_PCI) += pci_device.c ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c -ramstage-y += pciexp_device.c +ramstage-$(CONFIG_PCI) += pciexp_device.c ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c -ramstage-y += pnp_device.c -ramstage-y += pci_ops.c +ramstage-$(CONFIG_PCI) += pnp_device.c +ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-y += smbus_ops.c romstage-y+= device_romstage.c diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index d9e6b27..667d734 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -756,11 +756,9 @@ struct device_operations default_pci_ops_bus = { */ static struct device_operations *get_pci_bridge_ops(device_t dev) { - unsigned int pos; - #if CONFIG_PCIX_PLUGIN_SUPPORT - pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); - if (pos) { + pcixpos = pci_find_capability(dev, PCI_CAP_ID_PCIX); + if (pcixpos) { printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev)); return &default_pcix_ops_bus; } @@ -769,10 +767,10 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) /* How do I detect a PCI to AGP bridge? */ #endif #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT - pos = 0; - while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) { + unsigned int htpos = 0; + while ((htpos = pci_find_next_capability(dev, PCI_CAP_ID_HT, htpos))) { u16 flags; - flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); + flags = pci_read_config16(dev, htpos + PCI_CAP_FLAGS); if ((flags >> 13) == 1) { /* Host or Secondary Interface */ printk(BIOS_DEBUG, "%s subordinate bus HT\n", @@ -782,10 +780,11 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) } #endif #if CONFIG_PCIEXP_PLUGIN_SUPPORT - pos = pci_find_capability(dev, PCI_CAP_ID_PCIE); - if (pos) { + unsigned int pciexpos; + pciexpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (pciexpos) { u16 flags; - flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS); + flags = pci_read_config16(dev, pciexpos + PCI_EXP_FLAGS); switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) { case PCI_EXP_TYPE_ROOT_PORT: case PCI_EXP_TYPE_UPSTREAM:

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Patch merged into coreboot/master: 48e21ec Add mainboard hook to bootblock
by gerrit＠coreboot.org 29 Nov '12

29 Nov '12

the following patch was just integrated into master: commit 48e21ec430cf83f540bf189b1dfa372938cc9b36 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 14 08:08:50 2012 +0200 Add mainboard hook to bootblock Change allows to override default bootblock_mainboard_init() with mainboard-specific code. If the default bootblock_mainboard_init() handler is replaced, with one from file BOOTBLOCK_MAINBOARD_INIT, one needs to take care the replacement calls all the necessary bootblock_x_init() functions. Change-Id: Ie8c667cdba7cafe9ed2d4b19ab2bd21d941ad4ca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1845 Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Wed Nov 14 09:24:00 2012, giving +1 Build-Tested: build bot (Jenkins) at Wed Nov 14 10:15:23 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Nov 30 00:57:06 2012, giving +2 See http://review.coreboot.org/1845 for details. -gerrit

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Patch merged into coreboot/master: f902248 Refactor bootblock initialisation
by gerrit＠coreboot.org 29 Nov '12

29 Nov '12

the following patch was just integrated into master: commit f90224845d5a916863c3b060a58fd82ff8d6bec0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 14 08:01:44 2012 +0200 Refactor bootblock initialisation Makes it a bit easier to implement mainboard-specific behaviour while executing the bootblock. Change-Id: I04e87f89efb4fad1c0e20b62ea6a50329a286205 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/1844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Wed Nov 14 09:53:52 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Nov 30 00:57:57 2012, giving +2 See http://review.coreboot.org/1844 for details. -gerrit

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coreboot November 2012