coreboot October 2011

coreboot@coreboot.org

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Patch set updated for coreboot: db823ad SPEEDSTEP: write _CST tables
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/321 -gerrit commit db823adef073b9b781828fab9a3b0cc0bf460257 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sat Oct 22 13:41:16 2011 +0200 SPEEDSTEP: write _CST tables Change-Id: Idb4b57044808918de343d31519768d0986840f01 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/include/arch/acpigen.h | 2 ++ src/cpu/intel/speedstep/acpi.c | 10 ++++++++++ 2 files changed, 12 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 7feaa8e..0833371 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -66,4 +66,6 @@ int acpigen_write_resourcetemplate_footer(int len); int acpigen_write_mainboard_resource_template(void); int acpigen_write_mainboard_resources(const char *scope, const char *name); +int get_cst_entries(struct cst_entry **) __attribute__((weak)); + #endif diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 48e1a3c..8f32e4f 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -62,6 +62,11 @@ static int get_fsb(void) return 200; } +int get_cst_entries(struct cst_entry **entries __attribute__((unused))) +{ + return 0; +} + void generate_cpu_entries(void) { int len_pr, len_ps; @@ -70,6 +75,9 @@ void generate_cpu_entries(void) int totalcores = determine_total_number_of_cores(); int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout + int count; + struct cst_entry *cst_entries; + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); for (cpuID=1; cpuID <=numcpus; cpuID++) { @@ -81,6 +89,8 @@ void generate_cpu_entries(void) len_pr = acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen); len_pr += acpigen_write_empty_PCT(); len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY); + if ((count = get_cst_entries(&cst_entries)) > 0) + len_pr += acpigen_write_CST_package(cst_entries, count); len_pr += acpigen_write_name("_PSS"); int max_states=8;

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Patch set updated for coreboot: 6656f70 T60: add _CST table
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/322 -gerrit commit 6656f70efbbb71f4fb6e0bb5336525c27d047a96 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sat Oct 22 13:41:28 2011 +0200 T60: add _CST table Used by power management code to enable Cx powersaving modes. Change-Id: I02c6b10762245bc48f21a341286236e203421de0 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/mainboard.c | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 8456992..8c9ef0f 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -35,6 +35,19 @@ #include <ec/lenovo/h8/h8.h> #include <northbridge/intel/i945/i945.h> #include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> + +static struct cst_entry cst_entries[] = { + { 0x7f, 1, 2, 0, 1, 1, 1, 1000 }, + { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 }, + { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 }, +}; + +int get_cst_entries(struct cst_entry **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} static void mainboard_enable(device_t dev) {

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New patch to review for coreboot: d4af8c7 T60: enable C4onC3 mode
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/330 -gerrit commit d4af8c74697b12572a92d502bce2fc97800d36b2 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 16:36:22 2011 +0200 T60: enable C4onC3 mode It is safe to enable this setting on these Boards. Change-Id: Iaa7377117743d18a95c496c25abf9fb4a1b20ad9 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/devicetree.cb | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 4d0476f..dba3fdd 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -68,6 +68,8 @@ chip northbridge/intel/i945 register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000" + register "c4onc3_enable" = "1" + device pci 1b.0 on # Audio Cnotroller subsystemid 0x17aa 0x2010 end

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New patch to review for coreboot: 63d7721 i82801gx: Add setting for C4onC3 mode
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/329 -gerrit commit 63d77216c457f639553a626a081c9013f4c9fef4 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 16:35:01 2011 +0200 i82801gx: Add setting for C4onC3 mode If this bit is set, ich7 will enter C4 mode if possible instead of C3. See ich7 specification (LPC controller, Power management control registers) for more details. Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i82801gx/chip.h | 2 ++ src/southbridge/intel/i82801gx/lpc.c | 4 ++++ 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 4aea26e..b775d39 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -68,6 +68,8 @@ struct southbridge_intel_i82801gx_config { uint32_t ide_enable_primary; uint32_t ide_enable_secondary; uint32_t sata_ahci; + + int c4onc3_enable:1; }; extern struct chip_operations southbridge_intel_i82801gx_ops; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ab3c915..c6b76d3 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -243,6 +243,10 @@ static void i82801gx_power_options(device_t dev) reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only reg16 |= (1 << 5); // CPUSLP_EN Desktop only + + if (config->c4onc3_enable) + reg16 |= (1 << 7); + // another laptop wants this? // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only

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New patch to review for coreboot: a121fd5 T60: use ICS954309 clock driver
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/328 -gerrit commit a121fd554832055fd069929f4c752bef7ca447f7 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 15:54:31 2011 +0200 T60: use ICS954309 clock driver Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/Kconfig | 1 + src/mainboard/lenovo/t60/devicetree.cb | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 294384b..9deb5a3 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_TI_PCI1X2X select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select DRIVERS_ICS_954309 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 27ce46c..4d0476f 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -197,6 +197,21 @@ chip northbridge/intel/i945 end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f + chip drivers/ics/954309 + register "reg0" = "0x2e" + register "reg1" = "0xf7" + register "reg2" = "0x3c" + register "reg3" = "0x20" + register "reg4" = "0x01" + register "reg5" = "0x00" + register "reg6" = "0x1b" + register "reg7" = "0x01" + register "reg8" = "0x54" + register "reg9" = "0xff" + register "reg10" = "0xff" + register "reg11" = "0x07" + device i2c 69 on end + end end end end

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New patch to review for coreboot: b4631f9 Add driver for ICS954309 clock generator
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/327 -gerrit commit b4631f9483fc7ddcad53ed66901fc970a6b45f2d Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 15:53:47 2011 +0200 Add driver for ICS954309 clock generator Change-Id: Iac7e91cdd995dad1954eaa2d4dd52bffa293fc95 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/drivers/Kconfig | 2 +- src/drivers/Makefile.inc | 2 +- src/drivers/ics/954309/Kconfig | 2 + src/drivers/ics/954309/Makefile.inc | 1 + src/drivers/ics/954309/chip.h | 16 ++++++++++ src/drivers/ics/954309/ics954309.c | 56 +++++++++++++++++++++++++++++++++++ src/drivers/ics/Kconfig | 1 + src/drivers/ics/Makefile.inc | 1 + 8 files changed, 79 insertions(+), 2 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 98f2079..259bc29 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -25,4 +25,4 @@ source src/drivers/i2c/Kconfig source src/drivers/oxford/Kconfig source src/drivers/sil/Kconfig source src/drivers/trident/Kconfig - +source src/drivers/ics/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index ae7a098..21a698a 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -25,4 +25,4 @@ subdirs-y += i2c subdirs-y += oxford subdirs-y += sil subdirs-y += trident - +subdirs-y += ics diff --git a/src/drivers/ics/954309/Kconfig b/src/drivers/ics/954309/Kconfig new file mode 100644 index 0000000..43840a3 --- /dev/null +++ b/src/drivers/ics/954309/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_ICS_954309 + bool diff --git a/src/drivers/ics/954309/Makefile.inc b/src/drivers/ics/954309/Makefile.inc new file mode 100644 index 0000000..ede9639 --- /dev/null +++ b/src/drivers/ics/954309/Makefile.inc @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_ICS_954309) += ics954309.c diff --git a/src/drivers/ics/954309/chip.h b/src/drivers/ics/954309/chip.h new file mode 100644 index 0000000..efd205f --- /dev/null +++ b/src/drivers/ics/954309/chip.h @@ -0,0 +1,16 @@ +extern struct chip_operations drivers_ics_954309_ops; + +struct drivers_ics_954309_config { + u8 reg0; + u8 reg1; + u8 reg2; + u8 reg3; + u8 reg4; + u8 reg5; + u8 reg6; + u8 reg7; + u8 reg8; + u8 reg9; + u8 reg10; + u8 reg11; +}; diff --git a/src/drivers/ics/954309/ics954309.c b/src/drivers/ics/954309/ics954309.c new file mode 100644 index 0000000..a7a350e --- /dev/null +++ b/src/drivers/ics/954309/ics954309.c @@ -0,0 +1,56 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/smbus.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include "chip.h" +#include <string.h> + +static void ics954309_init(device_t dev) +{ + struct drivers_ics_954309_config *config; + u8 initdata[12]; + + if (!dev->enabled || dev->path.type != DEVICE_PATH_I2C) + return; + + config = dev->chip_info; + + initdata[0] = config->reg0; + initdata[1] = config->reg1; + initdata[2] = config->reg2; + initdata[3] = config->reg3; + initdata[4] = config->reg4; + initdata[5] = config->reg5; + initdata[6] = config->reg6; + initdata[7] = config->reg7; + initdata[8] = config->reg8; + initdata[9] = config->reg9; + initdata[10] = config->reg10; + initdata[11] = config->reg11; + + smbus_block_write(dev, 0, 12, initdata); +} + +static void ics954309_noop(device_t dummy) +{ +} + +static struct device_operations ics954309_operations = { + .read_resources = ics954309_noop, + .set_resources = ics954309_noop, + .enable_resources = ics954309_noop, + .init = ics954309_init, +}; + +static void enable_dev(struct device *dev) +{ + dev->ops = &ics954309_operations; +} + +struct chip_operations drivers_ics_954309_ops = { + CHIP_NAME("ICS 954309 Clock generator") + .enable_dev = enable_dev, +}; diff --git a/src/drivers/ics/Kconfig b/src/drivers/ics/Kconfig new file mode 100644 index 0000000..0a0ba66 --- /dev/null +++ b/src/drivers/ics/Kconfig @@ -0,0 +1 @@ +source src/drivers/ics/954309/Kconfig diff --git a/src/drivers/ics/Makefile.inc b/src/drivers/ics/Makefile.inc new file mode 100644 index 0000000..39cc90b --- /dev/null +++ b/src/drivers/ics/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_DRIVERS_ICS_954309) += 954309

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New patch to review for coreboot: a794ed2 i82801gx: Add write and read/write block functions
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/326 -gerrit commit a794ed2cd94cfbc2b519d913591801e0633fa48a Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 15:36:15 2011 +0200 i82801gx: Add write and read/write block functions Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i82801gx/smbus.c | 182 ++++++++++++++++++++++++++++++++ 1 files changed, 182 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 184120f..1764d97 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -42,8 +42,190 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } +static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data) +{ + unsigned char global_status_register; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(data, smbus_base + SMBHSTDAT0); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + + global_status_register = inb(smbus_base + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + if (global_status_register != (1 << 1)) + return SMBUS_ERROR; + return 0; +} + +static int lsmbus_write_byte(device_t dev, u8 address, u8 data) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + return do_smbus_write_byte(res->base, device, address, data); +} + +static int do_smbus_block_write(unsigned smbus_base, unsigned device, + unsigned cmd, unsigned bytes, const u8 *buf) +{ + u8 status; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(cmd & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a block data write */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* set number of bytes to transfer */ + outb(bytes, smbus_base + SMBHSTDAT0); + + outb(*buf++, smbus_base + SMBBLKDAT); + bytes--; + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + while(!(inb(smbus_base + SMBHSTSTAT) & 1)); + /* Poll for transaction completion */ + do { + status = inb(smbus_base + SMBHSTSTAT); + if (status & ((1 << 4) | /* FAILED */ + (1 << 3) | /* BUS ERR */ + (1 << 2))) /* DEV ERR */ + return SMBUS_ERROR; + + if (status & 0x80) { /* Byte done */ + outb(*buf++, smbus_base + SMBBLKDAT); + outb(status, smbus_base + SMBHSTSTAT); + } + } while(status & 0x01); + + return 0; +} + + + +static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + return do_smbus_block_write(res->base, device, cmd, bytes, buf); +} + +static int do_smbus_block_read(unsigned smbus_base, unsigned device, + unsigned cmd, unsigned bytes, u8 *buf) +{ + u8 status; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(cmd & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a block data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + while(!(inb(smbus_base + SMBHSTSTAT) & 1)); + /* Poll for transaction completion */ + do { + status = inb(smbus_base + SMBHSTSTAT); + if (status & ((1 << 4) | /* FAILED */ + (1 << 3) | /* BUS ERR */ + (1 << 2))) /* DEV ERR */ + return SMBUS_ERROR; + + if (status & 0x80) { /* Byte done */ + *buf = inb(smbus_base + SMBBLKDAT); + buf++; + outb(status, smbus_base + SMBHSTSTAT); + if (--bytes == 1) { + /* indicate that next byte is the last one */ + outb(inb(smbus_base + SMBHSTCTL) | 0x20, + smbus_base + SMBHSTCTL); + } + } + } while(status & 0x01); + + return 0; +} + +static int lsmbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buf) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + return do_smbus_block_read(res->base, device, cmd, bytes, buf); +} + + static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, + .block_read = lsmbus_block_read, + .block_write = lsmbus_block_write, }; static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)

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New patch to review for coreboot: 5d681e0 i82801gx: Don't set I/O base address to static value
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/325 -gerrit commit 5d681e0c15ea595292bd9c40d47691cd153aea34 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 15:30:29 2011 +0200 i82801gx: Don't set I/O base address to static value Doing it this way will break all subsequent smbus calls, because the smbus code still uses res->base, which points to the old base address. Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i82801gx/smbus.c | 14 -------------- 1 files changed, 0 insertions(+), 14 deletions(-) diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 834f310..184120f 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -29,19 +29,6 @@ #include "i82801gx.h" #include "smbus.h" -#define SMB_BASE 0x20 -static void smbus_init(struct device *dev) -{ - u32 smb_base; - - smb_base = pci_read_config32(dev, SMB_BASE); - printk(BIOS_DEBUG, "Initializing SMBus device:\n"); - printk(BIOS_DEBUG, " Old SMBUS Base Address: 0x%04x\n", smb_base); - pci_write_config32(dev, SMB_BASE, 0x00000401); - smb_base = pci_read_config32(dev, SMB_BASE); - printk(BIOS_DEBUG, " New SMBUS Base Address: 0x%04x\n", smb_base); -} - static int lsmbus_read_byte(device_t dev, u8 address) { u16 device; @@ -78,7 +65,6 @@ static struct device_operations smbus_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = smbus_init, .scan_bus = scan_static_bus, .enable = i82801gx_enable, .ops_smbus_bus = &lops_smbus_bus,

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Patch set updated for coreboot: 7e20b87 Allow XGCCPATH to be set on the make command line.
by Marc Jones 23 Oct '11

23 Oct '11

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/318 -gerrit commit 7e20b87c3ed60a8f3f4ac93c245c2e46e08b5c4e Author: Marc Jones <marcj303(a)gmail.com> Date: Fri Oct 7 17:20:30 2011 -0600 Allow XGCCPATH to be set on the make command line. The xgcc toolchain may be moved by the user and passed in on the commandline. Updates the Makefile and the xcompile script. Change-Id: I05797b2cabce39bdd7868c2515f30d34043fc8cc Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- Makefile | 2 +- util/xcompile/xcompile | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 44a1d63..c543897 100644 --- a/Makefile +++ b/Makefile @@ -34,7 +34,7 @@ ifeq ($(INNER_SCANBUILD),y) CC_real:=$(CC) endif -$(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile > .xcompile))) +$(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile $(XGCCPATH) > .xcompile))) include .xcompile ifeq ($(INNER_SCANBUILD),y) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index b68e1b3..9a0a295 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -35,7 +35,8 @@ for make in make gmake gnumake; do done GCCPREFIX=invalid -XGCCPATH="`pwd`/util/crossgcc/xgcc/bin/" +XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} +echo '#XGCCPATH='${XGCCPATH} TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz` touch $TMPFILE

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Patch merged into coreboot/master: 84aaa51 SB800: Hide unused gpp ports
by gerrit＠coreboot.org 23 Oct '11

23 Oct '11

the following patch was just integrated into master: commit 84aaa51051020920f5f42b7ea4c2410693cba36a Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Oct 12 12:06:23 2011 +0800 SB800: Hide unused gpp ports Add configure option SB_GPP_UNHIDE_PORTS for mainboard to hide/unhide the unused sb800 gpp ports. Certain gpp port should be hidden, if no device was detected and hotplug feature is disabled for such port. Hidden unused ports makes lspci -vvv get more accurate information under Linux. Test on avalue/eax-785e mainboard. Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Oct 23 14:07:27 2011, giving +2 See http://review.coreboot.org/207 for details. -gerrit

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coreboot October 2011