coreboot October 2011

coreboot@coreboot.org

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Patch set updated for coreboot: 88c9838 T60: add _CST table
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/322 -gerrit commit 88c9838d4f9a1c0285df955225bdd03175b884ba Author: Sven Schnelle <svens(a)stackframe.org> Date: Sat Oct 22 13:41:28 2011 +0200 T60: add _CST table Used by power management code to enable Cx powersaving modes. Change-Id: I02c6b10762245bc48f21a341286236e203421de0 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/mainboard.c | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 8456992..8c9ef0f 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -35,6 +35,19 @@ #include <ec/lenovo/h8/h8.h> #include <northbridge/intel/i945/i945.h> #include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> + +static struct cst_entry cst_entries[] = { + { 0x7f, 1, 2, 0, 1, 1, 1, 1000 }, + { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 }, + { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 }, +}; + +int get_cst_entries(struct cst_entry **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} static void mainboard_enable(device_t dev) {

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Patch set updated for coreboot: 384f8a9 i82801gx: Don't set I/O base address to static value
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/325 -gerrit commit 384f8a938f219c4a1d69eccda24baa79b642d6d0 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 15:30:29 2011 +0200 i82801gx: Don't set I/O base address to static value Doing it this way will break all subsequent smbus calls, because the smbus code still uses res->base, which points to the old base address. Fix this by allocating a proper resource. Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i82801gx/smbus.c | 26 +++++++++++--------------- 1 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 834f310..f296b46 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -29,19 +29,6 @@ #include "i82801gx.h" #include "smbus.h" -#define SMB_BASE 0x20 -static void smbus_init(struct device *dev) -{ - u32 smb_base; - - smb_base = pci_read_config32(dev, SMB_BASE); - printk(BIOS_DEBUG, "Initializing SMBus device:\n"); - printk(BIOS_DEBUG, " Old SMBUS Base Address: 0x%04x\n", smb_base); - pci_write_config32(dev, SMB_BASE, 0x00000401); - smb_base = pci_read_config32(dev, SMB_BASE); - printk(BIOS_DEBUG, " New SMBUS Base Address: 0x%04x\n", smb_base); -} - static int lsmbus_read_byte(device_t dev, u8 address) { u16 device; @@ -74,11 +61,20 @@ static struct pci_operations smbus_pci_ops = { .set_subsystem = smbus_set_subsystem, }; +static void smbus_read_resources(device_t dev) +{ + struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); + res->base = SMBUS_IO_BASE; + res->size = 32; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = smbus_init, .scan_bus = scan_static_bus, .enable = i82801gx_enable, .ops_smbus_bus = &lops_smbus_bus,

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Patch set updated for coreboot: 82d5c8f Add driver for ICS954309 clock generator
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/327 -gerrit commit 82d5c8f249022fe7cc11db7f48b95e57918aca89 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 15:53:47 2011 +0200 Add driver for ICS954309 clock generator Change-Id: Iac7e91cdd995dad1954eaa2d4dd52bffa293fc95 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/drivers/Kconfig | 2 +- src/drivers/Makefile.inc | 2 +- src/drivers/ics/954309/Kconfig | 2 + src/drivers/ics/954309/Makefile.inc | 1 + src/drivers/ics/954309/chip.h | 16 ++++++++++ src/drivers/ics/954309/ics954309.c | 56 +++++++++++++++++++++++++++++++++++ src/drivers/ics/Kconfig | 1 + src/drivers/ics/Makefile.inc | 1 + 8 files changed, 79 insertions(+), 2 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 98f2079..259bc29 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -25,4 +25,4 @@ source src/drivers/i2c/Kconfig source src/drivers/oxford/Kconfig source src/drivers/sil/Kconfig source src/drivers/trident/Kconfig - +source src/drivers/ics/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index ae7a098..21a698a 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -25,4 +25,4 @@ subdirs-y += i2c subdirs-y += oxford subdirs-y += sil subdirs-y += trident - +subdirs-y += ics diff --git a/src/drivers/ics/954309/Kconfig b/src/drivers/ics/954309/Kconfig new file mode 100644 index 0000000..43840a3 --- /dev/null +++ b/src/drivers/ics/954309/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_ICS_954309 + bool diff --git a/src/drivers/ics/954309/Makefile.inc b/src/drivers/ics/954309/Makefile.inc new file mode 100644 index 0000000..ede9639 --- /dev/null +++ b/src/drivers/ics/954309/Makefile.inc @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_ICS_954309) += ics954309.c diff --git a/src/drivers/ics/954309/chip.h b/src/drivers/ics/954309/chip.h new file mode 100644 index 0000000..efd205f --- /dev/null +++ b/src/drivers/ics/954309/chip.h @@ -0,0 +1,16 @@ +extern struct chip_operations drivers_ics_954309_ops; + +struct drivers_ics_954309_config { + u8 reg0; + u8 reg1; + u8 reg2; + u8 reg3; + u8 reg4; + u8 reg5; + u8 reg6; + u8 reg7; + u8 reg8; + u8 reg9; + u8 reg10; + u8 reg11; +}; diff --git a/src/drivers/ics/954309/ics954309.c b/src/drivers/ics/954309/ics954309.c new file mode 100644 index 0000000..a7a350e --- /dev/null +++ b/src/drivers/ics/954309/ics954309.c @@ -0,0 +1,56 @@ +#include <console/console.h> +#include <device/device.h> +#include <device/smbus.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include "chip.h" +#include <string.h> + +static void ics954309_init(device_t dev) +{ + struct drivers_ics_954309_config *config; + u8 initdata[12]; + + if (!dev->enabled || dev->path.type != DEVICE_PATH_I2C) + return; + + config = dev->chip_info; + + initdata[0] = config->reg0; + initdata[1] = config->reg1; + initdata[2] = config->reg2; + initdata[3] = config->reg3; + initdata[4] = config->reg4; + initdata[5] = config->reg5; + initdata[6] = config->reg6; + initdata[7] = config->reg7; + initdata[8] = config->reg8; + initdata[9] = config->reg9; + initdata[10] = config->reg10; + initdata[11] = config->reg11; + + smbus_block_write(dev, 0, 12, initdata); +} + +static void ics954309_noop(device_t dummy) +{ +} + +static struct device_operations ics954309_operations = { + .read_resources = ics954309_noop, + .set_resources = ics954309_noop, + .enable_resources = ics954309_noop, + .init = ics954309_init, +}; + +static void enable_dev(struct device *dev) +{ + dev->ops = &ics954309_operations; +} + +struct chip_operations drivers_ics_954309_ops = { + CHIP_NAME("ICS 954309 Clock generator") + .enable_dev = enable_dev, +}; diff --git a/src/drivers/ics/Kconfig b/src/drivers/ics/Kconfig new file mode 100644 index 0000000..0a0ba66 --- /dev/null +++ b/src/drivers/ics/Kconfig @@ -0,0 +1 @@ +source src/drivers/ics/954309/Kconfig diff --git a/src/drivers/ics/Makefile.inc b/src/drivers/ics/Makefile.inc new file mode 100644 index 0000000..39cc90b --- /dev/null +++ b/src/drivers/ics/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_DRIVERS_ICS_954309) += 954309

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Patch set updated for coreboot: 34fbe31 i82801gx: Add write and read/write block functions
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/326 -gerrit commit 34fbe315ac9301a0a312b09b386db74f4c3279c4 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 15:36:15 2011 +0200 i82801gx: Add write and read/write block functions Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i82801gx/smbus.c | 182 ++++++++++++++++++++++++++++++++ 1 files changed, 182 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index f296b46..63be26f 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -42,8 +42,190 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } +static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data) +{ + unsigned char global_status_register; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(data, smbus_base + SMBHSTDAT0); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + + global_status_register = inb(smbus_base + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + if (global_status_register != (1 << 1)) + return SMBUS_ERROR; + return 0; +} + +static int lsmbus_write_byte(device_t dev, u8 address, u8 data) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + return do_smbus_write_byte(res->base, device, address, data); +} + +static int do_smbus_block_write(unsigned smbus_base, unsigned device, + unsigned cmd, unsigned bytes, const u8 *buf) +{ + u8 status; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(cmd & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a block data write */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* set number of bytes to transfer */ + outb(bytes, smbus_base + SMBHSTDAT0); + + outb(*buf++, smbus_base + SMBBLKDAT); + bytes--; + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + while(!(inb(smbus_base + SMBHSTSTAT) & 1)); + /* Poll for transaction completion */ + do { + status = inb(smbus_base + SMBHSTSTAT); + if (status & ((1 << 4) | /* FAILED */ + (1 << 3) | /* BUS ERR */ + (1 << 2))) /* DEV ERR */ + return SMBUS_ERROR; + + if (status & 0x80) { /* Byte done */ + outb(*buf++, smbus_base + SMBBLKDAT); + outb(status, smbus_base + SMBHSTSTAT); + } + } while(status & 0x01); + + return 0; +} + + + +static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + return do_smbus_block_write(res->base, device, cmd, bytes, buf); +} + +static int do_smbus_block_read(unsigned smbus_base, unsigned device, + unsigned cmd, unsigned bytes, u8 *buf) +{ + u8 status; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(cmd & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a block data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + while(!(inb(smbus_base + SMBHSTSTAT) & 1)); + /* Poll for transaction completion */ + do { + status = inb(smbus_base + SMBHSTSTAT); + if (status & ((1 << 4) | /* FAILED */ + (1 << 3) | /* BUS ERR */ + (1 << 2))) /* DEV ERR */ + return SMBUS_ERROR; + + if (status & 0x80) { /* Byte done */ + *buf = inb(smbus_base + SMBBLKDAT); + buf++; + outb(status, smbus_base + SMBHSTSTAT); + if (--bytes == 1) { + /* indicate that next byte is the last one */ + outb(inb(smbus_base + SMBHSTCTL) | 0x20, + smbus_base + SMBHSTCTL); + } + } + } while(status & 0x01); + + return 0; +} + +static int lsmbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buf) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + return do_smbus_block_read(res->base, device, cmd, bytes, buf); +} + + static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, + .block_read = lsmbus_block_read, + .block_write = lsmbus_block_write, }; static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)

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afmelden help.
by Marjolein kooistra 23 Oct '11

23 Oct '11

HELP. afmelden

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Patch merged into coreboot/master: 0770acf FILO: Pass LIBCONFIG_PATH variable to FILOs make
by gerrit＠coreboot.org 23 Oct '11

23 Oct '11

the following patch was just integrated into master: commit 0770acf8abc1d4a1c70b97e4539369f56d30af9e Author: Thomas Gstädtner <thomas(a)gstaedtner.net> Date: Fri Oct 21 22:01:32 2011 +0200 FILO: Pass LIBCONFIG_PATH variable to FILOs make This fixes the build for HEAD/master. Current stable will not work, because it is too old for recent corboot. Change-Id: I9dfd5de472d4f58f07147cb9b9bb0b543f228561 Signed-off-by: Thomas Gstädtner <thomas(a)gstaedtner.net> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Oct 23 19:20:15 2011, giving +2 See http://review.coreboot.org/311 for details. -gerrit

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Patch merged into coreboot/master: 7e20b87 Allow XGCCPATH to be set on the make command line.
by gerrit＠coreboot.org 23 Oct '11

23 Oct '11

the following patch was just integrated into master: commit 7e20b87c3ed60a8f3f4ac93c245c2e46e08b5c4e Author: Marc Jones <marcj303(a)gmail.com> Date: Fri Oct 7 17:20:30 2011 -0600 Allow XGCCPATH to be set on the make command line. The xgcc toolchain may be moved by the user and passed in on the commandline. Updates the Makefile and the xcompile script. Change-Id: I05797b2cabce39bdd7868c2515f30d34043fc8cc Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Oct 23 18:55:26 2011, giving +2 See http://review.coreboot.org/318 for details. -gerrit

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Patch merged into coreboot/master: d2e2c79 console: support integrated 7-segment displays for POST codes
by gerrit＠coreboot.org 23 Oct '11

23 Oct '11

the following patch was just integrated into master: commit d2e2c796580078a568d66e59db805ceb69a1e774 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Sun Sep 18 22:54:51 2011 +0200 console: support integrated 7-segment displays for POST codes Add a configuration option POST_PORT which defaults to 0x80 and can be redefined by boards which have integrated POST displays on another I/O port. Change post.c to output POST codes to this port instead of 0x80 hardcoded. Change-Id: I8f8e820f8c75641b35e7249bf622b63a3604b9f3 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Oct 23 17:24:05 2011, giving +2 See http://review.coreboot.org/221 for details. -gerrit

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New patch to review for coreboot: 81d8670 X60: enable Cx power saving modes
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/331 -gerrit commit 81d8670d8c50d1851a73be816c934742502ea673 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sun Oct 23 16:57:50 2011 +0200 X60: enable Cx power saving modes Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/devicetree.cb | 18 ++++++++++++++++++ src/mainboard/lenovo/x60/mainboard.c | 13 +++++++++++++ 3 files changed, 32 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index c4b2f63..1784505 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_NSC_PC87392 select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select DRIVERS_ICS_954309 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 55e0b2d..000f9c7 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -60,6 +60,8 @@ chip northbridge/intel/i945 register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000" + + register "c4onc3_enable" = "1" device pci 1b.0 on # Audio Cnotroller subsystemid 0x17aa 0x2010 end @@ -174,6 +176,22 @@ chip northbridge/intel/i945 end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f + chip drivers/ics/954309 + register "reg0" = "0x2e" + register "reg1" = "0xf7" + register "reg2" = "0x3c" + register "reg3" = "0x20" + register "reg4" = "0x01" + register "reg5" = "0x00" + register "reg6" = "0x1b" + register "reg7" = "0x01" + register "reg8" = "0x54" + register "reg9" = "0xff" + register "reg10" = "0xff" + register "reg11" = "0x07" + device i2c 69 on end + end + end end chip southbridge/ricoh/rl5c476 diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index bf3d8d3..ef7d21f 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -36,6 +36,19 @@ #include <northbridge/intel/i945/i945.h> #include <pc80/mc146818rtc.h> #include "dock.h" +#include <arch/x86/include/arch/acpigen.h> + +static struct cst_entry cst_entries[] = { + { 0x7f, 1, 2, 0, 1, 1, 1, 1000 }, + { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 }, + { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 }, +}; + +int get_cst_entries(struct cst_entry **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} static void mainboard_enable(device_t dev) {

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Patch set updated for coreboot: b117811 ACPI: Add function for writing _CST tables
by Sven Schnelle 23 Oct '11

23 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/312 -gerrit commit b11781137de0ed6c2b694d710f23abf64e577db7 Author: Sven Schnelle <svens(a)stackframe.org> Date: Fri Oct 21 21:46:47 2011 +0200 ACPI: Add function for writing _CST tables Change-Id: I4e16a0d37717c56a3529f9f9fdb05efec1d93f99 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/boot/acpigen.c | 57 +++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 13 ++++++++ 2 files changed, 70 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index e8cd724..7dc7fed 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -374,6 +374,41 @@ int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) return len + lenh; } +static int acpigen_write_CST_package_entry(struct cst_entry *entry) +{ + int len, len0; + char *start, *end; + + len0 = acpigen_write_package(4); + len = acpigen_write_resourcetemplate_header(); + start = acpigen_get_current(); + acpigen_write_register(entry->type, entry->width, entry->offset, entry->addrsize, entry->address); + end = acpigen_get_current(); + len += end-start; + len += acpigen_write_resourcetemplate_footer(len); + len += len0; + len += acpigen_write_dword(entry->ctype); + len += acpigen_write_dword(entry->latency); + len += acpigen_write_dword(entry->power); + acpigen_patch_len(len - 1); + return len; +} + +int acpigen_write_CST_package(struct cst_entry *entry, int nentries) +{ + int len, lenh, lenp, i; + lenh = acpigen_write_name("_CST"); + lenp = acpigen_write_package(nentries+1); + len = acpigen_write_dword(nentries); + + for (i = 0; i < nentries; i++) + len += acpigen_write_CST_package_entry(entry + i); + + len += lenp; + acpigen_patch_len(len - 1); + return len + lenh; +} + int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) { /* @@ -399,6 +434,28 @@ int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) return 12; } +int acpigen_write_register(int type, int width, int offset, int addrsize, u64 address) +{ + acpigen_emit_byte(0x82); + /* Byte 1+2: length (0x000c) */ + acpigen_emit_byte(0x0c); + acpigen_emit_byte(0x00); + /* bit1-7 are ignored */ + acpigen_emit_byte(type); /* FFixedHW */ + acpigen_emit_byte(width); /* register width */ + acpigen_emit_byte(offset); /* register offset */ + acpigen_emit_byte(addrsize); /* register address size */ + acpigen_emit_byte(address & 0xff); /* register address 0-7 */ + acpigen_emit_byte((address >> 8) & 0xff); /* register address 8-15 */ + acpigen_emit_byte((address >> 16) & 0xff); /* register address 16-23 */ + acpigen_emit_byte((address >> 24) & 0xff); /* register address 24-31 */ + acpigen_emit_byte((address >> 32) & 0xff); /* register address 32-39 */ + acpigen_emit_byte((address >> 40) & 0xff); /* register address 40-47 */ + acpigen_emit_byte((address >> 48) & 0xff); /* register address 48-55 */ + acpigen_emit_byte((address >> 56) & 0xff); /* register address 56-63 */ + return 15; +} + int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 6f13a7a..7feaa8e 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -24,6 +24,17 @@ #include <stdlib.h> #include <stdint.h> +struct cst_entry { + int type; + int width; + int offset; + int addrsize; + u64 address; + int ctype; + int latency; + int power; +}; + void acpigen_patch_len(int len); void acpigen_set_current(char *curr); char *acpigen_get_current(void); @@ -45,9 +56,11 @@ int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat u32 control, u32 status); typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord; int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); +int acpigen_write_CST_package(struct cst_entry *entry, int nentries); int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); +int acpigen_write_register(int type, int width, int offset, int addrsize, u64 address); int acpigen_write_resourcetemplate_header(void); int acpigen_write_resourcetemplate_footer(int len); int acpigen_write_mainboard_resource_template(void);

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coreboot October 2011