coreboot September 2009

coreboot@coreboot.org

62 participants
305 discussions

[v2] r4684 - trunk/coreboot-v2/util/options
by svn＠coreboot.org 29 Sep '09

29 Sep '09

Author: oxygene Date: 2009-09-29 15:34:56 +0200 (Tue, 29 Sep 2009) New Revision: 4684 Modified: trunk/coreboot-v2/util/options/build_opt_tbl.c Log: Make the error messages somewhat less incomprehensible. I forget what they mean every time I see them. Add a proto. More work remains to be done. Build tested on dell s1850. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/util/options/build_opt_tbl.c =================================================================== --- trunk/coreboot-v2/util/options/build_opt_tbl.c 2009-09-28 22:36:40 UTC (rev 4683) +++ trunk/coreboot-v2/util/options/build_opt_tbl.c 2009-09-29 13:34:56 UTC (rev 4684) @@ -16,6 +16,7 @@ #define TMPFILE_TEMPLATE "/build_opt_tbl_XXXXXX" static unsigned char cmos_table[4096]; +void test_for_entry_overlaps(void *entry_start, void *entry_end); /* This array is used to isolate bits that are to be changed in a byte */ static unsigned char clip[9]={0,1,3,7,0x0f,0x1f,0x3f,0x7f,0xff}; @@ -460,17 +461,21 @@ } /* And since we are not ready to be fully general purpose yet.. */ if ((cs->range_start/8) != CONFIG_LB_CKS_RANGE_START) { - fprintf(stderr, "Error - Range start(%d) does not match define(%d) in line\n%s\n", - cs->range_start/8, CONFIG_LB_CKS_RANGE_START, line); + fprintf(stderr, "Error - Range start((value in file #%d), which is byte #%d)" + "does not match the value of the config variable LB_CKS_RANGE_START)(%d) in line\n%s\n", + cs->range_start, cs->range_start/8, CONFIG_LB_CKS_RANGE_START, line); exit(1); } if ((cs->range_end/8) != CONFIG_LB_CKS_RANGE_END) { - fprintf(stderr, "Error - Range end (%d) does not match define (%d) in line\n%s\n", - (cs->range_end/8), CONFIG_LB_CKS_RANGE_END, line); + fprintf(stderr, "Error - Range end ((value in file #%d), which is byte #%d)" + "does not match the value of the config variable LB_CKS_RANGE_END (%d) in line\n%s\n", + cs->range_end, cs->range_end/8, + CONFIG_LB_CKS_RANGE_END, line); exit(1); } if ((cs->location/8) != CONFIG_LB_CKS_LOC) { - fprintf(stderr, "Error - Location does not match define in line\n%s\n", line); + fprintf(stderr, "Error - Location ((value in file #%d), which is byte #%d) does not match LB_CKS_LOC (%d) in line\n%s\n", + cs->location, cs->location/8, CONFIG_LB_CKS_LOC, line); exit(1); }

1 0

filo build failure: get_multiboot_info is undefined
by Ken.Fuchs＠bench.com 28 Sep '09

28 Sep '09

The libpayload and filo code is from repos r4671. Summary of the error: ... LD build/filo /home/fuchsk/coreboot/filo/build/libpayload/lib/libpayload.a(sysinfo.o): \ In function `lib_get_sysinfo': sysinfo.c:(.text+0x18): undefined reference to `get_multiboot_info' make: *** [/home/fuchsk/coreboot/filo/build/filo] Error 1 $ Downloaded code via http://tracker.coreboot.org/trac/coreboot/browser/trunk/payloads & http://tracker.coreboot.org/trac/filo/browser/trunk and the zip download links at the bottom of each page. Extracted onto a relatively current (1-2 months old), trim (~600MB) Debian system. libpayload was built as follows: $ pushd ~/coreboot/trunk/payloads/libpayload $ make clean $ make defconfig $ make $ make DESTDIR=../../../filo/build install $ pushd ../../../filo/ $ make menuconfig <Save config without making any (new) selections.> $ make CC build/i386/context.o AS build/i386/switch.S.o CC build/i386/segment.o CC build/i386/timer.o CC build/i386/sys_info.o CC build/i386/linux_load.o CC build/main/filo.o CC build/main/strtox.o CC build/main/elfload.o CC build/main/elfnote.o CC build/main/ipchecksum.o CC build/main/grub/grub.o CC build/main/grub/builtins.o CC build/main/grub/cmdline.o CC build/main/grub/char_io.o CC build/main/grub/completions.o CC build/main/grub/md5.o CC build/fs/blockdev.o CC build/fs/vfs.o CC build/fs/eltorito.o CC build/fs/fsys_ext2fs.o CC build/fs/fsys_fat.o CC build/fs/fsys_reiserfs.o CC build/fs/fsys_iso9660.o CC build/fs/fsys_cbfs.o In file included from /home/fuchsk/coreboot/filo/fs/fsys_cbfs.c:21: include/cbfs.h:160: warning: â declared inside parameter list include/cbfs.h:160: warning: its scope is only this definition or declaration, \ which is probably not what you want CC build/fs/cbfs.o In file included from /home/fuchsk/coreboot/filo/fs/cbfs.c:22: include/cbfs.h:160: warning: â declared inside parameter list include/cbfs.h:160: warning: its scope is only this definition or declaration, \ which is probably not what you want /home/fuchsk/coreboot/filo/fs/cbfs.c: In function â: /home/fuchsk/coreboot/filo/fs/cbfs.c:88: warning: assignment makes integer from\ pointer without a cast /home/fuchsk/coreboot/filo/fs/cbfs.c:108: warning: comparison between pointer a\ nd integer CC build/fs/lzma.o CC build/drivers/ide.o CC build/drivers/intel.o CC build/drivers/newusb/usb.o LD build/filo /home/fuchsk/coreboot/filo/build/libpayload/lib/libpayload.a(sysinfo.o): In fun\ ction `lib_get_sysinfo': sysinfo.c:(.text+0x18): undefined reference to `get_multiboot_info' make: *** [/home/fuchsk/coreboot/filo/build/filo] Error 1 $ Any suggestions for resolving this error? Sincerely, Ken Fuchs

4 7

build service results for r4683
by coreboot information 28 Sep '09

28 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4683 to the coreboot repository. This caused the following changes: Change Log: Trivial config fix for Serengeti Cheetah. Change a type and a default. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4683&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4683&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4683&device=briq&vendor=to… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[v2] r4683 - trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah
by svn＠coreboot.org 28 Sep '09

28 Sep '09

Author: myles Date: 2009-09-29 00:36:40 +0200 (Tue, 29 Sep 2009) New Revision: 4683 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig Log: Trivial config fix for Serengeti Cheetah. Change a type and a default. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-09-28 21:51:39 UTC (rev 4682) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-09-28 22:36:40 UTC (rev 4683) @@ -110,8 +110,8 @@ depends on BOARD_AMD_SERENGETI_CHEETAH config SB_HT_CHAIN_UNITID_OFFSET_ONLY - int - default 1 + bool + default y depends on BOARD_AMD_SERENGETI_CHEETAH config SB_HT_CHAIN_ON_BUS0 @@ -126,7 +126,7 @@ config HT_CHAIN_UNITID_BASE hex - default 0x1 + default 0xa depends on BOARD_AMD_SERENGETI_CHEETAH config USE_INIT

1 0

build service results for r4682
by coreboot information 28 Sep '09

28 Sep '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 4682 to the coreboot repository. This caused the following changes: Change Log: Trivial config fix for Serengeti Cheetah. Remove duplication, add a default. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4682&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4682&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4682&device=briq&vendor=to… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[v2] r4682 - trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah
by svn＠coreboot.org 28 Sep '09

28 Sep '09

Author: myles Date: 2009-09-28 23:51:39 +0200 (Mon, 28 Sep 2009) New Revision: 4682 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig Log: Trivial config fix for Serengeti Cheetah. Remove duplication, add a default. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-09-26 16:43:17 UTC (rev 4681) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-09-28 21:51:39 UTC (rev 4682) @@ -49,11 +49,6 @@ default y depends on BOARD_AMD_SERENGETI_CHEETAH -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - depends on BOARD_AMD_SERENGETI_CHEETAH - config LB_CKS_RANGE_END int default 122 @@ -114,6 +109,16 @@ default n depends on BOARD_AMD_SERENGETI_CHEETAH +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + int + default 1 + depends on BOARD_AMD_SERENGETI_CHEETAH + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_AMD_SERENGETI_CHEETAH + config HT_CHAIN_END_UNITID_BASE hex default 0x6 @@ -144,11 +149,6 @@ default y depends on BOARD_AMD_SERENGETI_CHEETAH -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - depends on BOARD_AMD_SERENGETI_CHEETAH - config CONSOLE_VGA bool default y

1 0

Is this motherboard suppo
by Anonymous bin ich 28 Sep '09

28 Sep '09

Hi all! I have following laptop: MSI VR-610X Chipset: ATI RS690T + SB600 Procesor: AMD Athlon64 X2 dual-core TK-55 (1.8GHz, FSB 800MHz, 512KB L2) RAM 1GB DDR2 667MHz Hard disk: 100GB SATA Graphics-card: ATI Radeon X1270 Some more info is here: http://browse.geekbench.ca/geekbench2/view/82346 NOTE: It is AMD Sempron 3600+, and not 3800+ as listed in the above link. I am attaching the output of lspci, superiotool, and flashrom in the mail. It appears from the webpage that my motherboard is actually supported with coreboot v3, but SB600 is listed as "WIP". So, should I try it? -- Regards,

3 3

Last known good for Serengeti Cheetah
by Myles Watson 28 Sep '09

28 Sep '09

I'm seeing a triple fault after jumping to the payload. Does anyone know of a Kconfig revision that works for Serengeti Cheetah? As a related question: How hard would it be to add Qemu and SimNOW to the test infrastructure that we have, so that at least those too "boards" get boot tested at commit times? Thanks, Myles

1 1

Need help building
by Roger Sistla 28 Sep '09

28 Sep '09

Greetings , I just started to dabble with coreboot and would like some advice. I have a SuperMicro motherboard with intel chipsets and intel P4 2.8GHz CPU. I have attached an "lspci -vvv" and "flashrom" output at the bottom of the email. I am currently running Ubuntu 8.04 server. Anybody compile coreboot for this type of motherboard and if so what is the best approach ? THanks, /RS -- ======================== Roger Sistla sistla dot roger at gmail dot com ======================== ---------Output from flashrom utility ------------ Calibrating delay loop... OK. No coreboot table found. Found chipset "ICH4/ICH4-L", enabling flash write... OK. SST49LF004A/B found at physical address 0xfff80000. Flash part is SST49LF004A/B (512 KB). No operations were specified. ---------Output from lspci -vvv--------------------- 00:00.0 Host bridge: Intel Corporation 82845G/GL[Brookdale-G]/GE/PE DRAM Controller/Host-Hub Interface (rev 03) Subsystem: Super Micro Computer Inc Unknown device 3680 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- Latency: 0 Region 0: Memory at e8000000 (32-bit, prefetchable) [size=64M] Capabilities: [e4] Vendor Specific Information 00:02.0 VGA compatible controller: Intel Corporation 82845G/GL[Brookdale-G]/GE Chipset Integrated Graphics Device (rev 03) (prog-if 00 [VGA controller]) Subsystem: Super Micro Computer Inc Unknown device 3680 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 5 Region 0: Memory at e0000000 (32-bit, prefetchable) [size=128M] Region 1: Memory at ec100000 (32-bit, non-prefetchable) [size=512K] Capabilities: [d0] Power Management version 1 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:1d.0 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 (rev 02) (prog-if 00 [UHCI]) Subsystem: Super Micro Computer Inc Unknown device 3680 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 4: I/O ports at b800 [size=32] 00:1d.1 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2 (rev 02) (prog-if 00 [UHCI]) Subsystem: Super Micro Computer Inc Unknown device 3680 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin B routed to IRQ 17 Region 4: I/O ports at b000 [size=32] 00:1d.2 USB Controller: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3 (rev 02) (prog-if 00 [UHCI]) Subsystem: Super Micro Computer Inc Unknown device 3680 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at b400 [size=32] 00:1d.7 USB Controller: Intel Corporation 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller (rev 02) (prog-if 20 [EHCI]) Subsystem: Super Micro Computer Inc Unknown device 3680 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin D routed to IRQ 19 Region 0: Memory at ec180000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 82) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR+ Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 I/O behind bridge: 0000a000-0000afff Memory behind bridge: ec000000-ec0fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- 00:1f.0 ISA bridge: Intel Corporation 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00:1f.1 IDE interface: Intel Corporation 82801DB (ICH4) IDE Controller (rev 02) (prog-if 8a [Master SecP PriP]) Subsystem: Super Micro Computer Inc Unknown device 3680 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Interrupt: pin A routed to IRQ 18 Region 0: I/O ports at 01f0 [size=8] Region 1: I/O ports at 03f4 [size=1] Region 2: I/O ports at 0170 [size=8] Region 3: I/O ports at 0374 [size=1] Region 4: I/O ports at cc00 [size=16] Region 5: Memory at ec181000 (32-bit, non-prefetchable) [size=1K] 00:1f.3 SMBus: Intel Corporation 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller (rev 02) Subsystem: Super Micro Computer Inc Unknown device 3680 Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin B routed to IRQ 11 Region 4: I/O ports at 0500 [size=32] 01:02.0 RAID bus controller: Silicon Image, Inc. SiI 3124 PCI-X Serial ATA Controller (rev 02) Subsystem: Silicon Image, Inc. Unknown device 7124 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 17 Region 0: Memory at ec0c8000 (64-bit, non-prefetchable) [size=128] Region 2: Memory at ec0c0000 (64-bit, non-prefetchable) [size=32K] Region 4: I/O ports at a000 [size=16] [virtual] Expansion ROM at ec000000 [disabled] [size=512K] Capabilities: [64] Power Management version 2 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [40] PCI-X non-bridge device Command: DPERE- ERO+ RBC=512 OST=12 Status: Dev=ff:1f.0 64bit+ 133MHz+ SCD- USC- DC=simple DMMRBC=2048 DMOST=12 DMCRS=128 RSCEM- 266MHz- 533MHz- Capabilities: [54] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 01:05.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 02) Subsystem: Intel Corporation Unknown device 004e Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (63750ns min), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 20 Region 0: Memory at ec080000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at a400 [size=64] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [e4] PCI-X non-bridge device Command: DPERE- ERO+ RBC=512 OST=1 Status: Dev=00:00.0 64bit- 133MHz- SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=16 RSCEM- 266MHz- 533MHz- Capabilities: [f0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 01:06.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 02) Subsystem: Intel Corporation Unknown device 004e Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (63750ns min), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 19 Region 0: Memory at ec0a0000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at a800 [size=64] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [e4] PCI-X non-bridge device Command: DPERE- ERO+ RBC=512 OST=1 Status: Dev=00:00.0 64bit- 133MHz- SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=16 RSCEM- 266MHz- 533MHz- Capabilities: [f0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000

3 2

[PATCH] libgcc regparm workaround
by Stefan Reinauer 27 Sep '09

27 Sep '09

programs that are compiled with non-default regparm values are miscompiled if they use libgcc. This patch works around the problem for coreboot. * drop libgcc from coreboot_apc.o, not needed. * wrap libgcc calls into regparm(0) variants so that coreboot can be compiled with other regparm values Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: src/config/Config.lb =================================================================== --- src/config/Config.lb (revision 4675) +++ src/config/Config.lb (working copy) @@ -47,7 +47,7 @@ makerule coreboot_ram.o depends "src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" - action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) -Wl,-$ coreboot.a $(LIBGCC_FILE_NAME) -Wl,-$" + action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,-$ coreboot.a $(LIBGCC_FILE_NAME) -Wl,-$" end makerule coreboot_ram @@ -89,7 +89,7 @@ end makerule coreboot_apc.o - depends "src/arch/$(CONFIG_ARCH)/lib/c_start.o coreboot_apc.a $(LIBGCC_FILE_NAME)" + depends "src/arch/$(CONFIG_ARCH)/lib/c_start.o coreboot_apc.a" action "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^" end Index: src/lib/Makefile.inc =================================================================== --- src/lib/Makefile.inc (revision 4675) +++ src/lib/Makefile.inc (working copy) @@ -12,6 +12,7 @@ obj-y += cbfs.o obj-y += lzma.o #obj-y += lzmadecode.o +obj-y += gcc.o initobj-y += uart8250.o initobj-y += memset.o Index: src/lib/Config.lb =================================================================== --- src/lib/Config.lb (revision 4675) +++ src/lib/Config.lb (working copy) @@ -17,6 +17,8 @@ object fallback_boot.o object compute_ip_checksum.o object version.o +object gcc.o + # Force version.o to recompile every time makedefine .PHONY : version.o Index: src/lib/gcc.c =================================================================== --- src/lib/gcc.c (revision 0) +++ src/lib/gcc.c (revision 0) @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +/* GCC's libgcc handling is quite broken. While the libgcc functions + * are always regparm(0) the code that calls them uses whatever the + * compiler call specifies. Therefore we need a wrapper around those + * functions. + */ + +#define WRAP_LIBGCC_CALL(type, name) \ + type __real_##name(type a, type b) __attribute__((regparm(0))); \ + type __wrap_##name(type a, type b) { return __real_##name(a, b); } + +WRAP_LIBGCC_CALL(long long, __divdi3) +WRAP_LIBGCC_CALL(unsigned long long, __udivdi3) +WRAP_LIBGCC_CALL(long long, __moddi3) +WRAP_LIBGCC_CALL(unsigned long long, __umoddi3) +

3 12

← Newer
1
...
7
8
9
10
11
12
13
...
31
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot September 2009