coreboot April 2009

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[PATCH] [v3] Fix ROM caching on Via C7
by Corey Osgood 14 Apr '09

14 Apr '09

Tested and working on hardware :D -Corey

3 4

[v3] r1164 - in coreboot-v3: arch/x86 arch/x86/via mainboard/jetway
by svn＠coreboot.org 14 Apr '09

14 Apr '09

Author: cozzie Date: 2009-04-14 17:41:33 +0200 (Tue, 14 Apr 2009) New Revision: 1164 Modified: coreboot-v3/arch/x86/pirq_routing.c coreboot-v3/arch/x86/via/stage0.S coreboot-v3/mainboard/jetway/Kconfig Log: Enable caching for Via C7 CPUs, and also improve readability. Tested on hardware and seems to be working. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: coreboot-v3/arch/x86/pirq_routing.c =================================================================== --- coreboot-v3/arch/x86/pirq_routing.c 2009-04-14 13:58:45 UTC (rev 1163) +++ coreboot-v3/arch/x86/pirq_routing.c 2009-04-14 15:41:33 UTC (rev 1164) @@ -26,7 +26,7 @@ #include <console.h> #include <device/device.h> #include <tables.h> -#include <pirq_routing.h> +#include <arch/x86/pirq_routing.h> static void check_pirq_routing_table(struct irq_routing_table *rt) { Modified: coreboot-v3/arch/x86/via/stage0.S =================================================================== --- coreboot-v3/arch/x86/via/stage0.S 2009-04-14 13:58:45 UTC (rev 1163) +++ coreboot-v3/arch/x86/via/stage0.S 2009-04-14 15:41:33 UTC (rev 1164) @@ -35,6 +35,11 @@ #define CACHE_RAM_CODE_SEG 0x18 #define CACHE_RAM_DATA_SEG 0x20 +/* Note: disable this only if you want the system to boot REEEEALLY slow for debugging */ +#ifndef CACHE_CBROM +#define CACHE_CBROM +#endif + .align 4 .globl protected_stage0 protected_stage0: @@ -101,39 +106,37 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: /* MTRRPhysBase */ - movl $0x200, %ecx + movl $(MTRRphysBase_MSR(0)), %ecx xorl %edx, %edx movl $(CacheBase|MTRR_TYPE_WRBACK),%eax wrmsr /* MTRRPhysMask */ - movl $0x201, %ecx + movl $(MTRRphysMask_MSR(0)), %ecx /* This assumes we never access addresses above 2^36 in CAR. */ movl $0x0000000f,%edx - movl $(~(CacheSize-1)|0x800),%eax + movl $(~(CacheSize-1)|(1<<11)), %eax wrmsr -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) - /* enable write base caching so we can do execute in place - * on the flash rom. - */ +#ifdef CACHE_CBROM + /* enable write base caching. */ /* MTRRPhysBase */ - movl $0x202, %ecx + movl $(MTRRphysBase_MSR(1)), %ecx xorl %edx, %edx - movl $(XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax + movl $((0x100000000 - (CONFIG_COREBOOT_ROMSIZE_KB * 1024))|MTRR_TYPE_WRBACK),%eax wrmsr /* MTRRPhysMask */ - movl $0x203, %ecx + movl $(MTRRphysMask_MSR(1)), %ecx movl $0x0000000f,%edx - movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~((CONFIG_COREBOOT_ROMSIZE_KB * 1024) - 1) | (1<<11)), %eax wrmsr -#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CACHE_CBROM */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx /* Enable Variable and Fixed MTRRs */ - movl $0x00000800, %eax + movl $(1<<11), %eax wrmsr /* enable cache */ @@ -153,12 +156,12 @@ xorl %eax, %eax rep stosl -#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) - /* Read the XIP area */ - movl XIP_ROM_BASE, %esi - movl $(XIP_ROM_SIZE>>2), %ecx +#ifdef CACHE_CBROM + /* Read the ROM area */ + movl (0x100000000 - (CONFIG_COREBOOT_ROMSIZE_KB * 1024)), %esi + movl $((CONFIG_COREBOOT_ROMSIZE_KB * 1024) >> 2), %ecx rep lodsl -#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ +#endif /* CACHE_CBROM */ /* The key point of this CAR code is C7 cache does not turn into * "no fill" mode, which is not compatible with general CAR code. Modified: coreboot-v3/mainboard/jetway/Kconfig =================================================================== --- coreboot-v3/mainboard/jetway/Kconfig 2009-04-14 13:58:45 UTC (rev 1163) +++ coreboot-v3/mainboard/jetway/Kconfig 2009-04-14 15:41:33 UTC (rev 1164) @@ -28,7 +28,7 @@ select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237 select SUPERIO_FINTEK_F71805F - select PIRQ_TABLE +## select PIRQ_TABLE help Jetway J7F2-Series board. endchoice

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Re: [coreboot] SeaBIOS HAVE_HIGH_TABLES
by Jason Wang 14 Apr '09

14 Apr '09

On Tue, Apr 14, 2009 at 11:37 PM, Jason Wang <wangqingpei(a)gmail.com> wrote: > On Tue, Apr 14, 2009 at 8:13 PM, Joseph Smith <joe(a)settoplinux.org> wrote: >> >> Hello, >> I was just checking out the SeaBIOS Wiki page updates (great job by the >> way:-)). I am wondering about the HAVE_HIGH_TABLES section. It seems so say >> to statically add you memory size (uint64_t high_tables_base = ( >> <memorysize> )*1024*1024 - (64*1024); where <memorysize> is the amount of >> memory (in MiB) available on the target machine). This would not be good if >> you want to change memory sizes, you would have to rebuild every time, or it is an option method if the board does not have HAVE_HIGH_TABLE. It should pass the TOM variable from some other places which based on certain mainboard. I know that M2M have already realized that. >> am I reading it wrong? Why not pass a TOM variable from raminit.c or >> northbridge.c or something like that? >> >> -- >> Thanks, >> Joseph Smith >> Set-Top-Linux >> www.settoplinux.org >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > > > > -- > Jason Wang > Peking University > -- Jason Wang Peking University

1 0

v2/src romfs->cbfs rename
by Peter Stuge 14 Apr '09

14 Apr '09

6 12

Porting coreboot to Intel Atom (Silverthorne) & SCH US15W (Poulsbo) chipset
by Mansoor 14 Apr '09

14 Apr '09

Hi, I have a Atom Silverthorne Poulsbo based board (http://www.iwavesystems.com/iW-Q7.htm). I want to port coreboot on this platform. I would like to know if anybody has started/suceeded in porting coreboot to Atom, also if there is anyone interested in such a port. I saw two threads in mail archive but with little information,but it was posted long ago. Please refer these two threads for more information on Silverthorne and Poulsbo. http://www.mail-archive.com/coreboot@coreboot.org/msg02856.html http://www.coreboot.org/pipermail/coreboot/2008-May/034189.html If anyone can suggest/guide me in following, it will be helpful in getting started in right track. 1)Which version of coreboot can be used (v2 or v3) ? 2)Which platform (CPU,motherboard,EC) can be taken as reference ? Thanks Mansoor ------------------------------------------------------------------------------- DISCLAIMER: This e-mail and any attachment (s) is for authorised use by the intended recipient (s) only. It may contain proprietary material, confidential information and/or be subject to the legal privilege of iWave Systems Technologies Private Limited. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from retaining, using, copying, alerting or disclosing the content of this message. Thank you for your co-operation. ------------------------------------------------------------------------------

4 3

yabel: romfs->cbfs rename
by Peter Stuge 14 Apr '09

14 Apr '09

Not sure about this one. Help? //Peter

2 3

[v3] r1163 - coreboot-v3/util/x86emu/yabel/compat
by svn＠coreboot.org 14 Apr '09

14 Apr '09

Author: phueper Date: 2009-04-14 15:58:45 +0200 (Tue, 14 Apr 2009) New Revision: 1163 Modified: coreboot-v3/util/x86emu/yabel/compat/of.h Log: remove unnecessary function definition Signed-off-by: Pattrick Hueper <phueper(a)hueper.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/util/x86emu/yabel/compat/of.h =================================================================== --- coreboot-v3/util/x86emu/yabel/compat/of.h 2009-03-23 23:55:58 UTC (rev 1162) +++ coreboot-v3/util/x86emu/yabel/compat/of.h 2009-04-14 13:58:45 UTC (rev 1163) @@ -48,7 +48,6 @@ int of_yield(void); void * of_set_callback(void *); -unsigned int romfs_lookup(const char *, void **); int vpd_read(unsigned int , unsigned int , char *); int vpd_write(unsigned int , unsigned int , char *); int write_mm_log(char *, unsigned int , unsigned short );

1 0

SeaBIOS HAVE_HIGH_TABLES
by Joseph Smith 14 Apr '09

14 Apr '09

Hello, I was just checking out the SeaBIOS Wiki page updates (great job by the way:-)). I am wondering about the HAVE_HIGH_TABLES section. It seems so say to statically add you memory size (uint64_t high_tables_base = ( <memorysize> )*1024*1024 - (64*1024); where <memorysize> is the amount of memory (in MiB) available on the target machine). This would not be good if you want to change memory sizes, you would have to rebuild every time, or am I reading it wrong? Why not pass a TOM variable from raminit.c or northbridge.c or something like that? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

1 0

build service results for r4113
by coreboot information 14 Apr '09

14 Apr '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stuge" checked in revision 4113 to the coreboot repository. This caused the following changes: Change Log: v2/src romfs->cbfs rename This also has the config tool changes in v2/util. Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4113&device=serengeti_chee… Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4113&device=msm800sev&vend… Compilation of pcengines:alix1c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4113&device=alix1c&vendor=… Compilation of supermicro:h8dme is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4113&device=h8dme&vendor=s… Compilation of supermicro:h8dmr is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4113&device=h8dmr&vendor=s… Compilation of via:epia-cn has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4113&device=epia-cn&vendor… If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4113 - in trunk/coreboot-v2: src/arch/i386 src/boot src/config src/devices src/include src/lib src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0 src/mainboard/advantech/pcm-5820 src/mainboard/amd/db800 src/mainboard/amd/dbm690t src/mainboard/amd/norwich src/mainboard/amd/pistachio src/mainboard/amd/rumba src/mainboard/amd/serengeti_cheetah src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard/arima/hdama src/mainboard/artecgroup/dbe61 src/mainboa
by svn＠coreboot.org 14 Apr '09

14 Apr '09

Author: stuge Date: 2009-04-14 09:40:01 +0200 (Tue, 14 Apr 2009) New Revision: 4113 Added: trunk/coreboot-v2/src/include/cbfs.h trunk/coreboot-v2/src/lib/cbfs.c Modified: trunk/coreboot-v2/src/arch/i386/Config.lb trunk/coreboot-v2/src/boot/Config.lb trunk/coreboot-v2/src/boot/hardwaremain.c trunk/coreboot-v2/src/boot/selfboot.c trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/devices/pci_rom.c trunk/coreboot-v2/src/lib/Config.lb trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb trunk/coreboot-v2/src/mainboard/via/epia/Options.lb trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb trunk/coreboot-v2/util/newconfig/config.g Log: v2/src romfs->cbfs rename This also has the config tool changes in v2/util. Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/Config.lb =================================================================== --- trunk/coreboot-v2/src/arch/i386/Config.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/arch/i386/Config.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -80,8 +80,8 @@ else makerule coreboot.rom depends "coreboot.strip buildrom $(PAYLOAD-1)" - action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_ROMFS) -eq 1 ]; then PAYLOAD=/dev/null; touch romfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)" - action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 -a $(CONFIG_ROMFS) -eq 1 ]; then echo l > romfs-support; fi" + action "PAYLOAD=$(PAYLOAD-1); if [ $(CONFIG_CBFS) -eq 1 ]; then PAYLOAD=/dev/null; touch cbfs-support; fi; ./buildrom $< $@ $$PAYLOAD $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)" + action "if [ $(CONFIG_COMPRESSED_PAYLOAD_LZMA) -eq 1 -a $(CONFIG_CBFS) -eq 1 ]; then echo l > cbfs-support; fi" end end Modified: trunk/coreboot-v2/src/boot/Config.lb =================================================================== --- trunk/coreboot-v2/src/boot/Config.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/boot/Config.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,6 +1,6 @@ object elfboot.o object hardwaremain.o -if CONFIG_ROMFS +if CONFIG_CBFS object selfboot.o end if CONFIG_FS_PAYLOAD Modified: trunk/coreboot-v2/src/boot/hardwaremain.c =================================================================== --- trunk/coreboot-v2/src/boot/hardwaremain.c 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/boot/hardwaremain.c 2009-04-14 07:40:01 UTC (rev 4113) @@ -36,7 +36,7 @@ #include <part/hard_reset.h> #include <part/init_timer.h> #include <boot/elf.h> -#include <romfs.h> +#include <cbfs.h> #if HAVE_ACPI_RESUME == 1 #include <arch/acpi.h> #endif @@ -112,11 +112,11 @@ * write our configuration tables. */ lb_mem = write_tables(); -#if CONFIG_ROMFS == 1 +#if CONFIG_CBFS == 1 # if USE_FALLBACK_IMAGE == 1 - void (*pl)(void) = romfs_load_payload(lb_mem, "fallback/payload"); + void (*pl)(void) = cbfs_load_payload(lb_mem, "fallback/payload"); # else - void (*pl)(void) = romfs_load_payload(lb_mem, "normal/payload"); + void (*pl)(void) = cbfs_load_payload(lb_mem, "normal/payload"); # endif #endif Modified: trunk/coreboot-v2/src/boot/selfboot.c =================================================================== --- trunk/coreboot-v2/src/boot/selfboot.c 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/boot/selfboot.c 2009-04-14 07:40:01 UTC (rev 4113) @@ -28,7 +28,7 @@ #include <stdint.h> #include <stdlib.h> #include <string.h> -#include <romfs.h> +#include <cbfs.h> #ifndef CONFIG_BIG_ENDIAN #define ntohl(x) ( ((x&0xff)<<24) | ((x&0xff00)<<8) | \ @@ -70,12 +70,12 @@ unsigned short ip_checksum; }; -int romfs_self_decompress(int algo, void *src,struct segment *new) +int cbfs_self_decompress(int algo, void *src,struct segment *new) { u8 *dst; /* for uncompressed, it's easy: just point at the area in ROM */ - if (algo == ROMFS_COMPRESS_NONE) { + if (algo == CBFS_COMPRESS_NONE) { new->s_srcaddr = (u32) src; new->s_filesz = new->s_memsz; return 0; @@ -91,21 +91,21 @@ switch(algo) { #ifdef CONFIG_COMPRESSION_LZMA - case ROMFS_COMPRESS_LZMA: { + case CBFS_COMPRESS_LZMA: { unsigned long ulzma(unsigned char *src, unsigned char *dst); ulzma(src, dst); } #endif #ifdef CONFIG_COMPRESSION_NRV2B - case ROMFS_COMPRESS_NRV2B: { + case CBFS_COMPRESS_NRV2B: { unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p); unsigned long tmp; unrv2b(src, dst, &tmp); } #endif default: - printk_info( "ROMFS: Unknown compression type %d\n", + printk_info( "CBFS: Unknown compression type %d\n", algo); return -1; } @@ -341,13 +341,13 @@ static int build_self_segment_list( struct segment *head, unsigned long bounce_buffer, struct lb_memory *mem, - struct romfs_payload *payload, u32 *entry) + struct cbfs_payload *payload, u32 *entry) { struct segment *new; struct segment *ptr; u8 *data; int datasize; - struct romfs_payload_segment *segment, *first_segment; + struct cbfs_payload_segment *segment, *first_segment; memset(head, 0, sizeof(*head)); head->phdr_next = head->phdr_prev = head; head->next = head->prev = head; @@ -372,10 +372,10 @@ datasize = ntohl(segment->len); /* figure out decompression, do it, get pointer to the area */ - if (romfs_self_decompress(ntohl(segment->compression), + if (cbfs_self_decompress(ntohl(segment->compression), ((unsigned char *) first_segment) + ntohl(segment->offset), new)) { - printk_emerg("romfs_self_decompress failed\n"); + printk_emerg("cbfs_self_decompress failed\n"); return; } printk_debug("New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", @@ -432,7 +432,7 @@ } static int load_self_segments( - struct segment *head, struct romfs_payload *payload) + struct segment *head, struct cbfs_payload *payload) { unsigned long offset; struct segment *ptr; @@ -478,7 +478,7 @@ return 0; } -int selfboot(struct lb_memory *mem, struct romfs_payload *payload) +int selfboot(struct lb_memory *mem, struct cbfs_payload *payload) { void *entry; struct segment head; Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/config/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -679,10 +679,10 @@ export always comment "Enable FAT filesystem support" end -define CONFIG_ROMFS +define CONFIG_CBFS default 0 export always - comment "The new ROMFS file system" + comment "The new CBFS file system" end define AUTOBOOT_DELAY default 2 Modified: trunk/coreboot-v2/src/devices/pci_rom.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_rom.c 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/devices/pci_rom.c 2009-04-14 07:40:01 UTC (rev 4113) @@ -27,7 +27,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <string.h> -#include <romfs.h> +#include <cbfs.h> struct rom_header * pci_rom_probe(struct device *dev) { @@ -35,10 +35,10 @@ struct rom_header *rom_header; struct pci_data *rom_data; - if (CONFIG_ROMFS) { + if (CONFIG_CBFS) { void *v; /* if it's in FLASH, then it's as if dev->on_mainboard was true */ - v = romfs_load_optionrom(dev->vendor, dev->device, NULL); + v = cbfs_load_optionrom(dev->vendor, dev->device, NULL); printk_debug("In cbfs, rom address for %s = %lx\n", dev_path(dev), rom_address); if (v) { Copied: trunk/coreboot-v2/src/include/cbfs.h (from rev 4109, trunk/coreboot-v2/src/include/romfs.h) =================================================================== --- trunk/coreboot-v2/src/include/cbfs.h (rev 0) +++ trunk/coreboot-v2/src/include/cbfs.h 2009-04-14 07:40:01 UTC (rev 4113) @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net> + * + * This file is dual-licensed. You can choose between: + * - The GNU GPL, version 2, as published by the Free Software Foundation + * - The revised BSD license (without advertising clause) + * + * --------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * --------------------------------------------------------------------------- + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * --------------------------------------------------------------------------- + */ + +#ifndef _CBFS_H_ +#define _CBFS_H_ + +/** These are standard values for the known compression + alogrithms that coreboot knows about for stages and + payloads. Of course, other LAR users can use whatever + values they want, as long as they understand them. */ + +#define CBFS_COMPRESS_NONE 0 +#define CBFS_COMPRESS_LZMA 1 +#define CBFS_COMPRESS_NRV2B 2 + +/** These are standard component types for well known + components (i.e - those that coreboot needs to consume. + Users are welcome to use any other value for their + components */ + +#define CBFS_TYPE_STAGE 0x10 +#define CBFS_TYPE_PAYLOAD 0x20 +#define CBFS_TYPE_OPTIONROM 0x30 + +/** this is the master cbfs header - it need to be + located somewhere in the bootblock. Where it + actually lives is up to coreboot. A pointer to + this header will live at 0xFFFFFFFc, so we can + easily find it. */ + +#define CBFS_HEADER_MAGIC 0x4F524243 +#define CBFS_HEADPTR_ADDR 0xFFFFFFFc +#define VERSION1 0x31313131 + +struct cbfs_header { + u32 magic; + u32 version; + u32 romsize; + u32 bootblocksize; + u32 align; + u32 offset; + u32 pad[2]; +} __attribute__((packed)); + +/** This is a component header - every entry in the CBFS + will have this header. + + This is how the component is arranged in the ROM: + + -------------- <- 0 + component header + -------------- <- sizeof(struct component) + component name + -------------- <- offset + data + ... + -------------- <- offset + len +*/ + +#define CBFS_FILE_MAGIC "LARCHIVE" + +struct cbfs_file { + char magic[8]; + u32 len; + u32 type; + u32 checksum; + u32 offset; +} __attribute__((packed)); + +/*** Component sub-headers ***/ + +/* Following are component sub-headers for the "standard" + component types */ + +/** This is the sub-header for stage components. Stages are + loaded by coreboot during the normal boot process */ + +struct cbfs_stage { + u32 compression; /** Compression type */ + u64 entry; /** entry point */ + u64 load; /** Where to load in memory */ + u32 len; /** length of data to load */ + u32 memlen; /** total length of object in memory */ +} __attribute__((packed)); + +/** this is the sub-header for payload components. Payloads + are loaded by coreboot at the end of the boot process */ + +struct cbfs_payload_segment { + u32 type; + u32 compression; + u32 offset; + u64 load_addr; + u32 len; + u32 mem_len; +} __attribute__((packed)); + +struct cbfs_payload { + struct cbfs_payload_segment segments; +}; + +#define PAYLOAD_SEGMENT_CODE 0x45444F43 +#define PAYLOAD_SEGMENT_DATA 0x41544144 +#define PAYLOAD_SEGMENT_BSS 0x20535342 +#define PAYLOAD_SEGMENT_PARAMS 0x41524150 +#define PAYLOAD_SEGMENT_ENTRY 0x52544E45 + +struct cbfs_optionrom { + u32 compression; + u32 len; +} __attribute__((packed)); + +#define CBFS_NAME(_c) (((char *) (_c)) + sizeof(struct cbfs_file)) +#define CBFS_SUBHEADER(_p) ( (void *) ((((u8 *) (_p)) + ntohl((_p)->offset))) ) + +void * cbfs_load_payload(struct lb_memory *lb_mem, const char *name); +void * cbfs_load_stage(const char *name); +int cbfs_execute_stage(const char *name); +void * cbfs_get_file(const char *name); +void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest); +int run_address(void *f); + +#endif + Modified: trunk/coreboot-v2/src/lib/Config.lb =================================================================== --- trunk/coreboot-v2/src/lib/Config.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/lib/Config.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -28,6 +28,6 @@ initobject memcmp.o end -if CONFIG_ROMFS - object romfs.o +if CONFIG_CBFS + object cbfs.o end Copied: trunk/coreboot-v2/src/lib/cbfs.c (from rev 4109, trunk/coreboot-v2/src/lib/romfs.c) =================================================================== --- trunk/coreboot-v2/src/lib/cbfs.c (rev 0) +++ trunk/coreboot-v2/src/lib/cbfs.c 2009-04-14 07:40:01 UTC (rev 4113) @@ -0,0 +1,252 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008, Jordan Crouse <jordan(a)cosmicpenguin.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <boot/coreboot_tables.h> +#include <cbfs.h> + +#ifndef CONFIG_BIG_ENDIAN +#define ntohl(x) ( ((x&0xff)<<24) | ((x&0xff00)<<8) | \ + ((x&0xff0000) >> 8) | ((x&0xff000000) >> 24) ) +#else +#define ntohl(x) (x) +#endif + +int run_address(void *f); + +int cbfs_decompress(int algo, void *src, void *dst, int len) +{ + switch(algo) { + case CBFS_COMPRESS_NONE: + memcpy(dst, src, len); + return 0; + +#ifdef CONFIG_COMPRESSION_LZMA + + case CBFS_COMPRESS_LZMA: { + unsigned long ulzma(unsigned char *src, unsigned char *dst); + ulzma(src, dst); + } + return 0; +#endif + +#ifdef CONFIG_COMPRESSION_NRV2B + case CBFS_COMPRESS_NRV2B: { + unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p); + unsigned long tmp; + + unrv2b(src, dst, &tmp); + } + return 0; +#endif + default: + printk_info( "CBFS: Unknown compression type %d\n", + algo); + return -1; + } +} + +int cbfs_check_magic(struct cbfs_file *file) +{ + return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0; +} + +struct cbfs_header *cbfs_master_header(void) +{ + struct cbfs_header *header; + + void *ptr = (void *)*((unsigned long *) CBFS_HEADPTR_ADDR); + printk_debug("Check CBFS header at %p\n", ptr); + header = (struct cbfs_header *) ptr; + + printk_debug("magic is %08x\n", ntohl(header->magic)); + if (ntohl(header->magic) != CBFS_HEADER_MAGIC) { + printk_err("NO CBFS HEADER\n"); + return NULL; + } + + printk_debug("Found CBFS header at %p\n", ptr); + return header; +} + +struct cbfs_file *cbfs_find(const char *name) +{ + struct cbfs_header *header = cbfs_master_header(); + unsigned long offset; + + if (header == NULL) + return NULL; + offset = 0 - ntohl(header->romsize) + ntohl(header->offset); + + while(1) { + struct cbfs_file *file = (struct cbfs_file *) offset; + if (cbfs_check_magic(file)) printk_info("Check %s\n", CBFS_NAME(file)); + if (cbfs_check_magic(file) && + !strcmp(CBFS_NAME(file), name)) + return file; + + offset += ntohl(header->align); + + if (offset < 0xFFFFFFFF - ntohl(header->romsize)) + return NULL; + } +} + +struct cbfs_stage *cbfs_find_file(const char *name, int type) +{ + struct cbfs_file *file = cbfs_find(name); + + if (file == NULL) { + printk_info( "CBFS: Could not find file %s\n", + name); + return NULL; + } + + if (ntohl(file->type) != type) { + printk_info( "CBFS: File %s is of type %x instead of" + "type %x\n", name, file->type, type); + + return NULL; + } + + return (void *) CBFS_SUBHEADER(file); +} + +void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest) +{ + char name[17]; + struct cbfs_optionrom *orom; + u8 *src; + + sprintf(name,"pci%04x,%04x.rom", vendor, device); + + orom = (struct cbfs_optionrom *) + cbfs_find_file(name, CBFS_TYPE_OPTIONROM); + + if (orom == NULL) + return NULL; + + /* They might have specified a dest address. If so, we can decompress. + * If not, there's not much hope of decompressing or relocating the rom. + * in the common case, the expansion rom is uncompressed, we + * pass 0 in for the dest, and all we have to do is find the rom and + * return a pointer to it. + */ + + /* BUG: the cbfstool is (not yet) including a cbfs_optionrom header */ + src = ((unsigned char *) orom); // + sizeof(struct cbfs_optionrom); + + if (! dest) + return src; + + if (cbfs_decompress(ntohl(orom->compression), + src, + dest, + ntohl(orom->len))) + return NULL; + + return dest; +} + +void * cbfs_load_payload(struct lb_memory *lb_mem, const char *name) +{ + int selfboot(struct lb_memory *mem, struct cbfs_payload *payload); + struct cbfs_payload *payload = (struct cbfs_payload *) + cbfs_find_file(name, CBFS_TYPE_PAYLOAD); + + struct cbfs_payload_segment *segment, *first_segment; + + if (payload == NULL) + return (void *) -1; + printk_debug("Got a payload\n"); + first_segment = segment = &payload->segments; + selfboot(lb_mem, payload); + printk_emerg("SELFBOOT RETURNED!\n"); + + return (void *) -1; +} + +void * cbfs_load_stage(const char *name) +{ + struct cbfs_stage *stage = (struct cbfs_stage *) + cbfs_find_file(name, CBFS_TYPE_STAGE); + /* this is a mess. There is no ntohll. */ + /* for now, assume compatible byte order until we solve this. */ + u32 entry; + + if (stage == NULL) + return (void *) -1; + + printk_info("Stage: load @ %d/%d bytes, enter @ %llx\n", + ntohl((u32) stage->load), ntohl(stage->memlen), + stage->entry); + memset((void *) ntohl((u32) stage->load), 0, ntohl(stage->memlen)); + + if (cbfs_decompress(ntohl(stage->compression), + ((unsigned char *) stage) + + sizeof(struct cbfs_stage), + (void *) ntohl((u32) stage->load), + ntohl(stage->len))) + return (void *) -1; + + entry = stage->entry; +// return (void *) ntohl((u32) stage->entry); + return (void *) entry; +} + +void * cbfs_get_file(const char *name) +{ + return cbfs_find(name); +} + +int cbfs_execute_stage(const char *name) +{ + struct cbfs_stage *stage = (struct cbfs_stage *) + cbfs_find_file(name, CBFS_TYPE_STAGE); + + if (stage == NULL) + return 1; + + if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) { + printk_info( "CBFS: Unable to run %s: Compressed file" + "Not supported for in-place execution\n", name); + return 1; + } + + /* FIXME: This isn't right */ + printk_info( "CBFS: run @ %p\n", (void *) ntohl((u32) stage->entry)); + return run_address((void *) ntohl((u32) stage->entry)); +} + +/** + * run_address is passed the address of a function taking no parameters and + * jumps to it, returning the result. + * @param f the address to call as a function. + * returns value returned by the function. + */ + +int run_address(void *f) +{ + int (*v) (void); + v = f; + return v(); +} + Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -98,8 +98,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -98,8 +98,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -99,8 +99,8 @@ default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb. # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -104,8 +104,8 @@ default MAXIMUM_CONSOLE_LOGLEVEL = 9 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/amd/db800/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -180,8 +180,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -302,8 +302,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -180,8 +180,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -302,8 +302,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -161,8 +161,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -330,8 +330,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -18,7 +18,7 @@ # uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -365,8 +365,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/arima/hdama/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -243,8 +243,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -180,8 +180,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -104,8 +104,8 @@ default MAXIMUM_CONSOLE_LOGLEVEL = 9 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_PIRQ_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT uses HAVE_HARD_RESET @@ -163,8 +163,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses USE_FAILOVER_IMAGE @@ -168,8 +168,8 @@ default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -18,7 +18,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -168,8 +168,8 @@ default MAXIMUM_CONSOLE_LOGLEVEL = 8 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -18,7 +18,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -176,8 +176,8 @@ default MAXIMUM_CONSOLE_LOGLEVEL = 9 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -98,8 +98,8 @@ default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb. # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -159,8 +159,8 @@ default CONFIG_UDELAY_TSC=1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/asus/p2b/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -99,8 +99,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -105,8 +105,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -98,8 +98,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -98,8 +98,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/axus/tc320/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -104,8 +104,8 @@ default MAXIMUM_CONSOLE_LOGLEVEL = 6 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -98,8 +98,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -104,8 +104,8 @@ default MAXIMUM_CONSOLE_LOGLEVEL = 6 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -105,8 +105,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -98,8 +98,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -263,8 +263,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -98,8 +98,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/dell/s1850/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -229,8 +229,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -116,8 +116,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -124,8 +124,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -180,8 +180,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -166,8 +166,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -3,7 +3,7 @@ ## uses PCIC0_CFGADDR -uses CONFIG_ROMFS +uses CONFIG_CBFS uses PCIC0_CFGDATA uses ISA_IO_BASE uses ISA_MEM_BASE @@ -143,8 +143,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -44,13 +44,13 @@ uses DEFAULT_CONSOLE_LOGLEVEL uses MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_ROMFS +uses CONFIG_CBFS default CONFIG_CONSOLE_SERIAL8250=1 default DEFAULT_CONSOLE_LOGLEVEL=8 default MAXIMUM_CONSOLE_LOGLEVEL=8 -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE = 256*1024 Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -98,8 +98,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -22,7 +22,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -354,8 +354,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -358,8 +358,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/ibm/e325/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -222,8 +222,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/ibm/e326/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -228,8 +228,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -147,8 +147,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -174,8 +174,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -106,8 +106,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/intel/jarrell/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -243,8 +243,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -18,7 +18,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -226,8 +226,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -18,7 +18,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -228,8 +228,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME uses HAVE_PIRQ_TABLE @@ -241,8 +241,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -329,8 +329,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -229,8 +229,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -228,8 +228,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -106,8 +106,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -72,7 +72,7 @@ uses MMCONF_SUPPORT uses MMCONF_BASE_ADDRESS uses CONFIG_GFXUMA -uses CONFIG_ROMFS +uses CONFIG_CBFS # uses MAINBOARD @@ -325,9 +325,9 @@ default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" # -# ROMFS +# CBFS # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 ### End Options.lb end Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -161,8 +161,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -21,7 +21,7 @@ ## Based on Options.lb from AMD's DB800 mainboard. uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -210,8 +210,8 @@ default MAXIMUM_CONSOLE_LOGLEVEL = 8 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -21,7 +21,7 @@ ## Based on Options.lb from AMD's DB800 mainboard. uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -210,8 +210,8 @@ default MAXIMUM_CONSOLE_LOGLEVEL = 8 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/motorola/sandpoint/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses CONFIG_SANDPOINT_ALTIMUS -uses CONFIG_ROMFS +uses CONFIG_CBFS uses CONFIG_SANDPOINT_TALUS uses CONFIG_SANDPOINT_UNITY uses CONFIG_SANDPOINT_VALIS @@ -125,8 +125,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses ISA_IO_BASE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses ISA_MEM_BASE uses PCIC0_CFGADDR uses PCIC0_CFGDATA @@ -120,8 +120,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/msi/ms6119/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -98,8 +98,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/msi/ms6147/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -98,8 +98,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -97,8 +97,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -21,7 +21,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses USE_FAILOVER_IMAGE @@ -322,8 +322,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses USE_FAILOVER_IMAGE @@ -187,8 +187,8 @@ default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -23,7 +23,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -331,8 +331,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -23,7 +23,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -310,8 +310,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -97,8 +97,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/newisys/khepri/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -246,8 +246,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -352,8 +352,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/olpc/btest/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -162,8 +162,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -162,8 +162,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -198,8 +198,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses CC -uses CONFIG_ROMFS +uses CONFIG_CBFS uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_VGA uses CONFIG_COMPRESSED_PAYLOAD_LZMA @@ -95,8 +95,8 @@ default MAINBOARD_VENDOR = "RCA" default MAINBOARD_PART_NUMBER = "RM4100" # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -279,8 +279,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -349,8 +349,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -349,8 +349,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -230,8 +230,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -230,8 +230,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -230,8 +230,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -229,8 +229,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -229,8 +229,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -137,8 +137,8 @@ default HOSTCC="gcc" # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -105,8 +105,8 @@ default MAXIMUM_CONSOLE_LOGLEVEL = 6 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses CC -uses CONFIG_ROMFS +uses CONFIG_CBFS uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_CONSOLE_VGA uses CONFIG_COMPRESSED_PAYLOAD_LZMA @@ -95,8 +95,8 @@ default MAINBOARD_VENDOR = "THOMSON" default MAINBOARD_PART_NUMBER = "IP1000" # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/totalimpact/briq/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -3,7 +3,7 @@ ## uses TTYS0_DIV -uses CONFIG_ROMFS +uses CONFIG_CBFS uses TTYS0_BASE uses CONFIG_BRIQ_750FX uses CONFIG_BRIQ_7400 @@ -127,8 +127,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s1846/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -99,8 +99,8 @@ default CONFIG_PCI_ROM_RUN = 1 # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s2735/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -256,8 +256,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s2850/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -247,8 +247,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s2875/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -248,8 +248,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s2880/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -247,8 +247,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s2881/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -264,8 +264,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s2882/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -247,8 +247,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s2885/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -274,8 +274,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s2891/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -307,8 +307,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s2892/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -295,8 +295,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -314,8 +314,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -354,8 +354,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses HAVE_ACPI_TABLES uses HAVE_ACPI_RESUME @@ -362,8 +362,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s4880/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -256,8 +256,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/tyan/s4882/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -255,8 +255,8 @@ ### End Options.lb # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/via/epia/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/via/epia/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_ROMFS +uses CONFIG_CBFS uses DEFAULT_CONSOLE_LOGLEVEL uses CONFIG_CONSOLE_SERIAL8250 uses TTYS0_BAUD @@ -143,8 +143,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -20,7 +20,7 @@ ## uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -82,7 +82,7 @@ default HAVE_HARD_RESET = 0 default HAVE_PIRQ_TABLE = 1 default IRQ_SLOT_COUNT = 9 -default HAVE_ACPI_TABLES = 0 +default HAVE_ACPI_TABLES = 1 default HAVE_OPTION_TABLE = 1 default ROM_IMAGE_SIZE = 64 * 1024 default FALLBACK_SIZE = ROM_SIZE @@ -106,8 +106,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/via/epia-m/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -1,5 +1,5 @@ uses HAVE_MP_TABLE -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -145,8 +145,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/src/mainboard/via/pc2500e/Options.lb 2009-04-14 07:40:01 UTC (rev 4113) @@ -19,7 +19,7 @@ ## uses CONFIG_SMP -uses CONFIG_ROMFS +uses CONFIG_CBFS uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE @@ -114,8 +114,8 @@ # -# ROMFS +# CBFS # # -default CONFIG_ROMFS=0 +default CONFIG_CBFS=0 end Modified: trunk/coreboot-v2/util/newconfig/config.g =================================================================== --- trunk/coreboot-v2/util/newconfig/config.g 2009-04-14 06:38:15 UTC (rev 4112) +++ trunk/coreboot-v2/util/newconfig/config.g 2009-04-14 07:40:01 UTC (rev 4113) @@ -2224,11 +2224,11 @@ file = safe_open(makefilepath, 'w+') writemakefileheader(file, makefilepath) - # Hack to get the necessary settings (CONFIG_ROMFS): + # Hack to get the necessary settings (CONFIG_CBFS): file.write("include %s/Makefile.settings\n\n" % romimages.keys()[0]) # main rule - file.write("ifeq \"$(CONFIG_ROMFS)\" \"1\"\n") + file.write("ifeq \"$(CONFIG_CBFS)\" \"1\"\n") file.write("\nall: ") for i in buildroms: file.write(" %sfs" % i.name) @@ -2240,8 +2240,8 @@ file.write("\n") file.write("endif\n\n") - # romtool rules - file.write("\nromtool:\n\tmkdir -p tools/lzma\n\t$(MAKE) -C $(TOP)/util/romtool obj=$(shell pwd)\n\n") + # cbfstool rules + file.write("\ncbfstool:\n\tmkdir -p tools/lzma\n\t$(MAKE) -C $(TOP)/util/cbfstool obj=$(shell pwd)\n\n") file.write("include Makefile.settings\n\n") for i, o in romimages.items(): @@ -2278,17 +2278,17 @@ romsize = getoption("ROM_SIZE", image) # i.name? That can not be right, can it? - file.write("%sfs: %s romtool\n" %(i.name,i.name)); - file.write("\trm -f coreboot.romfs\n"); - file.write("\t./romtool %sfs create %s %s %s.bootblock\n" % (i.name, romsize, bootblocksize, i.name)) + file.write("%sfs: %s cbfstool\n" %(i.name,i.name)); + file.write("\trm -f coreboot.cbfs\n"); + file.write("\t./cbfstool %sfs create %s %s %s.bootblock\n" % (i.name, romsize, bootblocksize, i.name)) for i in buildroms: for j in i.roms: #failover is a hack that will go away soon. if (j != "failover") and (rommapping[j] != "/dev/null"): - file.write("\tif [ -f %s/romfs-support ]; then ./romtool %sfs add-payload %s %s/payload `cat %s/romfs-support`; fi\n" % (j, i.name, rommapping[j], j, j)) - file.write("\t ./romtool %sfs print\n" % i.name) + file.write("\tif [ -f %s/cbfs-support ]; then ./cbfstool %sfs add-payload %s %s/payload `cat %s/cbfs-support`; fi\n" % (j, i.name, rommapping[j], j, j)) + file.write("\t ./cbfstool %sfs print\n" % i.name) - file.write(".PHONY: all clean romtool") + file.write(".PHONY: all clean cbfstool") for i in romimages.keys(): file.write(" %s-clean" % i) for i, o in romimages.items():

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coreboot April 2009