coreboot April 2009

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[PATCH] add high tables support for supermicro h8dme
by Ward Vandewege 27 Apr '09

27 Apr '09

See attached. Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

3 3

[v2] r4222 - in trunk/coreboot-v2/src: mainboard/via/vt8454c northbridge/via/cx700
by svn＠coreboot.org 27 Apr '09

27 Apr '09

Author: oxygene Date: 2009-04-27 22:19:48 +0200 (Mon, 27 Apr 2009) New Revision: 4222 Modified: trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb trunk/coreboot-v2/src/mainboard/via/vt8454c/mainboard.c trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c Log: Add high table support to via vt8454c. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb 2009-04-27 20:19:06 UTC (rev 4221) +++ trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb 2009-04-27 20:19:48 UTC (rev 4222) @@ -25,6 +25,9 @@ uses HAVE_ACPI_TABLES uses HAVE_OPTION_TABLE uses USE_OPTION_TABLE +uses HAVE_LOW_TABLES +uses HAVE_HIGH_TABLES +uses HAVE_MAINBOARD_RESOURCES uses USE_FALLBACK_IMAGE uses HAVE_FALLBACK_BOOT @@ -139,7 +142,14 @@ ## default HAVE_OPTION_TABLE=1 +## +## Build code to fill in tables both in low and high memory +## +default HAVE_LOW_TABLES=1 +default HAVE_HIGH_TABLES=1 +default HAVE_MAINBOARD_RESOURCES=1 + ## ## Build code to setup a generic IOAPIC ## Modified: trunk/coreboot-v2/src/mainboard/via/vt8454c/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/vt8454c/mainboard.c 2009-04-27 20:19:06 UTC (rev 4221) +++ trunk/coreboot-v2/src/mainboard/via/vt8454c/mainboard.c 2009-04-27 20:19:48 UTC (rev 4222) @@ -20,8 +20,23 @@ */ #include <device/device.h> +#include <boot/tables.h> +#include <console/console.h> #include "chip.h" +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + printk_debug("Adding high table area\n"); + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif + return 0; +} + struct chip_operations mainboard_ops = { CHIP_NAME("VIA VT8454c Mainboard") }; Modified: trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c 2009-04-27 20:19:06 UTC (rev 4221) +++ trunk/coreboot-v2/src/northbridge/via/cx700/northbridge.c 2009-04-27 20:19:48 UTC (rev 4222) @@ -87,6 +87,12 @@ return tolm; } +#if HAVE_HIGH_TABLES==1 +/* maximum size of high tables in KB */ +#define HIGH_TABLES_SIZE 64 +extern uint64_t high_tables_base, high_tables_size; +#endif + static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -117,6 +123,12 @@ else tomk = (((rambits << 6) - (4 << reg) - 1) * 1024); +#if HAVE_HIGH_TABLES == 1 + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE* 1024; + printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); +#endif + /* Compute the top of Low memory */ tolmk = pci_tolm >> 10; if (tolmk >= tomk) {

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[v2] r4221 - trunk/coreboot-v2/src/mainboard/supermicro/h8dme
by svn＠coreboot.org 27 Apr '09

27 Apr '09

Author: ward Date: 2009-04-27 22:19:06 +0200 (Mon, 27 Apr 2009) New Revision: 4221 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dme/mainboard.c Log: Add high tables support for Supermicro H8DME. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-04-27 20:00:29 UTC (rev 4220) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-04-27 20:19:06 UTC (rev 4221) @@ -56,6 +56,10 @@ uses STACK_SIZE uses HEAP_SIZE uses USE_OPTION_TABLE +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES +uses HAVE_LOW_TABLES +uses CONFIG_MULTIBOOT uses LB_CKS_RANGE_START uses LB_CKS_RANGE_END uses LB_CKS_LOC @@ -125,6 +129,11 @@ #default ROM_SIZE=524288 default ROM_SIZE=0x100000 +default HAVE_MAINBOARD_RESOURCES = 1 +default HAVE_HIGH_TABLES = 1 +default HAVE_LOW_TABLES = 0 +default CONFIG_MULTIBOOT=0 + ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/mainboard.c =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/mainboard.c 2009-04-27 20:00:29 UTC (rev 4220) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/mainboard.c 2009-04-27 20:19:06 UTC (rev 4221) @@ -16,13 +16,23 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <device/device.h> #include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> +#include <boot/tables.h> #include "chip.h" +/* in arch/i386/boot/tables.c */ +extern uint64_t high_tables_base, high_tables_size; + +int add_mainboard_resources(struct lb_memory *mem) +{ +#if HAVE_HIGH_TABLES == 1 + lb_add_memory_range(mem, LB_MEM_TABLE, + high_tables_base, high_tables_size); +#endif + return 0; +} + struct chip_operations mainboard_ops = { CHIP_NAME("Supermicro H8DME Mainboard") };

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[PATCH] avoid mptable move with HAVE_LOW_TABLES=0 and HAVE_HIGH_TABLES=1
by Ward Vandewege 27 Apr '09

27 Apr '09

See attachment. Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

2 2

[v2] r4220 - trunk/coreboot-v2/src/arch/i386/boot
by svn＠coreboot.org 27 Apr '09

27 Apr '09

Author: ward Date: 2009-04-27 22:00:29 +0200 (Mon, 27 Apr 2009) New Revision: 4220 Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c Log: Special handling for MP table in low memory is only necessary if there are tables in low memory. This removes a hang when HAVE_LOW_TABLES=0 and HAVE_HIGH_TABLES=1. With this patch I can boot all the way to a payload. Tested on a Supermicro H8DME. Many thanks to Patrick Georgi for figuring this out. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-04-27 18:31:09 UTC (rev 4219) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-04-27 20:00:29 UTC (rev 4220) @@ -137,14 +137,6 @@ /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ #if HAVE_LOW_TABLES == 1 new_low_table_end = write_smp_table(low_table_end); // low_table_end is 0x10 at this point -#endif -#if HAVE_HIGH_TABLES == 1 - if (high_tables_base) { - high_table_end = write_smp_table(high_table_end); - high_table_end = (high_table_end+1023) & ~1023; - } -#endif - /* Don't write anything in the traditional x86 BIOS data segment, * for example the linux kernel smp need to use 0x467 to pass reset vector * or use 0x40e/0x413 for EBDA finding... @@ -171,6 +163,14 @@ smp_write_floating_table_physaddr(low_table_end - SMP_FLOATING_TABLE_LEN, mpc_start); memset((unsigned char *)low_table_end, '\0', mptable_size); } +#endif /* HAVE_LOW_TABLES */ + +#if HAVE_HIGH_TABLES == 1 + if (high_tables_base) { + high_table_end = write_smp_table(high_table_end); + high_table_end = (high_table_end+1023) & ~1023; + } +#endif #endif /* HAVE_MP_TABLE */ if (low_table_end < 0x500) {

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Re: [coreboot] flashrom and quanta mainboard
by Raphaël Maville 27 Apr '09

27 Apr '09

Well had not time to open the laptop; I have tried something: else: phnxdeco (phoenix bios decoder) on the update "bios.wph" from the vendor site (HP): Sorry, I am speaky below, because I do not know what is usefull! phnxdeco seem to be only to read bios, not to write it! This is the answers I have got: $ phnxdeco bios.wph -xs -=PhoenixDeco, version 0.33 (Linux)=- Filelength : 10D1A6 (1102246 bytes) Filename : bios.wph PhoenixBIOS hook found at : EF3AD System Information at : EF411 BootBlock : 8000 bytes BankSize : 1024 KB Version : DEVELAT6 Start : E93A5 Offset : F0000 BCP Modules : 34 BCPFCP : FAD65 FCP 1st module : 8F35 (F8F35) Released : 8(��l �O�H(�� at 11:21:38�Q 8k /* Copyrighted Information */ /* ----------------------- */ X.0 ROMEXEC0.rom ... O'k D.0 DISPLAY0.rom ... O'k G.0 DECOMPC0.rom ... O'k T.0 TEMPLAT0.rom ... O'k A.1 ACPI1.rom ... O'k A.2 ACPI2.rom ... O'k A.3 ACPI3.rom ... O'k A.4 ACPI4.rom ... O'k A.5 ACPI5.rom ... O'k A.6 ACPI6.rom ... O'k U.0 USER0.rom ... O'k L.5 LOGO5.rom ... O'k *.0 TCPA_*0.rom ... O'k B.0 BIOSCOD0.rom ... O'k X.1 ROMEXEC1.rom ... O'k S.0 STRINGS0.rom ... O'k R.0 OPROM0.rom ... O'k R.1 OPROM1.rom ... O'k R.2 OPROM2.rom ... O'k R.3 OPROM3.rom ... O'k E.0 SETUP0.rom ... O'k M.0 MISER0.rom ... O'k Y.0 User-De0.rom ... O'k L.1 LOGO1.rom ... O'k R.4 OPROM4.rom ... O'k Q.0 TCPA_Q0.rom ... O'k H.0 TCPA_H0.rom ... O'k A.0 ACPI0.rom ... O'k L.0 LOGO0.rom ... O'k L.2 LOGO2.rom ... O'k L.3 LOGO3.rom ... O'k L.4 LOGO4.rom ... O'k K.0 TCPA_K0.rom ... O'k B.1 BIOSCOD1.rom ... O'k B.2 BIOSCOD2.rom ... O'k B.3 BIOSCOD3.rom ... O'k B.4 BIOSCOD4.rom ... O'k B.5 BIOSCOD5.rom ... O'k B.6 BIOSCOD6.rom ... O'k C.0 UPDATE0.rom ... O'k Total Sections: 40 $ phnxdeco bios.wph -x -=PhoenixDeco, version 0.33 (Linux)=- Filelength : 10D1A6 (1102246 bytes) Filename : bios.wph PhoenixBIOS hook found at : EF3AD System Information at : EF411 BootBlock : 8000 bytes BankSize : 1024 KB Version : DEVELAT6 Start : E93A5 Offset : F0000 BCP Modules : 34 BCPFCP : FAD65 FCP 1st module : 8F35 (F8F35) Released : X8��|۷��O�h8��(9��O�@8��9�@8{�� at 11:21:38 /* Copyrighted Information */ /* ----------------------- */ C.00 :: Saving phoenix0.C0 ...Done B.06 :: Saving phoenix_.B6 ...Done B.05 :: Saving phoenix_.B5 ...Done B.04 :: Saving phoenix_.B4 ...Done B.03 :: Saving phoenix_.B3 ...Done B.02 :: Saving phoenix_.B2 ...Done B.01 :: Saving phoenix_.B1 ...Done K.00 :: Saving phoenix_.K0 ...Done L.04 :: Saving phoenix_.L4 ...Done L.03 :: Saving phoenix_.L3 ...Done L.02 :: Saving phoenix_.L2 ...Done L.00 :: Saving phoenix_.L0 ...Done A.00 :: Saving phoenix_.A0 ...Done H.00 :: Saving phoenix_.H0 ...Done Q.00 :: Saving phoenix_.Q0 ...Done R.04 :: Saving phoenix_.R4 ...Done L.01 :: Saving phoenix_.L1 ...Done Y.00 :: Saving phoenix_.Y0 ...Done M.00 :: Saving phoenix_.M0 ...Done E.00 :: Saving phoenix_.E0 ...Done R.03 :: Saving phoenix_.R3 ...Done R.02 :: Saving phoenix_.R2 ...Done R.01 :: Saving phoenix_.R1 ...Done R.00 :: Saving phoenix_.R0 ...Done S.00 :: Saving phoenix_.S0 ...Done X.01 :: Saving phoenix0.X1 ...Done B.00 :: Saving phoenix_.B0 ...Done *.00 :: Saving phoenix0.*0 ...Done L.05 :: Saving phoenix_.L5 ...Done U.00 :: Saving phoenix0.U0 ...Done A.06 :: Saving phoenix0.A6 ...Done A.05 :: Saving phoenix_.A5 ...Done A.04 :: Saving phoenix0.A4 ...Done A.03 :: Saving phoenix_.A3 ...Done A.02 :: Saving phoenix_.A2 ...Done A.01 :: Saving phoenix_.A1 ...Done T.00 :: Saving phoenix_.T0 ...Done G.00 :: Saving phoenix0.G0 ...Done D.00 :: Saving phoenix_.D0 ...Done X.00 :: Saving phoenix0.X0 ...Done B.00 :: Saving phoenix0.B0 ...Done .00 :: Saving phoenix0. ...Done Total Sections: 42 $ phnxdeco bios.wph -l -=PhoenixDeco, version 0.33 (Linux)=- Filelength : 10D1A6 (1102246 bytes) Filename : bios.wph PhoenixBIOS hook found at : EF3AD System Information at : EF411 BootBlock : 8000 bytes BankSize : 1024 KB Version : DEVELAT6 Start : E93A5 Offset : F0000 BCP Modules : 34 BCPFCP : FAD65 FCP 1st module : 8F35 (F8F35) Released : x��|ݷ��O��H��O�`��8�0� 8{�� at 11:21:38 /* Copyrighted Information */ /* ----------------------- */ +------------------------------------------------------------------------------+ | Class.Instance (Name) Packed ---> Expanded Compression Offset | +------------------------------------------------------------------------------+ C.00 ( UPDATE) 0F800 (63488) => 0F800 ( 63488) NONE (100%) 10005h B.06 ( BIOSCODE) 08B78 (35704) => 0CA40 ( 51776) LZINT ( 68%) 360F5h B.05 ( BIOSCODE) 0275D (10077) => 03AB0 ( 15024) LZINT ( 67%) 3EC88h B.04 ( BIOSCODE) 0170F (05903) => 025B0 ( 9648) LZINT ( 61%) 41400h B.03 ( BIOSCODE) 01D37 (07479) => 03810 ( 14352) LZINT ( 52%) 42B2Ah B.02 ( BIOSCODE) 07CCD (31949) => 0B230 ( 45616) LZINT ( 70%) 4487Ch B.01 ( BIOSCODE) 0AA24 (43556) => 0F370 ( 62320) LZINT ( 69%) 4C564h K.00 ( TCPA_K) 048F4 (18676) => 0842E ( 33838) LZINT ( 55%) 5B5B7h L.04 ( LOGO) 00848 (02120) => 09BA7 ( 39847) LZINT ( 5%) 5FEC6h L.03 ( LOGO) 01C6B (07275) => 116B9 ( 71353) LZINT ( 10%) 60729h L.02 ( LOGO) 007EE (02030) => 020A1 ( 8353) LZINT ( 24%) 623AFh L.00 ( LOGO) 02F23 (12067) => 0D4B7 ( 54455) LZINT ( 22%) 62BB8h A.00 ( ACPI) 03586 (13702) => 0759D ( 30109) LZINT ( 45%) 65AF6h H.00 ( TCPA_H) 0439A (17306) => 05F80 ( 24448) LZINT ( 70%) 69097h Q.00 ( TCPA_Q) 08200 (33280) => 10600 ( 67072) LZINT ( 49%) 6D44Ch R.04 ( OPROM) 0A983 (43395) => 0F000 ( 61440) LZINT ( 70%) 75667h L.01 ( LOGO) 009E7 (02535) => 07CB1 ( 31921) LZINT ( 7%) A04DAh Y.00 (User-Defined) 00980 (02432) => 01126 ( 4390) LZINT ( 55%) A0EDCh M.00 ( MISER) 0449E (17566) => 06BF0 ( 27632) LZINT ( 63%) A1877h E.00 ( SETUP) 03F3A (16186) => 09962 ( 39266) LZINT ( 41%) A5D30h R.03 ( OPROM) 0AEA7 (44711) => 0FE00 ( 65024) LZINT ( 68%) A9C85h R.02 ( OPROM) 093EA (37866) => 10000 ( 65536) LZINT ( 57%) B4B47h R.01 ( OPROM) 0A03C (41020) => 10200 ( 66048) LZINT ( 62%) BDF4Ch R.00 ( OPROM) 08784 (34692) => 0E600 ( 58880) LZINT ( 58%) C7FA3h S.00 ( STRINGS) 0F8A8 (63656) => 21132 (135474) LZINT ( 46%) D0742h X.01 ( ROMEXEC) 05060 (20576) => 05060 ( 20576) NONE (100%) E000Ah B.00 ( BIOSCODE) 00185 (00389) => 073C0 ( 29632) LZINT ( 1%) E5085h *.00 ( TCPA_*) 0004C (00076) => 0004C ( 076) NONE (100%) E5225h L.05 ( LOGO) 00581 (01409) => 02892 ( 10386) LZINT ( 13%) E528Ch U.00 ( USER) 0000E (00014) => 0000E ( 014) NONE (100%) E5828h A.06 ( ACPI) 00032 (00050) => 00032 ( 050) NONE (100%) E5851h A.05 ( ACPI) 00034 (00052) => 0003C ( 060) LZINT ( 86%) E589Eh A.04 ( ACPI) 00038 (00056) => 00038 ( 056) NONE (100%) E58EDh A.03 ( ACPI) 00051 (00081) => 00068 ( 104) LZINT ( 77%) E5940h A.02 ( ACPI) 0005F (00095) => 000F4 ( 244) LZINT ( 38%) E59ACh A.01 ( ACPI) 0005B (00091) => 00074 ( 116) LZINT ( 78%) E5A26h T.00 ( TEMPLATE) 0293B (10555) => 05D10 ( 23824) LZINT ( 44%) E5A9Ch G.00 ( DECOMPCODE) 00430 (01072) => 00430 ( 1072) NONE (100%) E83F2h D.00 ( DISPLAY) 00B52 (02898) => 01020 ( 4128) LZINT ( 70%) E883Dh X.00 ( ROMEXEC) 06C30 (27696) => 06C30 ( 27696) NONE (100%) E93AAh B.00 ( BIOSCODE) 01D40 (07488) => 01D40 ( 7488) NONE (100%) F8F3Ah .00 (User-Defined) 00000 (00000) => 00A30 ( 2608) NONE ( 0%) 100005h Total Sections: 42

2 4

[v2] r4219 - in trunk/coreboot-v2: src/mainboard/via/vt8454c targets/via/vt8454c
by svn＠coreboot.org 27 Apr '09

27 Apr '09

Author: oxygene Date: 2009-04-27 20:31:09 +0200 (Mon, 27 Apr 2009) New Revision: 4219 Modified: trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb trunk/coreboot-v2/targets/via/vt8454c/Config-abuild.lb Log: Migrate via/vt8454c to CBFS. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb 2009-04-27 18:26:43 UTC (rev 4218) +++ trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb 2009-04-27 18:31:09 UTC (rev 4219) @@ -240,7 +240,7 @@ # # CBFS # -default CONFIG_CBFS=0 +default CONFIG_CBFS=1 end Modified: trunk/coreboot-v2/targets/via/vt8454c/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/via/vt8454c/Config-abuild.lb 2009-04-27 18:26:43 UTC (rev 4218) +++ trunk/coreboot-v2/targets/via/vt8454c/Config-abuild.lb 2009-04-27 18:31:09 UTC (rev 4219) @@ -28,10 +28,11 @@ option CROSS_COMPILE="CROSS_PREFIX" option HOSTCC="CROSS_HOSTCC" -option ROM_SIZE=(512-64)*1024 -option FALLBACK_SIZE=(512-64)*1024 +option ROM_SIZE=512*1024 +option FALLBACK_SIZE=512*1024 __COMPRESSION__ +__LOGLEVEL__ romimage "fallback" option USE_FALLBACK_IMAGE=1 @@ -41,4 +42,4 @@ end buildrom ./coreboot.rom ROM_SIZE "fallback" - +#pci_rom $(TOP)/via-cx700.rom vendor_id=0x1106 device_id=0x3157

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[v2] r4218 - trunk/coreboot-v2/src/cpu/via/car
by svn＠coreboot.org 27 Apr '09

27 Apr '09

Author: oxygene Date: 2009-04-27 20:26:43 +0200 (Mon, 27 Apr 2009) New Revision: 4218 Modified: trunk/coreboot-v2/src/cpu/via/car/cache_as_ram_post.c Log: Create a valid stack pointer after leaving CAR, so function calls don't reset the machine in the small window between CAR and coreboot_ram. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/via/car/cache_as_ram_post.c =================================================================== --- trunk/coreboot-v2/src/cpu/via/car/cache_as_ram_post.c 2009-04-27 16:08:26 UTC (rev 4217) +++ trunk/coreboot-v2/src/cpu/via/car/cache_as_ram_post.c 2009-04-27 18:26:43 UTC (rev 4218) @@ -99,8 +99,11 @@ "movl %eax, %cr0\n\t" "invd\n\t" - /* - FIXME: I hope we don't need to change esp and ebp value here, so we can restore value from mmx sse back - But the problem is the range is some io related, So don't go back - */ + /* FIXME: These values might have to change for suspend-to-ram. + the 0x00400000 was chosen as this is a place in memory that + should exist in all contemporary configurations (ie. large + enough RAM), but doesn't collide with anything coreboot does. + Other than that, it's arbitrary. */ + "movl $0x00400000,%esp\n\t" + "movl %esp,%ebp\n\t" );

1 0

[v2] r4217 - trunk/coreboot-v2/src/cpu/amd/car
by svn＠coreboot.org 27 Apr '09

27 Apr '09

Author: myles Date: 2009-04-27 18:08:26 +0200 (Mon, 27 Apr 2009) New Revision: 4217 Modified: trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c Log: Revert 4099 patch that causes an ECC error. Memory has to be written while ECC error checking is disabled. The purpose of the patch was to preserve memory used by ACPI resume code. One possible solution is to read that memory and write it back while ECC error-checking is disabled. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c 2009-04-26 19:50:53 UTC (rev 4216) +++ trunk/coreboot-v2/src/cpu/amd/car/clear_init_ram.c 2009-04-27 16:08:26 UTC (rev 4217) @@ -6,7 +6,8 @@ // gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram // will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already // so noline clear_init_ram - clear_memory( _RAMBASE, (CONFIG_LB_MEM_TOPK << 10) - _RAMBASE - DCACHE_RAM_SIZE); + clear_memory(0, ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE)); + } /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/

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Rev 4099
by Myles Watson 27 Apr '09

27 Apr '09

It turns out that Rev 4099 breaks the hp dl145_g3. It boots into Linux which panics and complains "This is not a software error". Sorry I don't have the exact error message any more. Samuel said he thinks it has something to do with one processor overwriting another's space. Help? Thanks, Myles

10 27

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coreboot April 2009