coreboot March 2009

coreboot@coreboot.org

64 participants
316 discussions

seabios change to boot from last boot device for gPXE or other option rom booting
by Joe Julian 12 Mar '09

12 Mar '09

The hardcoded boot order method when using seabios with coreboot makes booting from option roms difficult if the number of hard drives installed is not a fixed number. I used this patch to allow choosing the last boot device by setting the nibble to 0xf. This allows me to boot from the gPXE option rom. diff --git a/src/boot.c b/src/boot.c index 6b4e985..44c1665 100644 --- a/src/boot.c +++ b/src/boot.c @@ -51,7 +51,8 @@ boot_setup() SET_EBDA(boot_sequence, 0xffff); if (CONFIG_COREBOOT) { // XXX - hardcode defaults for coreboot. - IPL.bootorder = 0x00000231; + // use 0xf to choose the last bev device + IPL.bootorder = 0x0000231f; IPL.checkfloppysig = 1; } else { // On emulators, get boot order from nvram. @@ -372,6 +373,10 @@ do_boot(u16 seq_nr) u32 bootdev = IPL.bootorder; bootdev >>= 4 * seq_nr; bootdev &= 0xf; + if(bootdev == 0x0f) { + dprintf(1, "IPL.bevcount = %d)\n", IPL.bevcount); + bootdev = IPL.bevcount; + } if (bootdev == 0) { printf("No bootable device.\n");

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Re: [coreboot] the seabios reboot in the post process
by Kevin O'Connor 12 Mar '09

12 Mar '09

On Thu, Mar 12, 2009 at 06:43:24AM +0000, wei yang wrote: > > On Thu, Mar 12, 2009 at 03:16:17AM +0000, wei yang wrote: > > > > I'll need to see the log. It looks like SeaBIOS didn't find your > > > > cdrom. > > > The sea bios boot log as following, can you have a look? > > > > I need to see the full log. > > All log is here, thanks Kevin. Thanks. You don't have the latest version of SeaBIOS, and a bunch of changes recently went into the ata code. Please pull the latest version from git and retry. -Kevin

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[PATCH] v2 ACPI updates for i945, ICH7 and kontron 986lcd-m
by Stefan Reinauer 12 Mar '09

12 Mar '09

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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r3998 - trunk/coreboot-v2/src/arch/i386/boot
by svn＠coreboot.org 12 Mar '09

12 Mar '09

Author: stepan Date: 2009-03-12 18:42:20 +0100 (Thu, 12 Mar 2009) New Revision: 3998 Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c Log: Fix HIGH_TABLES introduced error when compiling without MP table Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-03-11 16:20:39 UTC (rev 3997) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-03-12 17:42:20 UTC (rev 3998) @@ -122,6 +122,8 @@ /* copy the smp block to address 0 */ post_code(0x96); +#if HAVE_MP_TABLE == 1 + /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ #if HAVE_LOW_TABLES == 1 new_low_table_end = write_smp_table(low_table_end); // low_table_end is 0x10 at this point @@ -133,7 +135,6 @@ } #endif -#if HAVE_MP_TABLE == 1 /* Don't write anything in the traditional x86 BIOS data segment, * for example the linux kernel smp need to use 0x467 to pass reset vector * or use 0x40e/0x413 for EBDA finding... @@ -160,7 +161,7 @@ smp_write_floating_table_physaddr(low_table_end - SMP_FLOATING_TABLE_LEN, mpc_start); memset((unsigned char *)low_table_end, '\0', mptable_size); } -#endif +#endif /* HAVE_MP_TABLE */ if (low_table_end < 0x500) { low_table_end = 0x500;

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: ASUS P2-M2A690G Barebone
by Cirdec AREVIR 12 Mar '09

12 Mar '09

Hi, I'm trying to try Coreboot on this barebone that seems to be like the M2A-VM motherboard but flashrom can't do nothing with the flash chip : Calibrating delay loop... OK. No coreboot table found. Found chipset "ATI(AMD) SB600", enabling flash write... OK. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename The flash chip is an EON-EN25F80, after visual checking ;-) So, I bring in attachment some useful data, the motherboard is recognized as M2R68L, a standard AMD690G motherboard Any idea ? Thx. Regards Cedric.

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r89 - trunk/filo
by svn＠coreboot.org 12 Mar '09

12 Mar '09

Author: oxygene Date: 2009-03-12 18:02:09 +0100 (Thu, 12 Mar 2009) New Revision: 89 Modified: trunk/filo/Config.in Log: Allow DEBUG_IDE for IDE_NEW_DISK, too Modified: trunk/filo/Config.in =================================================================== --- trunk/filo/Config.in 2009-03-12 17:01:54 UTC (rev 88) +++ trunk/filo/Config.in 2009-03-12 17:02:09 UTC (rev 89) @@ -315,7 +315,7 @@ config DEBUG_IDE bool "DEBUG_IDE" - depends on IDE_DISK + depends on IDE_DISK||IDE_NEW_DISK default n config DEBUG_USB

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r88 - trunk/filo/drivers
by svn＠coreboot.org 12 Mar '09

12 Mar '09

Author: oxygene Date: 2009-03-12 18:01:54 +0100 (Thu, 12 Mar 2009) New Revision: 88 Modified: trunk/filo/drivers/ide_new.c Log: Handle 2048 byte sectors somewhat. It assumes that the filesystem also uses 2048 byte sectors and recalculates sector numbers based on 512b sectors (ie. sector number * 4). Prints a warning if assumption is wrong Modified: trunk/filo/drivers/ide_new.c =================================================================== --- trunk/filo/drivers/ide_new.c 2009-03-12 17:00:30 UTC (rev 87) +++ trunk/filo/drivers/ide_new.c 2009-03-12 17:01:54 UTC (rev 88) @@ -681,6 +681,14 @@ if (ob_ide_atapi_drive_ready(drive)) return 1; + if (drive->bs == 2048) { + if ((block & 3 != 0) || (sectors & 3 != 0)) { + printf("ob_ide_read_atapi: unaligned atapi access: %x blocks, starting from %x\n", sectors, block); + } + block >>= 2; + sectors >>= 2; + } + memset(cmd, 0, sizeof(*cmd)); /*

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r87 - trunk/filo/drivers
by svn＠coreboot.org 12 Mar '09

12 Mar '09

Author: oxygene Date: 2009-03-12 18:00:30 +0100 (Thu, 12 Mar 2009) New Revision: 87 Modified: trunk/filo/drivers/ide_new.c trunk/filo/drivers/ide_new.h Log: Use PCI BARs for I/O ports in new IDE driver. Port from old IDE driver. Modified: trunk/filo/drivers/ide_new.c =================================================================== --- trunk/filo/drivers/ide_new.c 2009-03-11 03:07:08 UTC (rev 86) +++ trunk/filo/drivers/ide_new.c 2009-03-12 17:00:30 UTC (rev 87) @@ -29,6 +29,10 @@ #include "ide_new.h" #include "hdreg.h" +#ifdef CONFIG_SUPPORT_PCI +#include <pci.h> +#endif + #if 0 #define dprintf printf #else @@ -44,6 +48,7 @@ #define IDE_NUM_CHANNELS CONFIG_IDE_NUM_CHANNELS #endif #define IDE_MAX_CHANNELS 4 +#define IDE_MAX_DRIVES (IDE_MAX_CHANNELS * 2) static struct ide_channel ob_ide_channels[IDE_MAX_CHANNELS]; @@ -1150,21 +1155,198 @@ return(drive->bs); } +#ifdef CONFIG_SUPPORT_PCI +static int pci_find_ata_device_on_bus(int bus, pcidev_t * dev, int *index, int sata, int pata) +{ + int slot, func; + u32 val; + unsigned char hdr; + u32 class; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + pcidev_t currdev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(currdev, REG_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + class = pci_read_config16(currdev, 0x0a); + debug("%02x:%02x.%02x [%04x:%04x] class %04x\n", + bus, slot, func, val & 0xffff, val >> 16, class); + + if ((sata && class == 0x180) || (pata && class == 0x101)) { + if (*index == 0) { + *dev = currdev; + return 1; + } + (*index)--; + } + + hdr = pci_read_config8(currdev, REG_HEADER_TYPE) & 0x7f; + + if (hdr == HEADER_TYPE_BRIDGE || hdr == HEADER_TYPE_CARDBUS) { + unsigned int new_bus; + new_bus = (pci_read_config32(currdev, REG_PRIMARY_BUS) >> 8) & 0xff; + if (new_bus == 0) { + debug("Misconfigured bridge at %02x:%02x.%02x skipped.\n", + bus, slot, func); + continue; + } + if (pci_find_ata_device_on_bus(new_bus, dev, index, sata, pata)) + return 1; + } + } + } + + return 0; +} + +int pci_find_ata_device(pcidev_t *dev, int *index, int sata, int pata) +{ + debug(" Scanning for:%s%s\n", sata?" SATA":"", pata?" PATA":""); + return pci_find_ata_device_on_bus(0, dev, index, sata, pata); +} +#endif + + +static void fixupregs(struct ide_channel *chan) +{ + int i; + for (i = 1; i < 8; i++) + chan->io_regs[i] = chan->io_regs[0] + i; + chan->io_regs[9] = chan->io_regs[8] + 1; +} + +static int find_ide_controller_compat(struct ide_channel *chan, int index) +{ +#ifdef CONFIG_SUPPORT_PCI + int skip, i, pci_index = index / 2; + pcidev_t dev; +#else + if (index >= IDE_MAX_CHANNELS) + return -1; +#endif +#ifdef CONFIG_PCMCIA_CF + if (index == 2) { + chan->io_regs[0] = 0x1e0; + chan->io_regs[8] = 0x1ec; + fixupregs(chan); + return 0; + } +#endif +#ifdef CONFIG_SUPPORT_PCI + /* skip any SATA and PATA PCI controllers in native mode */ + for (skip = i = 0; i < pci_index && index; i++) { + int devidx = i; + /* look for i:th ata (IDE/other storage really) device */ + if(!pci_find_ata_device(&dev, &devidx, 1, 1)) + break; + /* only IDE can be in compat mode so skip all others */ + if (pci_read_config16(dev, 0xa) != 0x0101) { + /* other storage (SATA) always has two channels */ + skip += 2; + continue; + } + /* primary in native mode? then skip it. */ + if (1 == (pci_read_config8(dev, 0x09) & 1)) + skip++; + /* secondary in native mode? then skip it. */ + if (index && 4 == (pci_read_config8(dev, 0x09) & 4)) + skip++; + } + index = skip <= index ? index - skip : 0; + debug("skipping %d native PCI controllers, new index=%d\n", skip, index); + if (index >= IDE_MAX_CHANNELS) + return -1; +#endif + chan->io_regs[0] = io_ports[index]; + chan->io_regs[8] = ctl_ports[index]; + fixupregs(chan); + return 0; +} + +#ifdef CONFIG_SUPPORT_PCI +static int find_ide_controller(struct ide_channel *chan, int chan_index) +{ + int pci_index; + pcidev_t dev; + unsigned int mask; + u8 prog_if; + u16 vendor, device, devclass; + + /* A PCI IDE controller has two channels (pri, sec) */ + pci_index = chan_index >> 1; + + /* Find a IDE storage class device */ + + if (!pci_find_ata_device(&dev, &pci_index, 1, 0)) { // S-ATA first + pci_index = chan_index >> 1; + if (!pci_find_ata_device(&dev, &pci_index, 0, 1)) { // P-ATA second + debug("PCI IDE #%d not found\n", chan_index >> 1); + return -1; + } + } + + vendor = pci_read_config16(dev, 0); + device = pci_read_config16(dev, 2); + prog_if = pci_read_config8(dev, 9); + devclass = pci_read_config16(dev, 0x0a); + + debug("found PCI IDE controller %04x:%04x prog_if=%#x\n", + vendor, device, prog_if); + + /* See how this controller is configured */ + mask = (chan_index & 1) ? 4 : 1; + debug("%s channel: ", (chan_index & 1) ? "secondary" : "primary"); + if ((prog_if & mask) || (devclass != 0x0101)) { + debug("native PCI mode\n"); + if ((chan_index & 1) == 0) { + /* Primary channel */ + chan->io_regs[0] = pci_read_resource(dev, 0); // io ports + chan->io_regs[8] = pci_read_resource(dev, 1); // ctrl ports + } else { + /* Secondary channel */ + chan->io_regs[0] = pci_read_resource(dev, 2); // io ports + chan->io_regs[8] = pci_read_resource(dev, 3); // ctrl ports + } + chan->io_regs[0] &= ~3; + chan->io_regs[8] &= ~3; + fixupregs(chan); + } else { + debug("compatibility mode\n"); + if (find_ide_controller_compat(chan, chan_index) != 0) + return -1; + } + return 0; +} +#else /* !CONFIG_SUPPORT_PCI */ +# define find_ide_controller find_ide_controller_compat +#endif //int ob_ide_init(int (*func)(struct ide_drive*)) -int ob_ide_init(void) +int ob_ide_init(int drive) { - int i, j; + int j; - for (i = 0; i < IDE_NUM_CHANNELS; i++) { - struct ide_channel *chan = &ob_ide_channels[i]; + struct ide_channel *chan; + int chan_index; - chan->mmio = 0; + if (drive >= IDE_MAX_DRIVES) { + printf("Unsupported drive number\n"); + return -1; + } - for (j = 0; j < 8; j++) - chan->io_regs[j] = io_ports[i] + j; + /* A controller has two drives (master, slave) */ + chan_index = drive >> 1; - chan->io_regs[8] = ctl_ports[i]; - chan->io_regs[9] = ctl_ports[i] + 1; + chan = &ob_ide_channels[chan_index]; + if (chan->present == 0) { + if (find_ide_controller(chan, chan_index) != 0) { + printf("IDE channel %d not found\n", chan_index); + return -1; + } chan->obide_inb = ob_ide_inb; chan->obide_insw = ob_ide_insw; @@ -1172,6 +1354,7 @@ chan->obide_outsw = ob_ide_outsw; chan->selected = -1; + chan->mmio = 0; /* * assume it's there, if not io port dead check will clear @@ -1185,17 +1368,17 @@ /* init with a decent value */ chan->drives[j].bs = 512; - chan->drives[j].nr = i * 2 + j; + chan->drives[j].nr = chan_index * 2 + j; } ob_ide_probe(chan); if (!chan->present) - continue; + return -1; ob_ide_identify_drives(chan); - printf("ata-%d: [io ports 0x%x-0x%x,0x%x]\n", i, + printf("ata-%d: [io ports 0x%x-0x%x,0x%x]\n", chan_index, chan->io_regs[0], chan->io_regs[0] + 7, chan->io_regs[8]); @@ -1232,10 +1415,7 @@ int ide_probe(int drive) { struct ide_drive *curr_drive = & ob_ide_channels[drive / 2].drives[drive % 2]; - if (!inited) { - ob_ide_init(); - inited = 1; - } + ob_ide_init(drive); if (!curr_drive->present) return -1; @@ -1249,10 +1429,7 @@ struct ide_drive *curr_drive = & ob_ide_channels[drive / 2].drives[drive % 2]; char *media = "UNKNOWN"; - if (!inited) { - ob_ide_init(); - inited = 1; - } + ob_ide_init(drive); if (!curr_drive->present) { return -1; @@ -1300,3 +1477,4 @@ } return 0; } + Modified: trunk/filo/drivers/ide_new.h =================================================================== --- trunk/filo/drivers/ide_new.h 2009-03-11 03:07:08 UTC (rev 86) +++ trunk/filo/drivers/ide_new.h 2009-03-12 17:00:30 UTC (rev 87) @@ -218,7 +218,7 @@ static int ob_ide_atapi_request_sense(struct ide_drive *drive); //int ob_ide_init(int (*func)(struct ide_drive*)); -int ob_ide_init(void); +int ob_ide_init(int drive); /* FILO compat */

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VGA ROM hang, May be a bug of the coreboot V2
by wei yang 12 Mar '09

12 Mar '09

Hi, I currently use the coreboot v2 -3290 version.(very new). When I boot the corboot V2 on the intel/Truxon board, the serial port without VGA is ok. Then, I tried to add the VGA add-on card, the coreboot hung in the VGA ROM. After hard debug, I found this VGA OPTION ROM will check a flag in the address 0xffffe, in coreboot the value is 0x0. So the OptionROM go to the wrong path and do the infinite loop. Actually, this addr in the legacy bios will put the System Mode ID (0xFC) in it, I manually wrote 0xFC to the address 0xfffffe. The VGA ROM was ok and the screen was trun on. I guess it is a thing the coreboot should do, otherwise some VGA OPTION ROM can't work correctly. _________________________________________________________________ Drag n’ drop—Get easy photo sharing with Windows Live™ Photos. http://www.microsoft.com/windows/windowslive/products/photos.aspx

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about the CACHE settting issue in the coreboot
by wei yang 12 Mar '09

12 Mar '09

This is also happend on me, I also wandering it is may be a test for my debug ability. I guess the cache control in the currently coreboot is not so perfect. I got such issue, when I boot coreboot through filo with VGA card, then system hung at very beginning of the filo. Filo was even not print out any thing. I debug and debug( by added many printk and infinite loop), then found the system hung in the "LGDT" operation just after the coreboot load the payload code section in the memory. Actually, this "LGDT" operation were always ok befoere payload code copy operation. So, I think this phenomenon may be due to the cache. Since we dynamiclly genearte the code, we should fluch the code to force CPU reload.(if I am wrong, pls correct me) Then I tried to disable global cache just after MTRRR setting, the system successfully boot the filo prompt. I have checked the elfboot.c /boot.c in the coreboot v2, I don't found the cache syn operation in the code. Does any one has the comment? Thanks _________________________________________________________________ Invite your mail contacts to join your friends list with Windows Live Spaces. It's easy! http://spaces.live.com/spacesapi.aspx?wx_action=create&wx_url=/friends.aspx…

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coreboot March 2009