coreboot September 2008

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415 discussions

r3559 - in trunk/payloads/libpayload: include libc
by svn＠coreboot.org 02 Sep '08

02 Sep '08

Author: oxygene Date: 2008-09-02 17:49:32 +0200 (Tue, 02 Sep 2008) New Revision: 3559 Modified: trunk/payloads/libpayload/include/libpayload.h trunk/payloads/libpayload/libc/malloc.c Log: Add memalign(align, size). Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/include/libpayload.h =================================================================== --- trunk/payloads/libpayload/include/libpayload.h 2008-09-02 09:35:43 UTC (rev 3558) +++ trunk/payloads/libpayload/include/libpayload.h 2008-09-02 15:49:32 UTC (rev 3559) @@ -221,6 +221,7 @@ void *malloc(size_t size); void *calloc(size_t nmemb, size_t size); void *realloc(void *ptr, size_t size); +void *memalign(size_t align, size_t size); /** @} */ /** Modified: trunk/payloads/libpayload/libc/malloc.c =================================================================== --- trunk/payloads/libpayload/libc/malloc.c 2008-09-02 09:35:43 UTC (rev 3558) +++ trunk/payloads/libpayload/libc/malloc.c 2008-09-02 15:49:32 UTC (rev 3559) @@ -72,7 +72,7 @@ *((hdrtype_t *) hstart) = FREE_BLOCK(size); } -static void *alloc(int len) +static void *alloc(int len, int align) { hdrtype_t header; void *ptr = hstart; @@ -92,13 +92,20 @@ header = *((hdrtype_t *) ptr); int size = SIZE(header); - if (!HAS_MAGIC(header) || size == 0) { + if (!HAS_MAGIC(header)) { printf("memory allocator panic.\n"); halt(); } if (header & FLAG_FREE) { - if (len <= size) { + int realaddr = (int)(ptr + HDRSIZE); + int overhead = ((realaddr+align-1) & ~(align-1)) - realaddr; + if (len + overhead <= size) { + if (overhead != 0) { + *((hdrtype_t *) ptr) = FREE_BLOCK(overhead - HDRSIZE); + ptr += overhead; + size -= overhead; + } void *nptr = ptr + (HDRSIZE + len); int nsize = size - (HDRSIZE + len); @@ -186,13 +193,13 @@ void *malloc(size_t size) { - return alloc(size); + return alloc(size, 1); } void *calloc(size_t nmemb, size_t size) { size_t total = nmemb * size; - void *ptr = alloc(total); + void *ptr = alloc(total, 1); if (ptr) memset(ptr, 0, total); @@ -206,7 +213,7 @@ unsigned int osize; if (ptr == NULL) - return alloc(size); + return alloc(size, 1); pptr = ptr - HDRSIZE; @@ -222,7 +229,7 @@ * reallocated the new space. */ free(ptr); - ret = alloc(size); + ret = alloc(size, 1); /* * if ret == NULL, then doh - failure. @@ -237,11 +244,23 @@ return ret; } +/** + * Allocate an aligned chunk of memory + * + * @param align alignment, must be power of two + * @param size size of chunk in bytes + * @return Return the address of such a memory region or NULL + */ +void *memalign(size_t align, size_t size) +{ + return alloc(size, align); +} + /* This is for debugging purposes. */ #ifdef TEST void print_malloc_map(void) { - void *ptr = hstart; +void *ptr = hstart; while (ptr < hend) { hdrtype_t hdr = *((hdrtype_t *) ptr);

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k8 progress: now in stage2.
by ron minnich 02 Sep '08

02 Sep '08

we're in to stage 2. commit message: With this change, we get all the way to stage 2 and this output, at which point we hang: Show all devs... root(Root Device): enabled 1 have_resources 0 initialized 0 cpus: Unknown device path type: 0 cpus(): enabled 1 have_resources 0 initialized 0 apic_0(APIC: 00): enabled 1 have_resources 0 initialized 0 pci_1_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0 pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 initialized 0 pci_4_0(PCI: 00:04.0): enabled 1 have_resources 0 initialized 0 pci_5_0(PCI: 00:05.0): enabled 1 have_resources 0 initialized 0 pci_18_0(PCI: 00:18.0): enabled 1 have_resources 0 initialized 0 ioport_2e(IOPORT: 2e): enabled 1 have_resources 0 initialized 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0 Phase 6: Initializing devices... Phase 6: Root Device init. Phase 6: PCI: 00:04.0 init. The hang is in pci_domain_read_resources. pc is 5f92. That PC is not compatible with the fact that we hit phase 6; something else is going on. The dts is quite incomplete and that is part of the problem. Doubtless there are other problems :-) But training is indeed working in simnow, and memory is working, and we can return from disable_car as on the geode. For those of you who want to help but were not sure what to do, well, we've got LOTS of places that need help now :-) ron

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r855 - coreboot-v3/arch/x86/amd/k8
by svn＠coreboot.org 02 Sep '08

02 Sep '08

Author: rminnich Date: 2008-09-02 17:25:06 +0200 (Tue, 02 Sep 2008) New Revision: 855 Modified: coreboot-v3/arch/x86/amd/k8/stage1.c Log: With this change, we get all the way to stage 2 and this output, at which point we hang: Show all devs... root(Root Device): enabled 1 have_resources 0 initialized 0 cpus: Unknown device path type: 0 cpus(): enabled 1 have_resources 0 initialized 0 apic_0(APIC: 00): enabled 1 have_resources 0 initialized 0 pci_1_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0 pci_0_0(PCI: 00:00.0): enabled 1 have_resources 0 initialized 0 pci_4_0(PCI: 00:04.0): enabled 1 have_resources 0 initialized 0 pci_5_0(PCI: 00:05.0): enabled 1 have_resources 0 initialized 0 pci_18_0(PCI: 00:18.0): enabled 1 have_resources 0 initialized 0 ioport_2e(IOPORT: 2e): enabled 1 have_resources 0 initialized 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0 Phase 6: Initializing devices... Phase 6: Root Device init. Phase 6: PCI: 00:04.0 init. The dts is quite incomplete and that is part of the problem. Doubtless there are other problems :-) But training is indeed working in simnow, and memory is working, and we can return from disable_car as on the geode. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/amd/k8/stage1.c =================================================================== --- coreboot-v3/arch/x86/amd/k8/stage1.c 2008-09-01 02:44:08 UTC (rev 854) +++ coreboot-v3/arch/x86/amd/k8/stage1.c 2008-09-02 15:25:06 UTC (rev 855) @@ -38,8 +38,16 @@ * the data back over itself, and the wbinvd should then * flush to memory. Let's see. */ + /* nope. __asm__ __volatile__("cld; rep movsl" ::"D" (CONFIG_CARBASE), "S" (CONFIG_CARBASE), "c" (CONFIG_CARSIZE/4): "memory"); + */ + /* call the inlined function */ + disable_cache_as_ram(); + + /* copy it down, wbinvd, copy it back? */ + __asm__ __volatile__("cld; rep movsl" ::"D" (0x88000), "S" (CONFIG_CARBASE), "c" (CONFIG_CARSIZE/4): "memory"); __asm__ __volatile__ ("wbinvd\n"); + __asm__ __volatile__("cld; rep movsl" ::"D" (CONFIG_CARBASE), "S" (0x88000), "c" (CONFIG_CARSIZE/4): "memory"); banner(BIOS_DEBUG, "Disable_car: done wbinvd"); banner(BIOS_DEBUG, "disable_car: done"); }

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[PATCH] libpayload keyboard driver fix.
by Stefan Reinauer 02 Sep '08

02 Sep '08

See Patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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r3558 - trunk/payloads/libpayload/drivers
by svn＠coreboot.org 02 Sep '08

02 Sep '08

Author: stepan Date: 2008-09-02 11:35:43 +0200 (Tue, 02 Sep 2008) New Revision: 3558 Modified: trunk/payloads/libpayload/drivers/keyboard.c Log: The keyboard driver mixed up the key press/release events for the special keys. Patrick Georgi explained: The |0x80 codes are "break codes", that means, codes that are emitted when the key transitions from pressed to non-pressed, so the modifier was always in the wrong state, as soon as you pressed shift for the first time. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/payloads/libpayload/drivers/keyboard.c =================================================================== --- trunk/payloads/libpayload/drivers/keyboard.c 2008-09-02 00:26:11 UTC (rev 3557) +++ trunk/payloads/libpayload/drivers/keyboard.c 2008-09-02 09:35:43 UTC (rev 3558) @@ -79,7 +79,7 @@ int keyboard_getchar(void) { - static int modifier; + static int modifier = 0; unsigned char ch; int shift; int ret = 0; @@ -91,17 +91,17 @@ switch (ch) { case 0x36: case 0x2a: - modifier &= ~MOD_SHIFT; + modifier |= MOD_SHIFT; break; case 0x80 | 0x36: case 0x80 | 0x2a: - modifier |= MOD_SHIFT; + modifier &= ~MOD_SHIFT; break; case 0x1d: - modifier &= ~MOD_CTRL; + modifier |= MOD_CTRL; break; case 0x80 | 0x1d: - modifier |= MOD_CTRL; + modifier &= ~MOD_CTRL; break; case 0x3a: if (modifier & MOD_CAPSLOCK)

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r3557 - trunk/util/flashrom
by svn＠coreboot.org 02 Sep '08

02 Sep '08

Author: stuge Date: 2008-09-02 02:26:11 +0200 (Tue, 02 Sep 2008) New Revision: 3557 Modified: trunk/util/flashrom/flashchips.c Log: flashrom: SST49LF016C TEST_OK_ PROBE READ ERASE WRITE Per test report from Bari Ari. Thanks! Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-09-01 01:48:07 UTC (rev 3556) +++ trunk/util/flashrom/flashchips.c 2008-09-02 00:26:11 UTC (rev 3557) @@ -88,7 +88,7 @@ {"SST", "SST49LF004C", SST_ID, SST_49LF004C, 512, 4 * 1024, TEST_UNTESTED, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, {"SST", "SST49LF008A", SST_ID, SST_49LF008A, 1024, 64 * 1024, TEST_OK_PREW, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, {"SST", "SST49LF008C", SST_ID, SST_49LF008C, 1024, 4 * 1024, TEST_UNTESTED, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, - {"SST", "SST49LF016C", SST_ID, SST_49LF016C, 2048, 4 * 1024, TEST_UNTESTED, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, + {"SST", "SST49LF016C", SST_ID, SST_49LF016C, 2048, 4 * 1024, TEST_OK_PREW, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, {"SST", "SST49LF020A", SST_ID, SST_49LF020A, 256, 16 * 1024, TEST_UNTESTED, probe_jedec, erase_49lf040, write_49lf040}, {"SST", "SST49LF040", SST_ID, SST_49LF040, 512, 4096, TEST_OK_PREW, probe_jedec, erase_49lf040, write_49lf040}, {"SST", "SST49LF040B", SST_ID, SST_49LF040B, 512, 64 * 1024, TEST_OK_PREW, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub},

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K8 RAMinit problematic code
by Carl-Daniel Hailfinger 02 Sep '08

02 Sep '08

Hi, this patch is not to be applied, but an annotation from my tree. Index: northbridge/amd/k8/dqs.c =================================================================== --- northbridge/amd/k8/dqs.c (Revision 853) +++ northbridge/amd/k8/dqs.c (Arbeitskopie) @@ -2001,6 +2001,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if(coreid) return; // only do it on core0 +#error This is broken beyond repair. We need to use the generic global variable infrastructure, especially if we relocate the global variables without telling anybody. struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); wait_till_sysinfo_in_ram(); // use pci to get it @@ -2012,6 +2013,7 @@ sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid]; memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller)); #else +#error Broken here as well. memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE); #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's Even if the stuff above is fixed, we absolutely have to finish the concept of accessing global variables by adding locking and/or spelling out the access rules, especially for the CAR stage. Oh, and can we please mark struct sys_info as const where possible and also not pass it around as parameter. Especially if we perform stack relocation, this can lead to really nasty problems. Thanks. Regards, Carl-Daniel -- http://www.hailfinger.org/

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AVATT Got signal !!!
by Cristi Magherusan 02 Sep '08

02 Sep '08

Hello, I have great news! I just found out that AVATT is working!!! The latest kvm version has a CFLAG --disable-nptl. I disabled it yesterday in http://repo.or.cz/w/kvm-coreboot.git?a=commitdiff;h=910b66268ed5a7a72a57a1b… and recompiled kvm, but I haven't tested it at that time to see whether it works or not. Today I did it, and it seems that OpenBSD's livecd is starting, but unfortunatelly it crashes after a while. So does NetBSD's, but it's a huge progress. See the images at http://panzer.utcluj.ro/~alien/coreboot/AVATT/screenshots/running/ Best regards, Cristi. -- Ing. Cristi Măgherușan, Universitatea Tehnică din Cluj-Napoca Centrul de Comunicații "Pusztai Kalman" Tel. 0264/401247 http://cc.utcluj.ro

2 2

/. effect:
by ron minnich 01 Sep '08

01 Sep '08

from just now: billybob2 writes "VIA has released a 113,800 line open source graphics driver with full mode-setting support for CRT, LCD, and DVI devices along with 2D, X-Video, and cursor acceleration. Harald Welte, VIA's open source representative, states that the next step is to add 3D (see preview), TV-out, and hardware codec support while integrating this work with existing open source projects. VIA has pre-installed Linux on a significant portion of the company's latest products, including the EVEREX gPC2, 15.4" gBook, and CloudBook. It has also helped port the open source CoreBoot BIOS (previously LinuxBIOS) to several of its motherboards." VIA seems to be making good on the promise of its open source initiative announced last April. Neat stuff. ron

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k8 and memory training
by ron minnich 01 Sep '08

01 Sep '08

see http://coreboot.pastebin.com/m354e6401 I can't really tell if it's working. I think there is a bug in simnow spd values. Computed size of the dimms from spd data is correct. The byte at 31 in SPD claims we only have 128 MB of RAM, which is wrong. It is right for one DIMM module, but we have two; it's a factor of two off. So I've made it a warning, not an error, if spd byte 31 and computed size don't agree. ron

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coreboot September 2008