coreboot January 2008

coreboot@coreboot.org

79 participants
347 discussions

[LinuxBIOS] Suspend to RAM with LinuxBIOSv2
by Rudolf Marek 13 Feb '08

13 Feb '08

Hi all, I'm pleased to announce that I got S3 working with LinuxBIOSv2 on ASUS A8V-E SE (K8 + VT8237 + K8T890)! I'm attaching the patch which is a big mess, but perhaps all are curious how is it done. To be able to do S3 we must first set the register values used for sleep in ACPI DSDT table: + Name (\_S3, Package () {0x01, 0x01, 0x00, 0x00 }) Plus we need some callbacks to SB code which tells LinuxBIOS if it is normal startup or Wakeup and if it is a wakeup we need to know the vector to return to OS. This vector is stored in one ACPI table and because LinuxBIOSv2 puts tables on same place I will take the vector value just before I overwrite it ;) So how it works? LinuxBIOS will boot as usual if S3, but not executing payload but jumping to real mode waking vector from OS. During memory initialization we need to exit the self-refresh mode instead of training the memory again. Plus we need to adjust the K8 registers to listen for SMAF messages from SB that we go S3. The serious problem is that LinuxBIOS overwrites a lot of memory - lowmem, highmem (1M above). So how to protect it for OS? I booted linux with custom memory map 2M-1GB and LinuxBIOS had 0M-2M for its own stuff. But If I reserved memory for linux this way, ACPI code refuses to work, because OS waking code must be in 1MB range. I decided to patch the kernel and put always waking code to 0xE000:0000 /linux-2.6.23.1/arch/x86_64/kernel/acpi/sleep.c void __init acpi_reserve_bootmem(void) { acpi_wakeup_address = phys_to_virt(0xE0000); //(unsigned long)alloc_bootmem_low(PAGE_SIZE*2); printk("ACpi wakeup %x\n", acpi_wakeup_address); if ((&wakeup_end - &wakeup_start) > (PAGE_SIZE*2)) printk(KERN_CRIT "ACPI: Wakeup code way too big, will crash on attempt" " to suspend\n"); } Getting close to have working implementation but one thing was still missing. The exit from Self refresh seemed not to work. But, booting with original BIOS, rebooting to LB and then suspend/resume in LB did work! Hum something was wrong with some chip, but not with memory itself. Today I found out. There seems to be some undocumented bit in Winbond W83627EHF which will leave power to right parts of the system :) The attached script fix_ehf has a workaround ;) In the meanwhile I found out how to blink with the power LED and how to overclock the motherboard + most GPIO meaning, so I updated the Wiki page with that too. So what needs to be done? 1) consolidate the memory usage of LinuxBIOSv2 2) dont clean arbitrary memory Perhaps we could reserve last 1MB of RAM or something after 8MB of mem and put linuxBIOS heap there when using S3 we would just reserve the region + (some region bellow the 1MB for AP CPU boot + ACPI tables etc) The patch has some errata update of code too, I will publish this as separate patch - I did it because I thought I got still some memory related problem. Unfortunately I do not have much time for this fun, very busy with other stuff, but I needed some break ;) Oh I forgot - the real mode switcher and A20 handler are from Linux kernel. Thanks, Rudolf isaset -y -f 0x2e 0x87 isaset -y -f 0x2e 0x87 isaset -y 0x2e 0x2f 0x7 0xa isaset -y 0x2e 0x2f 0xe6 0x10 isaset -y 0x2e 0x2f 0xe4 0x30 isadump -y -k 0x87,0x87 0x2e 0x2f 0xa

3 4

[PATCH][cbv2]Add serial port information to lbtable
by Patrick Georgi 09 Feb '08

09 Feb '08

Hi, the attached patch makes cbv2 add information about the serial port to lbtable. For this, a new record type is created. Payloads can then parse lbtable to figure out where to find the serial port (which is usually used by lb as console already). A patch for grub2 exists, too, and I'll implement a compatible change for cbv3 once the record format (and overall design etc) is stable. Regards, Patrick Georgi

5 17

Geode LX/CS5536 VSA
by Marc Jones 08 Feb '08

08 Feb '08

Geode LX/CS5536 VSA has been updated. The source and binary are attached. With this release we have changed how the binary is packaged. Previously it was posted alread compressed with nrv2b and padded to size. Going forward it is GZipd and will need to be compressed and padded by hand or by buildrom. Instructions available here: http://www.coreboot.org/AMD_Geode_Porting_Guide The following changes were made: Remove int15 callbacks removed. CPU and memory are calculated by VSA. VSA no longer takes all the MFGPTs. Two are now available for OS use. The VSA binary is always available here: http://www.amd.com/files/connectivitysolutions/geode/geode_lx/amd_vsa_lx_1.… buildrom and v2 patches to follow. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

7 17

Re: [coreboot] [LinuxBIOS] abit be6
by Jouni Mettälä 08 Feb '08

08 Feb '08

On Jan 14, 2008 5:30 PM, Jouni Mettälä <jtmettala(a)gmail.com> wrote: > > > On Jan 14, 2008 4:25 PM, Uwe Hermann <uwe(a)hermann-uwe.de> wrote: > > > On Sun, Jan 13, 2008 at 09:08:17PM +0200, Jouni Mettälä wrote: > > > It now boots with filo. This time with different filo Config file. # > > means > > > these lines were commented out. > > > > What did you change to make FILO boot from your disk? > > > I am not sure if commenting > #SUPPORT_PCI = 1 > #PCI_BRUTE_SCAN = 1 > out or adding > DEBUG_ALL = 1 > or using just fallback image instead of normal and fallback affected this. > > > > > Keyboard isn't working yet. Tested ps/2 keyboard. Using kernel as boot > file > > Does a USB keyboard work? (does the board have onboard-USB?) > > > I'll test USB keyboard as soon as possible (I'll hope today) > > > > > Some of the 440BX boards have problems with the PS/2 keyboard, I haven't > > yet found out if it's superio-related or some more general problem in > > the code somewhere... > > > > > > Please check the patch for the Abit BE6-II V2.0 I just (re)posted. Is > > your board identical to that one or is it really the "BE6" (without > > "II" or "V2.0")? If it's not exactly the same, please post some more > > information about it, e.g. 'lspci -tvnn', 'superiotool -dV', 'flashrom > > -V', > > and the output of 'getpir' (a file called 'irq_table.c'). > > > > ide_search_updated.patch didn't make keyboard working. > There reads ABIT-BE6 without II or V2 > > Files added using original bios. > > > <http://www.unmaintained-free-software.org> > > >

3 10

[LinuxBIOS] [PATCH] buildrom: add extract and busybox-config, uclibc-config targets
by Ward Vandewege 06 Feb '08

06 Feb '08

-- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

2 8

[LinuxBIOS] [patch] MSI MS-7135 (this time with attachment)
by jakllsch＠kollasch.net 02 Feb '08

02 Feb '08

Initial support for MSI MS-7135 (K8N Neo3) mainboard. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net>

4 8

LinuxBIOS on VIA EPIA EN15000
by bernhard.maenner＠mail.cablevision.at 02 Feb '08

02 Feb '08

I own a VIA EPIA EN15000 Motherboard see http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i… and I'd like to give LinuxBIOS a try. Linux lspci output is: 00:00.0 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:00.1 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:00.2 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:00.3 Host bridge: VIA Technologies, Inc. PT890 Host Bridge 00:00.4 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:00.7 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge 00:01.0 PCI bridge: VIA Technologies, Inc. VT8237 PCI Bridge 00:0d.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 80) 00:0e.0 Ethernet controller: VIA Technologies, Inc. VT6120/VT6121/VT6122 Gigabit Ethernet Adapter (rev 11) 00:0f.0 IDE interface: VIA Technologies, Inc. VIA VT6420 SATA RAID Controller (rev 80) 00:0f.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) 00:10.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) 00:10.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) 00:10.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 81) 00:10.4 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 86) 00:11.0 ISA bridge: VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] 00:11.5 Multimedia audio controller: VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller (rev 60) 00:14.0 Multimedia video controller: Internext Compression Inc iTVC15 MPEG-2 Encoder (rev 01) 01:00.0 VGA compatible controller: VIA Technologies, Inc. UniChrome Pro IGP (rev 01) Super I/O chip is Winbond W83697HG BIOS chip is SST49LF004B The "Supported Device List" includes all main devices but I can't find C7/CN700 support in the current stable version coreboot v2 nor in coreboot v3. Is there a chance to get my board working ? Can anybody tell me what to do ?

4 5

[PATCH] (resend2) fix the flashrom problem on m57sli boards with SPI flash
by Florentin Demetrescu 01 Feb '08

01 Feb '08

This patch fixes the decoding of the IO address range 0x0820->0x0827 into the LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI interface of the IT8716 SIO chip. Changes : 1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some functions of a PNP device can have more than 12 resources (ex the GPIO function of IT8716f), in which case one could have an "array overflow" inside the device structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at device init time..) 2) - define resource masks for the GPIO function in src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO ranges which are set into the LPC bridge of the SB are very strange (f.ex.: 0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching by the init code 3) - enable the flash SPI interface into src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource into the GPIO function). I know that this is problematic because not all m57sli boards are SPI, but .. do anyone have a better idea how to handle this?.. Signed-off-by: Florentin Demetrescu <echelon(a)free.fr> Patch file attached. Thanks, Florentin PS: By the way, with all due respect, Gentlemen, I think that keeping 2 (potentially incoherent) sets of resource definitions for PNP devices in 2 different places (<mobo>/Config.lb vs. <sio>/superio.c) is trully brain dammaging.. Juste my 2 (euro-)cents

4 7

i82801xx nic problems.
by joe＠smittys.pointclark.net 31 Jan '08

31 Jan '08

Hello, I am racking my brains with this. No matter what I do I can't seem to get the nic working. The nic is onboard the i82801DB southbridge down from the PCI bridge, so my Config.lb looks something like this: device pci 1e.0 on # PCI bridge: Intel Corporation 82801 PCI Bridge chip drivers/pci/onboard device pci 08.0 on end # Intel Corporation 82801DB PRO/100 VE Ethernet Controller end end But no matter what I try coreboot thinks it is a static device and disables it. do_pci_scan_bridge for PCI: 00:1e.0 PCI: pci_scan_bus for bus 01 PCI: devfn 0x0, bad id 0xffffffff PCI: devfn 0x8, bad id 0xffffffff PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff Disabling static device: PCI: 01:08.0 This wouldn't really be a problem if Linux detected it but that is not even happening. I am really stumped here. I even tried loading the Intel Boot Agent pci rom from the original bios but the same thing happens. Help? Thanks - Joe

3 9

[LinuxBIOS] Qemu compile for LinuxBIOSV2
by Marc Karasek 31 Jan '08

31 Jan '08

I am trying to get up to speed on LinuxBIOS and to that end have tried to compile both v3 & v2 for qemu. I have successfully compiled and run v3 with a filo package on my Fedora 8 system. When I try to compile v2 with a filo.elf payload I get the : collect2: ld terminated with signal 11 [Segmentation fault] Error In looking at the compile it has gotten through the compile part and is linking. rm -f linuxbios.a ar cr linuxbios.a malloc.o pci_ops.o smbus_ops.o memset.o pci_ops_auto.o linuxbios_table.o fallback_boot.o pciexp_device.o keyboard.o pnp_device.o printk.o irq_tables.o pcix_device.o i8259.o pci_device.o console.o elfboot.o hardwaremain.o boot.o exception.o delay.o version.o pci_ops_mmconf.o memcmp.o isa-dma.o hypertransport.o vtxprintf.o tables.o root_device.o cardbus_device.o uart8250.o device_util.o ./option_table.o compute_ip_checksum.o device.o northbridge.o memcpy.o agp_device.o vgabios.o clog2.o pirq_routing.o memmove.o pci_ops_conf2.o pci_ops_conf1.o mc146818rtc.o rom_stream.o c_start.o vsprintf.o cpu.o static.o gcc -m32 -nostdlib -r -o linuxbios_ram.o c_start.o mainboard.o uart8250_console.o linuxbios.a /usr/lib/gcc/i386-redhat-linux/4.1.2/libgcc.a gcc -m32 -nostdlib -nostartfiles -static -o linuxbios_ram -T /home/mk216460/src/LinuxBIOSv2-2988/src/config/linuxbios_ram.ld linuxbios_ram.o collect2: ld terminated with signal 11 [Segmentation fault] make[1]: *** [linuxbios_ram] Error 1 make[1]: Leaving directory `/home/mk216460/src/LinuxBIOSv2-2988/targets/emulation/qemu-i386/qemu-i386/image' In looking at the /var/log/messages you see Nov 30 14:37:02 dhcp-uatl04-156-163 kernel: ld[3691]: segfault at 00000030 eip 08068b2c esp bfc6a0f0 error 4 Any help/pointers for what to look at would be helpful. -- /********************* Marc Karasek MTS Sun Microsystems mailto:marc.karasek@sun.com ph:770.360.6415 *********************/

6 20

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot January 2008