coreboot August 2007

coreboot@coreboot.org

78 participants
202 discussions

[LinuxBIOS] r2750 - trunk/LinuxBIOSv2/util/probe_superio
by svn＠openbios.org 28 Aug '07

28 Aug '07

Author: uwe Date: 2007-08-28 12:43:57 +0200 (Tue, 28 Aug 2007) New Revision: 2750 Modified: trunk/LinuxBIOSv2/util/probe_superio/probe_superio.c Log: This patch makes ITE Super I/O probing/dumping a little bit more generic, fixes minor coding style issues and prepares the table for supporting more chips of the ITE IT87xx Super I/O family. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/util/probe_superio/probe_superio.c =================================================================== --- trunk/LinuxBIOSv2/util/probe_superio/probe_superio.c 2007-08-27 07:28:28 UTC (rev 2749) +++ trunk/LinuxBIOSv2/util/probe_superio/probe_superio.c 2007-08-28 10:43:57 UTC (rev 2750) @@ -35,22 +35,22 @@ unsigned char regval(unsigned short port, unsigned char reg) { outb(reg, port); - return inb(port+1); + return inb(port + 1); } void regwrite(unsigned short port, unsigned char reg, unsigned char val) { outb(reg, port); - outb(val, port+1); + outb(val, port + 1); } void dump_ns8374(unsigned short port) { - printf("Enables: 21=%02x, 22=%02x, 23=%02x, 24=%02x, 26=%02x\n", - regval(port,0x21), regval(port,0x22), - regval(port,0x23), regval(port,0x24), regval(port,0x26)); + printf("Enables: 21=%02x, 22=%02x, 23=%02x, 24=%02x, 26=%02x\n", + regval(port, 0x21), regval(port, 0x22), regval(port, 0x23), + regval(port, 0x24), regval(port, 0x26)); printf("SMBUS at %02x\n", regval(port, 0x2a)); /* check COM1. This is all we care about at present. */ - printf("COM 1 is Globally %s\n", regval(port,0x26)&8 ? "disabled" : "enabled"); + printf("COM 1 is Globally %s\n", regval(port, 0x26) & 8 ? "disabled" : "enabled"); /* select com1 */ regwrite(port, 0x07, 0x03); printf("COM 1 is locally %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); @@ -77,11 +77,11 @@ printf ("Fintek F71872\n"); break; default: - printf ("Unknown Fintek SuperIO: did=0x%04x\n",did); + printf ("Unknown Fintek SuperI/O: did=0x%04x\n", did); return; } - printf("Flash write is %s.\n", regval(port, 0x28)&0x80 ? "enabled" : "disabled"); + printf("Flash write is %s.\n", regval(port, 0x28) & 0x80 ? "enabled" : "disabled"); printf("Flash control is 0x%04x.\n", regval(port, 0x28)); printf("27=%02x\n", regval(port, 0x27)); printf("29=%02x\n", regval(port, 0x29)); @@ -92,27 +92,27 @@ regwrite(port, 0x07, 0x01); printf("UART1 is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("UART1 base=%02x%02x, irq=%02x, mode=%s\n", - regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f, - regval(port, 0xf0)&0x10 ? "RS485":"RS232"); + regval(port, 0x60), regval(port, 0x61), regval(port, 0x70) & 0x0f, + regval(port, 0xf0) & 0x10 ? "RS485":"RS232"); /* select UART 2 */ regwrite(port, 0x07, 0x02); printf("UART2 is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("UART2 base=%02x%02x, irq=%02x, mode=%s\n", - regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f, - regval(port, 0xf0)&0x10 ? "RS485":"RS232"); + regval(port, 0x60), regval(port, 0x61), regval(port, 0x70) & 0x0f, + regval(port, 0xf0) & 0x10 ? "RS485":"RS232"); /* select Parport */ regwrite(port, 0x07, 0x03); printf("PARPORT is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("PARPORT base=%02x%02x, irq=%02x\n", - regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f); + regval(port, 0x60), regval(port, 0x61), regval(port, 0x70) & 0x0f); /* select hw monitor */ regwrite(port, 0x07, 0x04); printf("HW monitor is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("HW monitor base=%02x%02x, irq=%02x\n", - regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f); + regval(port, 0x60), regval(port, 0x61), regval(port, 0x70) & 0x0f); /* select gpio */ regwrite(port, 0x07, 0x05); @@ -129,25 +129,39 @@ } -//End Of Table +/* End Of Table */ #define EOT -1 -//NO LDN needed +/* NO LDN needed */ #define NOLDN -2 -//Not Available +/* Not Available */ #define NANA -3 -//Biggest LDN +/* Maximum Name Length */ +#define MAXNAMELEN 20 +/* Biggest LDN */ #define MAXLDN 0xa -//MAXimum NUMber of Indexes +/* biggestLDN + 0 + NOLDN + EOT */ +#define LDNSIZE MAXLDN + 3 +/* MAXimum NUMber of Indexes */ #define MAXNUMIDX 70 +#define IDXSIZE MAXNUMIDX + 1 + const static struct ite_registers { - signed short superio_id; //yes, it should be unsigned, but then EOT has to be positive + /* yes, superio_id should be unsigned, but EOT has to be negative */ + signed short superio_id; + char name[MAXNAMELEN]; struct ite_ldnidx { signed short ldn; - signed short idx[MAXNUMIDX+1]; - signed short def[MAXNUMIDX+1]; - } ldn[MAXLDN+3]; //biggestLDN+0+NOLDN+EOT + signed short idx[IDXSIZE]; + signed short def[IDXSIZE]; + } ldn[LDNSIZE]; } ite_reg_table[] = { - {0x8712,{ + {0x8702, "IT8702", { + {EOT}}}, + {0x8705, "IT8705 or IT8700", { + {EOT}}}, + {0x8710, "IT8710", { + {EOT}}}, + {0x8712, "IT8712", { {NOLDN, {0x07,0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, {NANA,0x87,0x12,0x08,0x00,0x00,0x00,EOT}}, @@ -164,8 +178,10 @@ {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,EOT}, {0x00,0x03,0x78,0x07,0x78,0x07,0x03,0x03,EOT}}, {0x4, - {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,EOT}, - {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00,0x00,0x00,NANA,NANA,EOT}}, + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3, + 0xf4,0xf5,0xf6,EOT}, + {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00,0x00, + 0x00,NANA,NANA,EOT}}, {0x5, {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x00,EOT}}, @@ -173,8 +189,18 @@ {0x30,0x70,0x71,0xf0,EOT}, {0x00,0x0c,0x02,0x00,EOT}}, {0x7, - {0x25,0x26,0x27,0x28,0x29,0x2a,0x2c,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0x72,0x73,0x74,0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xc0,0xc1,0xc2,0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,EOT}, - {0x01,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,0x00,EOT}}, + {0x25,0x26,0x27,0x28,0x29,0x2a,0x2c,0x60,0x61,0x62, + 0x63,0x64,0x65,0x70,0x71,0x72,0x73,0x74,0xb0,0xb1, + 0xb2,0xb3,0xb4,0xb5,0xb8,0xb9,0xba,0xbb,0xbc,0xbd, + 0xc0,0xc1,0xc2,0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc, + 0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4, + 0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,EOT}, + {0x01,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x30,0x38,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x40,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,0x00,EOT}}, {0x8, {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x00,0x0a,0x00,EOT}}, @@ -185,6 +211,10 @@ {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, {EOT}}}, + {0x8716, "IT8716", { + {EOT}}}, + {0x8718, "IT8718", { + {EOT}}}, {EOT} }; @@ -204,73 +234,65 @@ 0x8708 -> IT8708 0x8710 -> IT8710 0x8712 -> IT8712 - 0x8716 -> IT8716 or IT8726 (identical except CPU voltage control) + 0x8716 -> IT8716 0x8718 -> IT8718 - 0x8726 does not exist according to datasheet, but experience differs + 0x8726 -> IT8726 (datasheet wrongly says 0x8716) */ switch(id) { - case 0x8702: - printf ("IT8702\n"); - break; - case 0x8705: - printf ("IT8700 or IT8705\n"); - break; - case 0x8710: - printf ("IT8710\n"); - break; - case 0x8712: - printf ("IT8712\n"); - for (i=0;; i++) { - if (ite_reg_table[i].superio_id == EOT) + case 0x8702: + case 0x8705: + case 0x8710: + case 0x8712: + case 0x8716: + case 0x8718: + for (i=0;; i++) { + if (ite_reg_table[i].superio_id == EOT) + break; + if ((unsigned short)ite_reg_table[i].superio_id != id) + continue; + printf ("%s\n", ite_reg_table[i].name); + for (j=0;; j++) { + if (ite_reg_table[i].ldn[j].ldn == EOT) break; - if ((unsigned short)ite_reg_table[i].superio_id != id) - continue; - for (j=0;; j++) { - if (ite_reg_table[i].ldn[j].ldn == EOT) + if (ite_reg_table[i].ldn[j].ldn != NOLDN) { + printf("switching to LDN 0x%01x\n", + ite_reg_table[i].ldn[j].ldn); + regwrite(port, 0x07, + ite_reg_table[i].ldn[j].ldn); + } + idx = ite_reg_table[i].ldn[j].idx; + printf("idx "); + for (k=0;; k++) { + if (idx[k] == EOT) break; - if (ite_reg_table[i].ldn[j].ldn != NOLDN) { - printf("switching to LDN 0x%01x\n", ite_reg_table[i].ldn[j].ldn); - regwrite(port, 0x07, ite_reg_table[i].ldn[j].ldn); - } - idx = ite_reg_table[i].ldn[j].idx; - printf("idx "); - for (k=0;; k++) { - if (idx[k] == EOT) - break; + printf("%02x ", idx[k]); + } + printf("\nval "); + for (k=0;; k++) { + if (idx[k] == EOT) + break; + printf("%02x ", regval(port, idx[k])); + } + printf("\ndef "); + idx = ite_reg_table[i].ldn[j].def; + for (k=0;; k++) { + if (idx[k] == EOT) + break; + if (idx[k] == NANA) + printf("NA "); + else printf("%02x ", idx[k]); - } - printf("\nval "); - for (k=0;; k++) { - if (idx[k] == EOT) - break; - printf("%02x ", regval(port, idx[k])); - } - printf("\ndef "); - idx = ite_reg_table[i].ldn[j].def; - for (k=0;; k++) { - if (idx[k] == EOT) - break; - if (idx[k] == NANA) - printf("NA "); - else - printf("%02x ", idx[k]); - } - printf("\n"); } + printf("\n"); + } - } - break; - case 0x8716: - printf ("IT8716 or IT8726\n"); - break; - case 0x8718: - printf ("IT8718\n"); - break; - default: - printf ("unknown ITE chip, id=%04x\n", id); - for (i=0x20; i<=0x24; i++) - printf("index %02x=%02x\n", i, regval(port, i)); - break; + } + break; + default: + printf ("unknown ITE chip, id=%04x\n", id); + for (i=0x20; i<=0x24; i++) + printf("index %02x=%02x\n", i, regval(port, i)); + break; } } @@ -280,15 +302,15 @@ outb(0x20, port); if (inb(port) != 0x20) { if (inb(port) == 0xff ) - printf ("No SuperIO chip found at 0x%04x\n", port); + printf ("No SuperI/O chip found at 0x%04x\n", port); else printf("probing 0x%04x, failed (0x%02x), data returns 0x%02x\n", - port, inb(port), inb(port+1)); + port, inb(port), inb(port + 1)); return; } - id = inb(port+1); + id = inb(port + 1); - printf("SuperIO found at 0x%02x: id = 0x%02x\n", port, id); + printf("SuperI/O found at 0x%02x: id = 0x%02x\n", port, id); if (id == 0xff) return; @@ -312,40 +334,39 @@ probe_idregs_fintek(unsigned short port){ unsigned int vid, did, success = 0; - // Enable configuration sequence (Fintek uses this for example) - // Older ITE chips have the same enable sequence + /* Enable configuration sequence (Fintek uses this for example) + Older ITE chips have the same enable sequence */ outb(0x87, port); outb(0x87, port); - // outb(0x20, port); if (inb(port) != 0x20) { if (inb(port) == 0xff ) printf ("No SuperIO chip found at 0x%04x\n", port); else printf("probing 0x%04x, failed (0x%02x), data returns 0x%02x\n", - port, inb(port), inb(port+1)); + port, inb(port), inb(port + 1)); return; } - did = inb(port+1); + did = inb(port + 1); - did = did|(regval(port, 0x21)<<8); + did |= (regval(port, 0x21)<<8); vid = regval(port, 0x23); - vid = vid|(regval(port, 0x24)<<8); + vid |= (regval(port, 0x24)<<8); printf("SuperIO found at 0x%02x: vid=0x%04x/did=0x%04x\n", port, vid, did); if (vid == 0xff || vid == 0xffff) return; - // printf("%s\n", familyid[id]); + /* printf("%s\n", familyid[id]); */ switch(did) { - case 0x0887: // reversed for ITE8708 - case 0x1087: // reversed for ITE8710 + case 0x0887: /* pseudoreversed for ITE8708 */ + case 0x1087: /* pseudoreversed for ITE8710 */ success = 1; dump_ite(port, ((did & 0xff) << 8) | ((did & 0xff00) >> 8)); - // disable configuration + /* disable configuration */ regwrite(port, 0x02, 0x02); break; default: @@ -362,7 +383,7 @@ if (!success) printf("no dump for vid 0x%04x, did 0x%04x\n", vid, did); - // disable configuration (for Fintek, doesn't hurt ITE) + /* disable configuration (for Fintek, doesn't hurt ITE) */ outb(0xaa, port); } @@ -370,12 +391,12 @@ probe_idregs_ite(unsigned short port){ unsigned int id, chipver; - // Enable configuration sequence (ITE uses this for newer IT87[012]x) - // IT871[01] uses 0x87, 0x87 -> fintek detection should handle it - // IT8761 uses 0x87, 0x61, 0x55, 0x55/0xaa - // IT86xx series uses different ports - // IT8661 uses 0x86, 0x61, 0x55/0xaa, 0x55/0xaa and 32 more writes - // IT8673 uses 0x86, 0x80, 0x55/0xaa, 0x55/0xaa and 32 more writes + /* Enable configuration sequence (ITE uses this for newer IT87[012]x) + IT871[01] uses 0x87, 0x87 -> fintek detection should handle it + IT8761 uses 0x87, 0x61, 0x55, 0x55/0xaa + IT86xx series uses different ports + IT8661 uses 0x86, 0x61, 0x55/0xaa, 0x55/0xaa and 32 more writes + IT8673 uses 0x86, 0x80, 0x55/0xaa, 0x55/0xaa and 32 more writes */ outb(0x87, port); outb(0x01, port); outb(0x55, port); @@ -384,23 +405,23 @@ else outb(0xAA, port); - // Read Chip ID Byte 1 + /* Read Chip ID Byte 1 */ id = regval(port, 0x20); if (id != 0x87) { if (inb(port) == 0xff ) printf ("No SuperIO chip found at 0x%04x\n", port); else printf("probing 0x%04x, failed (0x%02x), data returns 0x%02x\n", - port, inb(port), inb(port+1)); + port, inb(port), inb(port + 1)); return; } id <<= 8; - // Read Chip ID Byte 2 + /* Read Chip ID Byte 2 */ id |= regval(port, 0x21); - // Read Chip Version, only bit 3..0 for all IT87xx + /* Read Chip Version, only bit 3..0 for all IT87xx */ chipver = regval(port, 0x22) & 0x0f; /* ID Mapping Table @@ -410,26 +431,27 @@ 0x8705 -> IT8700 or IT8705 0x8710 -> IT8710 0x8712 -> IT8712 - 0x8716 -> IT8716 or IT8726 (identical except CPU voltage control) + 0x8716 -> IT8716 0x8718 -> IT8718 + 0x8726 -> IT8726 (datasheet wrongly says 0x8716) */ - printf("ITE? SuperIO found at 0x%02x: id=0x%04x, chipver=0x%01x\n", + printf("SuperI/O found at 0x%02x: id=0x%04x, chipver=0x%01x\n", port, id, chipver); switch(id) { case 0x8702: case 0x8705: - case 0x8710: //pointless, IT8710 has different enable sequence case 0x8712: case 0x8716: case 0x8718: + case 0x8726: dump_ite(port, id); break; default: printf("no dump for id 0x%04x\n", id); break; } - // disable configuration + /* disable configuration */ regwrite(port, 0x02, 0x02); }

1 0

[LinuxBIOS] Latest on via epia-m for LinuxBIOS v2?
by Matthew Bloch 28 Aug '07

28 Aug '07

Hi there, I am trying to build a LinuxBIOS setup to turn an Epia-M board into a NAS server and am stuck on the configuration. FILO is built and tested (with grub). I've now checked out LinuxBIOSv2, and am trying to use this configuration: mnas:~/LinuxBIOSv2/targets/via/epia-m/epia-m# cat ../Config.lb target epia-m mainboard via/epia-m option MAXIMUM_CONSOLE_LOGLEVEL=8 option DEFAULT_CONSOLE_LOGLEVEL=8 option CONFIG_CONSOLE_SERIAL8250=1 option ROM_SIZE=256*1024 option HAVE_OPTION_TABLE=1 option CONFIG_ROM_PAYLOAD=1 option HAVE_FALLBACK_BOOT=0 option _RAMBASE=0x00004000 romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x30000 option LINUXBIOS_EXTRA_VERSION=".0-Normal" option PAYLOAD_SIZE=0xc000 payload /root/filo-0.5/filo.elf end buildrom ./linuxbios.rom ROM_SIZE "normal" However trying to build it gives me: ./romcc -mcpu=c3 ... (snip lots of -Is and -Ds) /root/LinuxBIOSv2/src/mainboard/via/epia-m/auto.c -o auto.inc earlymtrr.c:23.0: "XIP_ROM_BASE is not a multiple of XIP_ROM_SIZE" make[1]: *** [auto.inc] Error 1 make[1]: Leaving directory `/root/LinuxBIOSv2/targets/via/epia-m/epia-m/normal' I'm assuming something elementary is missing from the config but I'm not sure where to look next. Can someone point me in the right direction? I will happily update the HOWTO in exchange :) cheers, -- Matthew

3 9

[LinuxBIOS] DELL Latitude D820 flashrom info
by Johannes Engel 28 Aug '07

28 Aug '07

Hello! As Carl-Daniel suggested attached you find the info for a Dell Latitude D820 laptop. Greetings, Johannes # dmidecode 2.8 SMBIOS 2.4 present. 64 structures occupying 2959 bytes. Table at 0x000F6E30. Handle 0xDA00, DMI type 218, 251 bytes OEM-specific Type Header and Data: DA FB 00 DA B2 00 0D 5F 1F 37 40 7D 00 00 00 00 00 7E 00 02 00 00 00 40 00 04 00 01 00 41 00 04 00 00 00 90 00 05 00 00 00 91 00 05 00 01 00 92 00 05 00 02 00 65 00 06 00 00 00 66 00 06 00 01 00 5E 00 07 00 01 00 5F 00 07 00 00 00 F1 00 08 00 00 00 F2 00 08 00 01 00 F3 00 08 00 02 00 0F 00 09 00 00 00 11 00 09 00 01 00 05 00 09 00 02 00 12 00 09 00 03 00 06 00 09 00 04 00 31 00 0A 00 00 00 32 00 0A 00 01 00 33 00 0A 00 02 00 34 00 0A 00 03 00 35 00 0A 00 04 00 07 00 0B 00 00 00 0B 00 0B 00 01 00 0C 00 0B 00 02 00 0D 00 0B 00 03 00 89 01 0C 00 00 00 8A 01 0C 00 01 00 42 00 0D 00 01 00 43 00 0D 00 00 00 55 00 0E 00 00 00 6D 00 0E 00 01 00 98 01 0E 00 02 00 0A 01 0F 00 01 00 0B 01 0F 00 00 00 2D 00 10 00 02 00 27 01 10 00 03 00 FF FF 00 00 00 00 Handle 0xDA01, DMI type 218, 251 bytes OEM-specific Type Header and Data: DA FB 01 DA B2 00 0D 5F 1F 37 40 6E 00 10 00 01 00 2E 00 10 00 00 00 11 01 11 00 00 00 10 01 11 00 01 00 F0 00 12 00 01 00 ED 00 12 00 00 00 41 01 13 00 01 00 40 01 13 00 00 00 47 01 14 00 01 00 46 01 14 00 00 00 4A 01 15 00 00 00 4B 01 15 00 01 00 52 01 16 00 01 00 53 01 16 00 00 00 80 01 17 00 01 00 7F 01 17 00 00 00 7C 01 18 00 01 00 7B 01 18 00 00 00 7E 01 19 00 01 00 7D 01 19 00 00 00 92 01 1A 00 00 00 91 01 1A 00 01 00 94 01 1B 00 00 00 93 01 1B 00 01 00 86 01 1C 00 01 00 85 01 1C 00 00 00 82 01 1D 00 01 00 81 01 1D 00 00 00 84 01 1E 00 01 00 83 01 1E 00 00 00 9B 01 1F 00 00 00 9C 01 1F 00 01 00 9D 01 1F 00 02 00 9E 01 1F 00 03 00 8D 01 20 00 00 00 8E 01 20 00 01 00 EA 00 21 00 00 00 EB 00 21 00 01 00 EC 00 21 00 02 00 FF FF 00 00 00 00 Handle 0xDA02, DMI type 218, 251 bytes OEM-specific Type Header and Data: DA FB 02 DA B2 00 0D 5F 1F 37 40 28 00 22 00 00 00 29 00 22 00 01 00 2A 00 22 00 02 00 2B 00 23 00 00 00 2C 00 24 00 00 00 E7 00 25 00 01 00 E6 00 25 00 00 00 0E 01 26 00 01 00 0F 01 26 00 00 00 9B 00 27 00 01 00 9C 00 27 00 00 00 87 00 28 00 01 00 88 00 28 00 00 00 D1 00 29 00 01 00 D2 00 29 00 00 00 E8 00 2A 00 01 00 E9 00 2A 00 00 00 51 01 2B 00 00 00 50 01 2B 00 01 00 12 01 2C 00 01 00 13 01 2C 00 00 00 9A 01 2D 00 01 00 99 01 2D 00 00 00 87 01 2E 00 00 00 88 01 2E 00 01 00 01 01 2F 00 00 00 02 01 2F 00 01 00 04 01 2F 00 02 00 45 01 45 01 01 00 44 01 44 01 00 00 00 80 00 80 01 00 00 A0 00 A0 01 00 05 80 05 80 01 00 76 01 76 01 01 00 75 01 75 01 01 00 9F 01 9F 01 00 00 A0 01 A0 01 01 00 01 F0 01 F0 00 00 02 F0 02 F0 00 00 FF FF 00 00 00 00 Handle 0xDA03, DMI type 218, 29 bytes OEM-specific Type Header and Data: DA 1D 03 DA B2 00 0D 5F 1F 37 40 03 F0 03 F0 00 00 04 F0 04 F0 00 00 FF FF 00 00 00 00 Handle 0x0000, DMI type 0, 24 bytes BIOS Information Vendor: Dell Inc. Version: A07 Release Date: 06/15/2007 Address: 0xF0000 Runtime Size: 64 kB ROM Size: 576 kB Characteristics: ISA is supported PCI is supported PC Card (PCMCIA) is supported PNP is supported BIOS is upgradeable BIOS shadowing is allowed Boot from CD is supported Selectable boot is supported 3.5"/720 KB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) ACPI is supported USB legacy is supported AGP is supported Smart battery is supported BIOS boot specification is supported Function key-initiated network boot is supported Targeted content distribution is supported BIOS Revision: 0.7 Firmware Revision: 0.7 Handle 0x0100, DMI type 1, 27 bytes System Information Manufacturer: Dell Inc. Product Name: Latitude D820 Version: Not Specified Serial Number: 6CKZK2J UUID: 44454C4C-4300-104B-805A-B6C04F4B324A Wake-up Type: Power Switch SKU Number: Not Specified Family: Handle 0x0200, DMI type 2, 9 bytes Base Board Information Manufacturer: Dell Inc. Product Name: 0GF470 Version: Serial Number: .6CKZK2J.CN486436AH2437. Handle 0x0300, DMI type 3, 13 bytes Chassis Information Manufacturer: Dell Inc. Type: Portable Lock: Not Present Version: Not Specified Serial Number: 6CKZK2J Asset Tag: Not Specified Boot-up State: Safe Power Supply State: Safe Thermal State: Safe Security Status: None Handle 0x0301, DMI type 126, 13 bytes Inactive Handle 0x0400, DMI type 4, 40 bytes Processor Information Socket Designation: Microprocessor Type: Central Processor Family: Pentium M Manufacturer: Intel ID: E8 06 00 00 FF FB E9 BF Signature: Type 0, Family 6, Model 14, Stepping 8 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) APIC (On-chip APIC hardware supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) PAT (Page attribute table) CLFSH (CLFLUSH instruction supported) DS (Debug store) ACPI (ACPI supported) MMX (MMX technology supported) FXSR (Fast floating-point save and restore) SSE (Streaming SIMD extensions) SSE2 (Streaming SIMD extensions 2) SS (Self-snoop) HTT (Hyper-threading technology) TM (Thermal monitor supported) PBE (Pending break enabled) Version: Not Specified Voltage: 3.3 V External Clock: 166 MHz Max Speed: 1800 MHz Current Speed: 1666 MHz Status: Populated, Enabled Upgrade: None L1 Cache Handle: 0x0700 L2 Cache Handle: 0x0701 L3 Cache Handle: Not Provided Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified Handle 0x0700, DMI type 7, 19 bytes Cache Information Socket Designation: Not Specified Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 32 KB Maximum Size: 32 KB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: None System Type: Data Associativity: 4-way Set-associative Handle 0x0701, DMI type 7, 19 bytes Cache Information Socket Designation: Not Specified Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Varies With Memory Address Location: Internal Installed Size: 2048 KB Maximum Size: 2048 KB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: 15 ns Error Correction Type: None System Type: Unified Associativity: Other Handle 0x0800, DMI type 126, 9 bytes Inactive Handle 0x0801, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: SERIAL1 Internal Connector Type: None External Reference Designator: Not Specified External Connector Type: DB-9 male Port Type: Serial Port 16550A Compatible Handle 0x0803, DMI type 126, 9 bytes Inactive Handle 0x0804, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: USB Internal Connector Type: None External Reference Designator: Not Specified External Connector Type: Access Bus (USB) Port Type: USB Handle 0x0805, DMI type 126, 9 bytes Inactive Handle 0x0806, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: MONITOR Internal Connector Type: None External Reference Designator: Not Specified External Connector Type: DB-15 female Port Type: Video Port Handle 0x0808, DMI type 126, 9 bytes Inactive Handle 0x0809, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: IrDA Internal Connector Type: None External Reference Designator: Not Specified External Connector Type: Infrared Port Type: Other Handle 0x080A, DMI type 126, 9 bytes Inactive Handle 0x080B, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: FireWire Internal Connector Type: None External Reference Designator: Not Specified External Connector Type: IEEE 1394 Port Type: Firewire (IEEE P1394) Handle 0x080C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Modem Internal Connector Type: None External Reference Designator: Not Specified External Connector Type: RJ-11 Port Type: Modem Port Handle 0x080D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Ethernet Internal Connector Type: None External Reference Designator: Not Specified External Connector Type: RJ-45 Port Type: Network Port Handle 0x0900, DMI type 9, 13 bytes System Slot Information Designation: PCMCIA 0 Type: 32-bit PC Card (PCMCIA) Current Usage: Available Length: Other ID: Adapter 0, Socket 0 Characteristics: 5.0 V is provided 3.3 V is provided PC Card-16 is supported Cardbus is supported Zoom Video is supported Modem ring resume is supported Handle 0x0902, DMI type 126, 13 bytes Inactive Handle 0x0A00, DMI type 10, 6 bytes On Board Device Information Type: Video Status: Enabled Description: Intel 945GM Graphics Handle 0x0A01, DMI type 10, 6 bytes On Board Device Information Type: Sound Status: Enabled Description: Sigmatel 9200 Handle 0x0B00, DMI type 11, 5 bytes OEM Strings String 1: Dell System String 2: 5[0003] String 3: 13[PP04X] Handle 0x0D00, DMI type 13, 22 bytes BIOS Language Information Installable Languages: 1 en|US|iso8859-1 Currently Installed Language: en|US|iso8859-1 Handle 0x1000, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 4 GB Error Information Handle: Not Provided Number Of Devices: 2 Handle 0x1100, DMI type 17, 27 bytes Memory Device Array Handle: 0x1000 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 512 MB Form Factor: DIMM Set: None Locator: DIMM_B Bank Locator: Not Specified Type: DDR Type Detail: Synchronous Speed: 667 MHz (1.5 ns) Manufacturer: CE00000000000000 Serial Number: F54D9A85 Asset Tag: 430645 Part Number: M4 70T6554CZ3-CE6 Handle 0x1101, DMI type 17, 27 bytes Memory Device Array Handle: 0x1000 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 512 MB Form Factor: DIMM Set: None Locator: DIMM_A Bank Locator: Not Specified Type: DDR Type Detail: Synchronous Speed: 667 MHz (1.5 ns) Manufacturer: CE00000000000000 Serial Number: F54D9ADE Asset Tag: 430645 Part Number: M4 70T6554CZ3-CE6 Handle 0x1300, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0000009FFFF Range Size: 640 kB Physical Array Handle: 0x1000 Partition Width: 0 Handle 0x1301, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000100000 Ending Address: 0x0003FFFFFFF Range Size: 1023 MB Physical Array Handle: 0x1000 Partition Width: 0 Handle 0x1400, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0000009FFFF Range Size: 640 kB Physical Device Handle: 0x1100 Memory Array Mapped Address Handle: 0x1300 Partition Row Position: 1 Handle 0x1401, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000100000 Ending Address: 0x0001FFFFFFF Range Size: 511 MB Physical Device Handle: 0x1100 Memory Array Mapped Address Handle: 0x1301 Partition Row Position: 1 Handle 0x1402, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00020000000 Ending Address: 0x0003FFFFFFF Range Size: 512 MB Physical Device Handle: 0x1101 Memory Array Mapped Address Handle: 0x1301 Partition Row Position: 1 Handle 0x1500, DMI type 21, 7 bytes Built-in Pointing Device Type: Touch Pad Interface: Bus Mouse Buttons: 2 Handle 0x1600, DMI type 22, 26 bytes Portable Battery Location: Sys. Battery Bay Manufacturer: SMP Name: DELL YD6236A Design Capacity: 78000 mWh Design Voltage: 11100 mV SBDS Version: 1.0 Maximum Error: 5% SBDS Serial Number: 0792 SBDS Manufacture Date: 2006-10-10 SBDS Chemistry: LION OEM-specific Information: 0x00000001 Handle 0x1601, DMI type 22, 26 bytes Portable Battery Location: Sys. Module Bay Manufacturer: Sony Name: DELL 0000M78 Design Capacity: 42000 mWh Design Voltage: 11100 mV SBDS Version: 1.0 Maximum Error: 16% SBDS Serial Number: 023D SBDS Manufacture Date: 2006-09-13 SBDS Chemistry: LiP OEM-specific Information: 0x00000002 Handle 0x1602, DMI type 126, 26 bytes Inactive Handle 0x1B00, DMI type 27, 12 bytes Cooling Device Type: Fan Status: OK OEM-specific Information: 0x0000DD00 Handle 0x1C00, DMI type 28, 20 bytes Temperature Probe Description: CPU Internal Temperature Location: Processor Status: OK Maximum Value: 127.0 deg C Minimum Value 0.0 deg C Resolution: 1.000 deg C Tolerance: 0.5 deg C Accuracy: Unknown OEM-specific Information: 0x0000DC00 Handle 0x2000, DMI type 32, 11 bytes System Boot Information Status: No errors detected Handle 0xB000, DMI type 176, 5 bytes OEM-specific Type Header and Data: B0 05 00 B0 01 Handle 0xB100, DMI type 177, 12 bytes OEM-specific Type Header and Data: B1 0C 00 B1 03 00 00 00 00 00 00 00 Handle 0xB200, DMI type 178, 6 bytes OEM-specific Type Header and Data: B2 06 00 B2 E7 0C Handle 0xD000, DMI type 208, 10 bytes OEM-specific Type Header and Data: D0 0A 00 D0 01 04 FE 00 CC 01 Handle 0xD100, DMI type 126, 12 bytes Inactive Handle 0xD200, DMI type 210, 12 bytes OEM-specific Type Header and Data: D2 0C 00 D2 F8 03 04 03 06 80 04 05 Handle 0xD300, DMI type 211, 13 bytes OEM-specific Type Header and Data: D3 0D 00 D3 01 04 02 01 00 00 00 00 02 Strings: Back of System Handle 0xD800, DMI type 216, 9 bytes OEM-specific Type Header and Data: D8 09 00 D8 01 03 01 F0 03 Strings: Intel Corp. 1343 Handle 0xD900, DMI type 217, 8 bytes OEM-specific Type Header and Data: D9 08 00 D9 01 02 01 03 Strings: US-101 Proprietary Handle 0xDB00, DMI type 219, 9 bytes OEM-specific Type Header and Data: DB 09 00 DB 03 01 02 03 FF Strings: System Device Bay Floppy, Battery, CD-ROM, CD-RW, DVD, DVD+RW, DVD+/-RW, Hard Disk Battery Handle 0xDB01, DMI type 219, 9 bytes OEM-specific Type Header and Data: DB 09 01 DB 03 01 02 03 FF Strings: System DBay Floppy, CD-ROM, CD-RW, DVD, DVD+RW, DVD+/-RW, Hard Disk EMPTY Handle 0xDB80, DMI type 126, 9 bytes Inactive Handle 0xDB81, DMI type 126, 9 bytes Inactive Handle 0x8100, DMI type 129, 8 bytes OEM-specific Type Header and Data: 81 08 00 81 01 01 02 01 Strings: Intel_ASF Dell_ASF_001 Handle 0xDC00, DMI type 220, 22 bytes OEM-specific Type Header and Data: DC 16 00 DC 01 F0 00 00 02 F0 00 00 00 00 03 F0 04 F0 00 00 00 00 Handle 0xDD00, DMI type 221, 19 bytes OEM-specific Type Header and Data: DD 13 00 DD 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Handle 0xD400, DMI type 212, 47 bytes OEM-specific Type Header and Data: D4 2F 00 D4 74 00 75 00 00 10 2D 2E 5C 00 78 BF 40 5D 00 78 BF 00 2D 01 1D EF 10 2E 01 1D EF 00 08 00 1D DF 00 03 00 1D DF 00 FF FF 00 00 00 Handle 0xDE00, DMI type 222, 13 bytes OEM-specific Type Header and Data: DE 0D 00 DE 01 02 FF FF 00 00 00 00 00 Handle 0x7F00, DMI type 127, 4 bytes End Of Table Calibrating delay loop... 472M loops per second. ok No LinuxBIOS table found. Found chipset "ICH7M": Enabling flash write... OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0xb8, id2 0x32 Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for At29C040A, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for At29C020, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for Mx29f002, 256 KB probe_29f002: id1 0x34, id2 0x6d Probing for SST29EE020A, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for SST28SF040A, 512 KB probe_28sf040: id1 0xb8, id2 0x32 Probing for SST39SF010A, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for SST39SF020A, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for SST39SF040, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for SST39VF020, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for SST49LF040B, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for SST49LF040, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for SST49LF020A, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for SST49LF080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF002A/B, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for SST49LF003A/B, 384 KB probe_jedec: id1 0x72, id2 0xad Probing for SST49LF004A/B, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for SST49LF008A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF004C, 512 KB probe_49lfxxxc: id1 0xb8, id2 0x32 Probing for SST49LF008C, 1024 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF016C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF160C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for Pm49FL002, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for Pm49FL004, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for W29C011, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for W29C020C, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for W49F002U, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for W49V002A, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for W49V002FA, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for W39V040FA, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for W39V040A, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for W39V040B, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for W39V080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F002B, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for M50FW040, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for M29W040B, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for M29F002T/NT, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for M29F400BT, 512 KB probe_m29f400bt: id1 0xb8, id2 0x0 Probing for M50FLW040A, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for M50FLW040B, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for M50FLW080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FLW080B, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW080, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW016, 2048 KB probe_jedec: id1 0xff, id2 0xff Probing for M50LPW116, 2048 KB probe_jedec: id1 0xff, id2 0xff Probing for M29W010B, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F040B, 512 KB probe_29f040b: id1 0xb8, id2 0x32 Probing for 82802ab, 512 KB probe_82802ab: id1 0xb8, id2 0x32 Probing for 82802ac, 1024 KB probe_82802ab: id1 0xff, id2 0xff Probing for F49B002UA, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for LHF00L04, 1024 KB probe_lhf00l04: id1 0xff, id2 0xff Probing for S29C51001T, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for S29C51002T, 256 KB probe_jedec: id1 0x34, id2 0x6d Probing for S29C51004T, 512 KB probe_jedec: id1 0xb8, id2 0x32 Probing for S29C31004T, 512 KB probe_jedec: id1 0xb8, id2 0x32 No EEPROM/flash device found. 00:00.0 Class 0600: 8086:27a0 (rev 03) Subsystem: 1028:01cc Flags: bus master, fast devsel, latency 0 Capabilities: [e0] Vendor Specific Information 00:02.0 Class 0300: 8086:27a2 (rev 03) (prog-if 00 [VGA]) Subsystem: 1028:01cc Flags: bus master, fast devsel, latency 0, IRQ 16 Memory at eff00000 (32-bit, non-prefetchable) [size=512K] I/O ports at eff8 [size=8] Memory at d0000000 (32-bit, prefetchable) [size=256M] Memory at efec0000 (32-bit, non-prefetchable) [size=256K] Capabilities: [90] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable- Capabilities: [d0] Power Management version 2 00:02.1 Class 0380: 8086:27a6 (rev 03) Subsystem: 1028:01cc Flags: bus master, fast devsel, latency 0 Memory at eff80000 (32-bit, non-prefetchable) [size=512K] Capabilities: [d0] Power Management version 2 00:1b.0 Class 0403: 8086:27d8 (rev 01) Subsystem: 1028:01cc Flags: bus master, fast devsel, latency 0, IRQ 20 Memory at efebc000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Capabilities: [60] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Capabilities: [70] Express Unknown type IRQ 0 Capabilities: [100] Virtual Channel Capabilities: [130] Unknown (5) 00:1c.0 Class 0604: 8086:27d0 (rev 01) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 Capabilities: [40] Express Root Port (Slot+) IRQ 0 Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Capabilities: [90] Subsystem: 1028:01cc Capabilities: [a0] Power Management version 2 Capabilities: [100] Virtual Channel Capabilities: [180] Unknown (5) 00:1c.1 Class 0604: 8086:27d2 (rev 01) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 Memory behind bridge: efd00000-efdfffff Capabilities: [40] Express Root Port (Slot+) IRQ 0 Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Capabilities: [90] Subsystem: 1028:01cc Capabilities: [a0] Power Management version 2 Capabilities: [100] Virtual Channel Capabilities: [180] Unknown (5) 00:1c.2 Class 0604: 8086:27d4 (rev 01) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 Memory behind bridge: efc00000-efcfffff Capabilities: [40] Express Root Port (Slot+) IRQ 0 Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Capabilities: [90] Subsystem: 1028:01cc Capabilities: [a0] Power Management version 2 Capabilities: [100] Virtual Channel Capabilities: [180] Unknown (5) 00:1c.3 Class 0604: 8086:27d6 (rev 01) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: efa00000-efbfffff Prefetchable memory behind bridge: 00000000e0000000-00000000e01fffff Capabilities: [40] Express Root Port (Slot+) IRQ 0 Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Queue=0/0 Enable+ Capabilities: [90] Subsystem: 1028:01cc Capabilities: [a0] Power Management version 2 Capabilities: [100] Virtual Channel Capabilities: [180] Unknown (5) 00:1d.0 Class 0c03: 8086:27c8 (rev 01) (prog-if 00 [UHCI]) Subsystem: 1028:01cc Flags: bus master, medium devsel, latency 0, IRQ 21 I/O ports at bf80 [size=32] 00:1d.1 Class 0c03: 8086:27c9 (rev 01) (prog-if 00 [UHCI]) Subsystem: 1028:01cc Flags: bus master, medium devsel, latency 0, IRQ 20 I/O ports at bf60 [size=32] 00:1d.2 Class 0c03: 8086:27ca (rev 01) (prog-if 00 [UHCI]) Subsystem: 1028:01cc Flags: bus master, medium devsel, latency 0, IRQ 22 I/O ports at bf40 [size=32] 00:1d.3 Class 0c03: 8086:27cb (rev 01) (prog-if 00 [UHCI]) Subsystem: 1028:01cc Flags: bus master, medium devsel, latency 0, IRQ 23 I/O ports at bf20 [size=32] 00:1d.7 Class 0c03: 8086:27cc (rev 01) (prog-if 20 [EHCI]) Subsystem: 1028:01cc Flags: bus master, medium devsel, latency 0, IRQ 21 Memory at ffa80000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Capabilities: [58] Debug port 00:1e.0 Class 0604: 8086:2448 (rev e1) (prog-if 01 [Subtractive decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=05, subordinate=09, sec-latency=32 I/O behind bridge: 00002000-00002fff Memory behind bridge: ef900000-ef9fffff Prefetchable memory behind bridge: 0000000050000000-0000000053ffffff Capabilities: [50] Subsystem: 1028:01cc 00:1f.0 Class 0601: 8086:27b9 (rev 01) Subsystem: 1028:01cc Flags: bus master, medium devsel, latency 0 Capabilities: [e0] Vendor Specific Information 00:1f.2 Class 0101: 8086:27c4 (rev 01) (prog-if 80 [Master]) Subsystem: 1028:01cc Flags: bus master, 66MHz, medium devsel, latency 0, IRQ 17 I/O ports at 01f0 [size=8] I/O ports at 03f4 [size=1] I/O ports at 0170 [size=8] I/O ports at 0374 [size=1] I/O ports at bfa0 [size=16] Capabilities: [70] Power Management version 2 00:1f.3 Class 0c05: 8086:27da (rev 01) Subsystem: 1028:01cc Flags: medium devsel, IRQ 17 I/O ports at 10c0 [size=32] 02:00.0 Class 0280: 8086:4222 (rev 02) Subsystem: 8086:1021 Flags: bus master, fast devsel, latency 0, IRQ 17 Memory at efdff000 (32-bit, non-prefetchable) [size=4K] Capabilities: [c8] Power Management version 2 Capabilities: [d0] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Capabilities: [e0] Express Legacy Endpoint IRQ 0 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number d2-af-9c-ff-ff-de-18-00 03:00.0 Class 0200: 14e4:1600 (rev 02) Subsystem: 1028:01cc Flags: bus master, fast devsel, latency 0, IRQ 219 Memory at efcf0000 (64-bit, non-prefetchable) [size=64K] Capabilities: [48] Power Management version 2 Capabilities: [50] Vital Product Data Capabilities: [58] Message Signalled Interrupts: Mask- 64bit+ Queue=0/3 Enable+ Capabilities: [d0] Express Endpoint IRQ 0 Capabilities: [100] Advanced Error Reporting Capabilities: [13c] Virtual Channel 05:01.0 Class 0607: 1217:7135 (rev 21) Subsystem: 1028:01cc Flags: bus master, stepping, slow devsel, latency 168, IRQ 19 Memory at ef900000 (32-bit, non-prefetchable) [size=4K] Bus: primary=05, secondary=06, subordinate=09, sec-latency=176 Memory window 0: 50000000-53fff000 (prefetchable) Memory window 1: 54000000-57fff000 I/O window 0: 00002000-000020ff I/O window 1: 00002400-000024ff 16-bit legacy interface ports at 0001 05:01.4 Class 0c00: 1217:00f7 (rev 02) (prog-if 10 [OHCI]) Subsystem: 1028:01cc Flags: bus master, medium devsel, latency 64, IRQ 19 Memory at ef9ff000 (32-bit, non-prefetchable) [size=4K] Memory at ef9fe800 (32-bit, non-prefetchable) [size=2K] Capabilities: [60] Power Management version 2

2 1

[LinuxBIOS] [PATCH] [notready] my current v3 diff
by Carl-Daniel Hailfinger 27 Aug '07

27 Aug '07

Hi, attached (because of whitespace issues, same content as quoted text inline) is my current diff to upstream sources. Some cosmetic stuff, some comments to self, maybe even downright senseless changes. A short review would be appreciated so I can send real patches. Regards, Carl-Daniel > Index: include/device/device.h > =================================================================== > --- include/device/device.h (Revision 476) > +++ include/device/device.h (Arbeitskopie) > @@ -202,7 +202,7 @@ > struct resource resource[MAX_RESOURCES]; > unsigned int resources; > > - /* link are (down sream) buses attached to the device, usually a leaf > + /* link are (downstream) buses attached to the device, usually a leaf > * device with no children have 0 buses attached and a bridge has 1 bus > */ > struct bus link[MAX_LINKS]; > Index: mainboard/adl/msm800sev/stage1.c > =================================================================== > --- mainboard/adl/msm800sev/stage1.c (Revision 476) > +++ mainboard/adl/msm800sev/stage1.c (Arbeitskopie) > @@ -33,7 +33,9 @@ > #include <southbridge/amd/cs5536/cs5536.h> > #include <superio/winbond/w83627hf/w83627hf.h> > > +/* This is wrong! SERIAL_DEV can't be >=0x10 because it's a PNP device number */ > #define SERIAL_DEV 0x30 > +#define SERIAL_IOBASE 0x3f8 > > void hardware_stage1(void) > { > @@ -49,6 +51,6 @@ > * for cs5536 > */ > cs5536_disable_internal_uart(); > - w83627hf_enable_serial(0x2e, 0x30, 0x3f8); > + w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); > printk(BIOS_DEBUG, "Done %s\n", __FUNCTION__); > } > Index: device/device.c > =================================================================== > --- device/device.c (Revision 476) > +++ device/device.c (Arbeitskopie) > @@ -260,8 +260,10 @@ > for (curdev = bus->children; curdev; curdev = curdev->sibling) { > unsigned int links; > int i; > - printk(BIOS_SPEW, "%s: %s(%s) have_resources %d enabled %d\n", > + printk(BIOS_SPEW, > + "%s: %s(%s) dtsname %s have_resources %d enabled %d\n", > __func__, bus->dev->dtsname, dev_path(bus->dev), > + curdev->dtsname, > curdev->have_resources, curdev->enabled); > if (curdev->have_resources) { > continue; > @@ -402,7 +404,11 @@ > min_align = 0; > base = bridge->base; > > - printk(BIOS_SPEW, "%s compute_allocate_%s: base: %08Lx size: %08Lx align: %d gran: %d\n", dev_path(bus->dev), (bridge->flags & IORESOURCE_IO) ? "io" : (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", base, bridge->size, bridge->align, bridge->gran); > + printk(BIOS_SPEW, > + "%s compute_allocate_%s: base: %08llx size: %08llx align: %d gran: %d\n", > + dev_path(bus->dev), > + (bridge->flags & IORESOURCE_IO) ? "io" : (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", > + base, bridge->size, bridge->align, bridge->gran); > > /* We want different minimum alignments for different kinds of > * resources. These minimums are not device type specific but > @@ -485,7 +491,7 @@ > base += size; > > printk(BIOS_SPEW, > - "%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", > + "%s %02lx * [0x%08llx - 0x%08llx] %s\n", > dev_path(dev), > resource->index, > resource->base, > @@ -503,7 +509,11 @@ > */ > bridge->size = align_up(base, bridge->gran) - bridge->base; > > - printk(BIOS_SPEW, "%s compute_allocate_%s: base: %08Lx size: %08Lx align: %d gran: %d done\n", dev_path(bus->dev), (bridge->flags & IORESOURCE_IO) ? "io" : (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", base, bridge->size, bridge->align, bridge->gran); > + printk(BIOS_SPEW, > + "%s compute_allocate_%s: base: %08llx size: %08llx align: %d gran: %d done\n", > + dev_path(bus->dev), > + (bridge->flags & IORESOURCE_IO) ? "io" : (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", > + base, bridge->size, bridge->align, bridge->gran); > } > > #if defined(CONFIG_PCI_OPTION_ROM_RUN) && CONFIG_PCI_OPTION_ROM_RUN == 1 > Index: device/pnp_device.c > =================================================================== > --- device/pnp_device.c (Revision 476) > +++ device/pnp_device.c (Arbeitskopie) > @@ -87,7 +87,7 @@ > { > if (!(resource->flags & IORESOURCE_ASSIGNED)) { > printk(BIOS_ERR, > - "ERROR: %s %02lx %s size: 0x%010Lx not assigned\n", > + "ERROR: %s %02lx %s size: 0x%010llx not assigned\n", > dev_path(dev), resource->index, resource_type(resource), > resource->size); > return; > Index: device/pci_device.c > =================================================================== > --- device/pci_device.c (Revision 476) > +++ device/pci_device.c (Arbeitskopie) > @@ -252,10 +252,10 @@ > printk(BIOS_DEBUG, "%s %02x ->", > dev_path(dev), resource->index); > printk(BIOS_DEBUG, > - " value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n", > + " value: 0x%08llx zeroes: 0x%08llx ones: 0x%08llx attr: %08lx\n", > value, zeroes, ones, attr); > printk(BIOS_DEBUG, > - "%s %02x -> size: 0x%08Lx max: 0x%08Lx %s\n ", > + "%s %02x -> size: 0x%08llx max: 0x%08llx %s\n ", > dev_path(dev), resource->index, resource->size, > resource->limit, resource_type(resource)); > } > @@ -456,7 +456,7 @@ > /* Make certain the resource has actually been set. */ > if (!(resource->flags & IORESOURCE_ASSIGNED)) { > printk(BIOS_ERR, > - "ERROR: %s %02lx %s size: 0x%010Lx not assigned\n", > + "ERROR: %s %02lx %s size: 0x%010llx not assigned\n", > dev_path(dev), resource->index, resource_type(resource), > resource->size); > return; > @@ -863,7 +863,7 @@ > (*list)->path.type); > continue; > } > - printk(BIOS_SPEW, "%s: check dev %s it has devfn 0x%x\n", > + printk(BIOS_SPEW, "%s: check dev %s it has devfn 0x%02x\n", > __func__, (*list)->dtsname, (*list)->path.u.pci.devfn); > if ((*list)->path.u.pci.devfn == devfn) { > /* Unlink from the list. */ > Index: device/device_util.c > =================================================================== > --- device/device_util.c (Revision 476) > +++ device/device_util.c (Arbeitskopie) > @@ -229,7 +229,7 @@ > memcpy(buffer, "Root Device", 12); > break; > case DEVICE_ID_PCI: > - sprintf(buffer, "PCI: %02x:%02x", id->u.pci.vendor, > + sprintf(buffer, "PCI: %04x:%04x", id->u.pci.vendor, > id->u.pci.device); > break; > case DEVICE_ID_PNP: > @@ -243,7 +243,7 @@ > id->u.apic.device); > break; > case DEVICE_ID_PCI_DOMAIN: > - sprintf(buffer, "PCI_DOMAIN: %02x:%02x", > + sprintf(buffer, "PCI_DOMAIN: %04x:%04x", > id->u.pci_domain.vendor, > id->u.pci_domain.device); > break; > @@ -602,7 +602,7 @@ > #endif > } > printk(BIOS_DEBUG, > - "%s %02lx <- [0x%010Lx - 0x%010Lx] %s%s%s\n", > + "%s %02lx <- [0x%010llx - 0x%010llx] %s%s%s\n", > dev_path(dev), > resource->index, > base, end, buf, resource_type(resource), comment); > @@ -656,7 +656,7 @@ > for (i = 0; i < curdev->resources; i++) { > struct resource *resource = &curdev->resource[i]; > printk(BIOS_SPEW, > - "%s: dev %s, resource %d, flags %lx base 0x%Lx size 0x%Lx\n", > + "%s: dev %s, resource %d, flags %lx base 0x%llx size 0x%llx\n", > __func__, curdev->dtsname, i, resource->flags, > resource->base, resource->size); > /* If it isn't the right kind of resource ignore it. */ > Index: lib/stage2.c > =================================================================== > --- lib/stage2.c (Revision 476) > +++ lib/stage2.c (Arbeitskopie) > @@ -31,8 +31,9 @@ > /** > * Main function of the DRAM part of LinuxBIOS. > * > - * LinuxBIOS is divided into pre-DRAM part and DRAM part. The phases before > - * this part are phase 0 and phase 1. This part contains phases x through y. > + * LinuxBIOS is divided into pre-DRAM part and DRAM part. The stages before > + * this part are stage 0 and stage 1. This part contains stage 2, which > + * consists of phases 1 through 6. > * > * Device Enumeration: in the dev_enumerate() phase. > * > @@ -53,6 +54,7 @@ > > post_code(0x20); > > + /* TODO: Explain why we use printk here although it is impossible */ > printk(BIOS_NOTICE, console_test); > > dev_init(); > Index: lib/elfboot.c > =================================================================== > --- lib/elfboot.c (Revision 476) > +++ lib/elfboot.c (Arbeitskopie) > @@ -61,7 +61,7 @@ > } > if (i == mem_entries) { > printk(BIOS_ERR, "No matching RAM area found for range:\n"); > - printk(BIOS_ERR, " [0x%016Lx, 0x%016Lx)\n", start, end); > + printk(BIOS_ERR, " [0x%016llx, 0x%016llx)\n", start, end); > printk(BIOS_ERR, "RAM areas\n"); > for(i = 0; i < mem_entries; i++) { > u64 mstart, mend; > @@ -69,7 +69,7 @@ > mtype = mem->map[i].type; > mstart = unpack_lb64(mem->map[i].start); > mend = mstart + unpack_lb64(mem->map[i].size); > - printk(BIOS_ERR, " [0x%016Lx, 0x%016Lx) %s\n", > + printk(BIOS_ERR, " [0x%016llx, 0x%016llx) %s\n", > mstart, mend, (mtype == LB_MEM_RAM)?"RAM":"Reserved"); > > } > Index: northbridge/intel/i440bxemulation/i440bx.c > =================================================================== > --- northbridge/intel/i440bxemulation/i440bx.c (Revision 476) > +++ northbridge/intel/i440bxemulation/i440bx.c (Arbeitskopie) > @@ -79,7 +79,7 @@ > resource->size = ((resource_t) sizek) << 10; > resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | > IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; > - printk(BIOS_DEBUG, "%s: add ram resoource %Ld bytes\n", __func__, > + printk(BIOS_DEBUG, "%s: add ram resource %lld bytes\n", __func__, > resource->size); > } > > Index: arch/x86/linuxbios_table.c > =================================================================== > --- arch/x86/linuxbios_table.c (Revision 476) > +++ arch/x86/linuxbios_table.c (Arbeitskopie) > @@ -177,7 +177,7 @@ > { > int entries; > > - printk(BIOS_DEBUG, "%s: start 0x%Lx size 0x%Lx\n", > + printk(BIOS_DEBUG, "%s: start 0x%llx size 0x%llx\n", > __func__, start, size); > > entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); > Index: arch/x86/pci_ops_mmconf.c > =================================================================== > --- arch/x86/pci_ops_mmconf.c (Revision 476) > +++ arch/x86/pci_ops_mmconf.c (Arbeitskopie) > @@ -18,32 +18,32 @@ > > #include <mmio_conf.h> > > -static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, int where) > +static u8 pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, int where) > { > return (read8x(PCI_MMIO_ADDR(bus, devfn, where))); > } > > -static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, int where) > +static u16 pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, int where) > { > return (read16x(PCI_MMIO_ADDR(bus, devfn, where))); > } > > -static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, int where) > +static u32 pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, int where) > { > return (read32x(PCI_MMIO_ADDR(bus, devfn, where))); > } > > -static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) > +static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int where, u8 value) > { > write8x(PCI_MMIO_ADDR(bus, devfn, where), value); > } > > -static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) > +static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, int where, u16 value) > { > write8x(PCI_MMIO_ADDR(bus, devfn, where), value); > } > > -static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) > +static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, int where, u32 value) > { > write8x(PCI_MMIO_ADDR(bus, devfn, where), value); > } Index: include/device/device.h =================================================================== --- include/device/device.h (Revision 476) +++ include/device/device.h (Arbeitskopie) @@ -202,7 +202,7 @@ struct resource resource[MAX_RESOURCES]; unsigned int resources; - /* link are (down sream) buses attached to the device, usually a leaf + /* link are (downstream) buses attached to the device, usually a leaf * device with no children have 0 buses attached and a bridge has 1 bus */ struct bus link[MAX_LINKS]; Index: mainboard/adl/msm800sev/stage1.c =================================================================== --- mainboard/adl/msm800sev/stage1.c (Revision 476) +++ mainboard/adl/msm800sev/stage1.c (Arbeitskopie) @@ -33,7 +33,9 @@ #include <southbridge/amd/cs5536/cs5536.h> #include <superio/winbond/w83627hf/w83627hf.h> +/* This is wrong! SERIAL_DEV can't be >=0x10 because it's a PNP device number */ #define SERIAL_DEV 0x30 +#define SERIAL_IOBASE 0x3f8 void hardware_stage1(void) { @@ -49,6 +51,6 @@ * for cs5536 */ cs5536_disable_internal_uart(); - w83627hf_enable_serial(0x2e, 0x30, 0x3f8); + w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); printk(BIOS_DEBUG, "Done %s\n", __FUNCTION__); } Index: device/device.c =================================================================== --- device/device.c (Revision 476) +++ device/device.c (Arbeitskopie) @@ -260,8 +260,10 @@ for (curdev = bus->children; curdev; curdev = curdev->sibling) { unsigned int links; int i; - printk(BIOS_SPEW, "%s: %s(%s) have_resources %d enabled %d\n", + printk(BIOS_SPEW, + "%s: %s(%s) dtsname %s have_resources %d enabled %d\n", __func__, bus->dev->dtsname, dev_path(bus->dev), + curdev->dtsname, curdev->have_resources, curdev->enabled); if (curdev->have_resources) { continue; @@ -402,7 +404,11 @@ min_align = 0; base = bridge->base; - printk(BIOS_SPEW, "%s compute_allocate_%s: base: %08Lx size: %08Lx align: %d gran: %d\n", dev_path(bus->dev), (bridge->flags & IORESOURCE_IO) ? "io" : (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", base, bridge->size, bridge->align, bridge->gran); + printk(BIOS_SPEW, + "%s compute_allocate_%s: base: %08llx size: %08llx align: %d gran: %d\n", + dev_path(bus->dev), + (bridge->flags & IORESOURCE_IO) ? "io" : (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", + base, bridge->size, bridge->align, bridge->gran); /* We want different minimum alignments for different kinds of * resources. These minimums are not device type specific but @@ -485,7 +491,7 @@ base += size; printk(BIOS_SPEW, - "%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", + "%s %02lx * [0x%08llx - 0x%08llx] %s\n", dev_path(dev), resource->index, resource->base, @@ -503,7 +509,11 @@ */ bridge->size = align_up(base, bridge->gran) - bridge->base; - printk(BIOS_SPEW, "%s compute_allocate_%s: base: %08Lx size: %08Lx align: %d gran: %d done\n", dev_path(bus->dev), (bridge->flags & IORESOURCE_IO) ? "io" : (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", base, bridge->size, bridge->align, bridge->gran); + printk(BIOS_SPEW, + "%s compute_allocate_%s: base: %08llx size: %08llx align: %d gran: %d done\n", + dev_path(bus->dev), + (bridge->flags & IORESOURCE_IO) ? "io" : (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", + base, bridge->size, bridge->align, bridge->gran); } #if defined(CONFIG_PCI_OPTION_ROM_RUN) && CONFIG_PCI_OPTION_ROM_RUN == 1 Index: device/pnp_device.c =================================================================== --- device/pnp_device.c (Revision 476) +++ device/pnp_device.c (Arbeitskopie) @@ -87,7 +87,7 @@ { if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, - "ERROR: %s %02lx %s size: 0x%010Lx not assigned\n", + "ERROR: %s %02lx %s size: 0x%010llx not assigned\n", dev_path(dev), resource->index, resource_type(resource), resource->size); return; Index: device/pci_device.c =================================================================== --- device/pci_device.c (Revision 476) +++ device/pci_device.c (Arbeitskopie) @@ -252,10 +252,10 @@ printk(BIOS_DEBUG, "%s %02x ->", dev_path(dev), resource->index); printk(BIOS_DEBUG, - " value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n", + " value: 0x%08llx zeroes: 0x%08llx ones: 0x%08llx attr: %08lx\n", value, zeroes, ones, attr); printk(BIOS_DEBUG, - "%s %02x -> size: 0x%08Lx max: 0x%08Lx %s\n ", + "%s %02x -> size: 0x%08llx max: 0x%08llx %s\n ", dev_path(dev), resource->index, resource->size, resource->limit, resource_type(resource)); } @@ -456,7 +456,7 @@ /* Make certain the resource has actually been set. */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, - "ERROR: %s %02lx %s size: 0x%010Lx not assigned\n", + "ERROR: %s %02lx %s size: 0x%010llx not assigned\n", dev_path(dev), resource->index, resource_type(resource), resource->size); return; @@ -863,7 +863,7 @@ (*list)->path.type); continue; } - printk(BIOS_SPEW, "%s: check dev %s it has devfn 0x%x\n", + printk(BIOS_SPEW, "%s: check dev %s it has devfn 0x%02x\n", __func__, (*list)->dtsname, (*list)->path.u.pci.devfn); if ((*list)->path.u.pci.devfn == devfn) { /* Unlink from the list. */ Index: device/device_util.c =================================================================== --- device/device_util.c (Revision 476) +++ device/device_util.c (Arbeitskopie) @@ -229,7 +229,7 @@ memcpy(buffer, "Root Device", 12); break; case DEVICE_ID_PCI: - sprintf(buffer, "PCI: %02x:%02x", id->u.pci.vendor, + sprintf(buffer, "PCI: %04x:%04x", id->u.pci.vendor, id->u.pci.device); break; case DEVICE_ID_PNP: @@ -243,7 +243,7 @@ id->u.apic.device); break; case DEVICE_ID_PCI_DOMAIN: - sprintf(buffer, "PCI_DOMAIN: %02x:%02x", + sprintf(buffer, "PCI_DOMAIN: %04x:%04x", id->u.pci_domain.vendor, id->u.pci_domain.device); break; @@ -602,7 +602,7 @@ #endif } printk(BIOS_DEBUG, - "%s %02lx <- [0x%010Lx - 0x%010Lx] %s%s%s\n", + "%s %02lx <- [0x%010llx - 0x%010llx] %s%s%s\n", dev_path(dev), resource->index, base, end, buf, resource_type(resource), comment); @@ -656,7 +656,7 @@ for (i = 0; i < curdev->resources; i++) { struct resource *resource = &curdev->resource[i]; printk(BIOS_SPEW, - "%s: dev %s, resource %d, flags %lx base 0x%Lx size 0x%Lx\n", + "%s: dev %s, resource %d, flags %lx base 0x%llx size 0x%llx\n", __func__, curdev->dtsname, i, resource->flags, resource->base, resource->size); /* If it isn't the right kind of resource ignore it. */ Index: lib/stage2.c =================================================================== --- lib/stage2.c (Revision 476) +++ lib/stage2.c (Arbeitskopie) @@ -31,8 +31,9 @@ /** * Main function of the DRAM part of LinuxBIOS. * - * LinuxBIOS is divided into pre-DRAM part and DRAM part. The phases before - * this part are phase 0 and phase 1. This part contains phases x through y. + * LinuxBIOS is divided into pre-DRAM part and DRAM part. The stages before + * this part are stage 0 and stage 1. This part contains stage 2, which + * consists of phases 1 through 6. * * Device Enumeration: in the dev_enumerate() phase. * @@ -53,6 +54,7 @@ post_code(0x20); + /* TODO: Explain why we use printk here although it is impossible */ printk(BIOS_NOTICE, console_test); dev_init(); Index: lib/elfboot.c =================================================================== --- lib/elfboot.c (Revision 476) +++ lib/elfboot.c (Arbeitskopie) @@ -61,7 +61,7 @@ } if (i == mem_entries) { printk(BIOS_ERR, "No matching RAM area found for range:\n"); - printk(BIOS_ERR, " [0x%016Lx, 0x%016Lx)\n", start, end); + printk(BIOS_ERR, " [0x%016llx, 0x%016llx)\n", start, end); printk(BIOS_ERR, "RAM areas\n"); for(i = 0; i < mem_entries; i++) { u64 mstart, mend; @@ -69,7 +69,7 @@ mtype = mem->map[i].type; mstart = unpack_lb64(mem->map[i].start); mend = mstart + unpack_lb64(mem->map[i].size); - printk(BIOS_ERR, " [0x%016Lx, 0x%016Lx) %s\n", + printk(BIOS_ERR, " [0x%016llx, 0x%016llx) %s\n", mstart, mend, (mtype == LB_MEM_RAM)?"RAM":"Reserved"); } Index: northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- northbridge/intel/i440bxemulation/i440bx.c (Revision 476) +++ northbridge/intel/i440bxemulation/i440bx.c (Arbeitskopie) @@ -79,7 +79,7 @@ resource->size = ((resource_t) sizek) << 10; resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "%s: add ram resoource %Ld bytes\n", __func__, + printk(BIOS_DEBUG, "%s: add ram resource %lld bytes\n", __func__, resource->size); } Index: arch/x86/linuxbios_table.c =================================================================== --- arch/x86/linuxbios_table.c (Revision 476) +++ arch/x86/linuxbios_table.c (Arbeitskopie) @@ -177,7 +177,7 @@ { int entries; - printk(BIOS_DEBUG, "%s: start 0x%Lx size 0x%Lx\n", + printk(BIOS_DEBUG, "%s: start 0x%llx size 0x%llx\n", __func__, start, size); entries = (mem->size - sizeof(*mem))/sizeof(mem->map[0]); Index: arch/x86/pci_ops_mmconf.c =================================================================== --- arch/x86/pci_ops_mmconf.c (Revision 476) +++ arch/x86/pci_ops_mmconf.c (Arbeitskopie) @@ -18,32 +18,32 @@ #include <mmio_conf.h> -static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, int where) +static u8 pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, int where) { return (read8x(PCI_MMIO_ADDR(bus, devfn, where))); } -static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, int where) +static u16 pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, int where) { return (read16x(PCI_MMIO_ADDR(bus, devfn, where))); } -static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, int where) +static u32 pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, int where) { return (read32x(PCI_MMIO_ADDR(bus, devfn, where))); } -static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) +static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int where, u8 value) { write8x(PCI_MMIO_ADDR(bus, devfn, where), value); } -static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) +static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, int where, u16 value) { write8x(PCI_MMIO_ADDR(bus, devfn, where), value); } -static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) +static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, int where, u32 value) { write8x(PCI_MMIO_ADDR(bus, devfn, where), value); }

3 3

[LinuxBIOS] [PATCH] probe_superio: rewrite, add ITE support, sophisticated dumping
by Carl-Daniel Hailfinger 27 Aug '07

27 Aug '07

This patch rewrites probe_superio almost completely. Common code sequences have been factored out, the code has been made more generic, has better handling of corner cases and is actually much shorter. It also adds probing for almost all recent (since 1999) ITE Super I/O chips to probe_superio. I did verify against all ITE datasheets (including those not available any more) that the probing was non-destructive. For the ITE IT8712F, the complete configuration is dumped and as comparison the default value from the data sheet is printed. More information can be extracted easily, however this needs loads of datasheet surfing. This code has been tested extensively, dumping for other ITE chips will follow as a separate patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- LinuxBIOSv2/util/probe_superio/probe_superio.c (Revision 2748) +++ LinuxBIOSv2/util/probe_superio/probe_superio.c (Arbeitskopie) @@ -3,6 +3,7 @@ * * Copyright (C) 2006 Ronald Minnich <rminnich(a)gmail.com> * Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de> + * Copyright (C) 2007 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,11 +33,16 @@ * if we need this. */ -unsigned char regval(unsigned short port, unsigned short reg) { +unsigned char regval(unsigned short port, unsigned char reg) { outb(reg, port); return inb(port+1); } +void regwrite(unsigned short port, unsigned char reg, unsigned char val) { + outb(reg, port); + outb(val, port+1); +} + void dump_ns8374(unsigned short port) { printf("Enables: 21=%02x, 22=%02x, 23=%02x, 24=%02x, 26=%02x\n", @@ -46,15 +52,13 @@ /* check COM1. This is all we care about at present. */ printf("COM 1 is Globally %s\n", regval(port,0x26)&8 ? "disabled" : "enabled"); /* select com1 */ - outb(0x7, port); - outb(3, port+1); + regwrite(port, 0x07, 0x03); printf("COM 1 is locally %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("COM1 60=%02x, 61=%02x, 70=%02x, 71=%02x, 74=%02x, 75=%02x, f0=%02x\n", regval(port, 0x60), regval(port, 0x61), regval(port, 0x70), regval(port, 0x71), regval(port, 0x74), regval(port, 0x75), regval(port, 0xf0)); /* select gpio */ - outb(0x7, port); - outb(7, port+1); + regwrite(port, 0x07, 0x07); printf("GPIO is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("GPIO 60=%02x, 61=%02x, 70=%02x, 71=%02x, 74=%02x, 75=%02x, f0=%02x\n", regval(port, 0x60), regval(port, 0x61), regval(port, 0x70), regval(port, 0x71), @@ -85,38 +89,33 @@ printf("2b=%02x\n", regval(port, 0x2b)); /* select UART 1 */ - outb(0x07, port); - outb(0x01, port+1); + regwrite(port, 0x07, 0x01); printf("UART1 is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("UART1 base=%02x%02x, irq=%02x, mode=%s\n", regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f, regval(port, 0xf0)&0x10 ? "RS485":"RS232"); /* select UART 2 */ - outb(0x07, port); - outb(0x02, port+1); + regwrite(port, 0x07, 0x02); printf("UART2 is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("UART2 base=%02x%02x, irq=%02x, mode=%s\n", regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f, regval(port, 0xf0)&0x10 ? "RS485":"RS232"); /* select Parport */ - outb(0x07, port); - outb(0x03, port+1); + regwrite(port, 0x07, 0x03); printf("PARPORT is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("PARPORT base=%02x%02x, irq=%02x\n", regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f); /* select hw monitor */ - outb(0x07, port); - outb(0x04, port+1); + regwrite(port, 0x07, 0x04); printf("HW monitor is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("HW monitor base=%02x%02x, irq=%02x\n", regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f); /* select gpio */ - outb(0x07, port); - outb(0x06, port+1); + regwrite(port, 0x07, 0x05); printf("GPIO is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("GPIO 70=%02x, e0=%02x, e1=%02x, e2=%02x, e3=%02x, e4=%02x, e5=%02x\n", regval(port, 0x70), regval(port, 0xe0), regval(port, 0xe1), regval(port, 0xe2), @@ -130,8 +129,152 @@ } +//End Of Table +#define EOT -1 +//NO LDN needed +#define NOLDN -2 +//Not Available +#define NANA -3 +//Biggest LDN +#define MAXLDN 0xa +//MAXimum NUMber of Indexes +#define MAXNUMIDX 70 +const static struct ite_registers { + signed short superio_id; //yes, it should be unsigned, but then EOT has to be positive + struct ite_ldnidx { + signed short ldn; + signed short idx[MAXNUMIDX+1]; + signed short def[MAXNUMIDX+1]; + } ldn[MAXLDN+3]; //biggestLDN+0+NOLDN+EOT +} ite_reg_table[] = { + {0x8712,{ + {NOLDN, + {0x07,0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, + {NANA,0x87,0x12,0x08,0x00,0x00,0x00,EOT}}, + {0x0, + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x00,0x00,EOT}}, + {0x1, + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x03,0xf8,0x04,0x00,0x50,0x00,0x7f,EOT}}, + {0x2, + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x02,0xf8,0x03,0x00,0x50,0x00,0x7f,EOT}}, + {0x3, + {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,EOT}, + {0x00,0x03,0x78,0x07,0x78,0x07,0x03,0x03,EOT}}, + {0x4, + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,EOT}, + {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00,0x00,0x00,NANA,NANA,EOT}}, + {0x5, + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x00,EOT}}, + {0x6, + {0x30,0x70,0x71,0xf0,EOT}, + {0x00,0x0c,0x02,0x00,EOT}}, + {0x7, + {0x25,0x26,0x27,0x28,0x29,0x2a,0x2c,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0x72,0x73,0x74,0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xc0,0xc1,0xc2,0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,EOT}, + {0x01,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,0x00,EOT}}, + {0x8, + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0x00,0x0a,0x00,EOT}}, + {0x9, + {0x30,0x60,0x61,EOT}, + {0x00,0x02,0x01,EOT}}, + {0xa, + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0x10,0x0b,0x00,EOT}}, + {EOT}}}, + {EOT} +}; void +dump_ite(unsigned short port, unsigned short id) +{ + int i, j, k; + signed short *idx; + printf ("ITE "); + + + /* ID Mapping Table + unknown -> IT8711 (no datasheet) + unknown -> IT8722 (no datasheet) + 0x8702 -> IT8702 + 0x8705 -> IT8700 or IT8705 + 0x8708 -> IT8708 + 0x8710 -> IT8710 + 0x8712 -> IT8712 + 0x8716 -> IT8716 or IT8726 (identical except CPU voltage control) + 0x8718 -> IT8718 + 0x8726 does not exist according to datasheet, but experience differs + */ + switch(id) { + case 0x8702: + printf ("IT8702\n"); + break; + case 0x8705: + printf ("IT8700 or IT8705\n"); + break; + case 0x8710: + printf ("IT8710\n"); + break; + case 0x8712: + printf ("IT8712\n"); + for (i=0;; i++) { + if (ite_reg_table[i].superio_id == EOT) + break; + if ((unsigned short)ite_reg_table[i].superio_id != id) + continue; + for (j=0;; j++) { + if (ite_reg_table[i].ldn[j].ldn == EOT) + break; + if (ite_reg_table[i].ldn[j].ldn != NOLDN) { + printf("switching to LDN 0x%01x\n", ite_reg_table[i].ldn[j].ldn); + regwrite(port, 0x07, ite_reg_table[i].ldn[j].ldn); + } + idx = ite_reg_table[i].ldn[j].idx; + printf("idx "); + for (k=0;; k++) { + if (idx[k] == EOT) + break; + printf("%02x ", idx[k]); + } + printf("\nval "); + for (k=0;; k++) { + if (idx[k] == EOT) + break; + printf("%02x ", regval(port, idx[k])); + } + printf("\ndef "); + idx = ite_reg_table[i].ldn[j].def; + for (k=0;; k++) { + if (idx[k] == EOT) + break; + if (idx[k] == NANA) + printf("NA "); + else + printf("%02x ", idx[k]); + } + printf("\n"); + } + + } + break; + case 0x8716: + printf ("IT8716 or IT8726\n"); + break; + case 0x8718: + printf ("IT8718\n"); + break; + default: + printf ("unknown ITE chip, id=%04x\n", id); + for (i=0x20; i<=0x24; i++) + printf("index %02x=%02x\n", i, regval(port, i)); + break; + } +} + +void probe_idregs_simple(unsigned short port){ unsigned char id; outb(0x20, port); @@ -167,9 +310,10 @@ void probe_idregs_fintek(unsigned short port){ - unsigned int vid, did; + unsigned int vid, did, success = 0; // Enable configuration sequence (Fintek uses this for example) + // Older ITE chips have the same enable sequence outb(0x87, port); outb(0x87, port); @@ -185,13 +329,10 @@ } did = inb(port+1); - outb(0x21, port); - did = did|(inb(port+1)<<8); + did = did|(regval(port, 0x21)<<8); - outb(0x23, port); - vid = inb(port+1); - outb(0x24, port); - vid = vid|(inb(port+1)<<8); + vid = regval(port, 0x23); + vid = vid|(regval(port, 0x24)<<8); printf("SuperIO found at 0x%02x: vid=0x%04x/did=0x%04x\n", port, vid, did); @@ -199,23 +340,104 @@ return; // printf("%s\n", familyid[id]); + switch(did) { + case 0x0887: // reversed for ITE8708 + case 0x1087: // reversed for ITE8710 + success = 1; + dump_ite(port, ((did & 0xff) << 8) | ((did & 0xff00) >> 8)); + // disable configuration + regwrite(port, 0x02, 0x02); + break; + default: + break; + } switch(vid) { case 0x3419: + success = 1; dump_fintek(port, did); break; default: - printf("no dump for 0x%04x/0x%04x\n", vid, did); break; } + if (!success) + printf("no dump for vid 0x%04x, did 0x%04x\n", vid, did); - // disable configuration + // disable configuration (for Fintek, doesn't hurt ITE) outb(0xaa, port); } void +probe_idregs_ite(unsigned short port){ + unsigned int id, chipver; + + // Enable configuration sequence (ITE uses this for newer IT87[012]x) + // IT871[01] uses 0x87, 0x87 -> fintek detection should handle it + // IT8761 uses 0x87, 0x61, 0x55, 0x55/0xaa + // IT86xx series uses different ports + // IT8661 uses 0x86, 0x61, 0x55/0xaa, 0x55/0xaa and 32 more writes + // IT8673 uses 0x86, 0x80, 0x55/0xaa, 0x55/0xaa and 32 more writes + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + if (port == 0x2e) + outb(0x55, port); + else + outb(0xAA, port); + + // Read Chip ID Byte 1 + id = regval(port, 0x20); + if (id != 0x87) { + if (inb(port) == 0xff ) + printf ("No SuperIO chip found at 0x%04x\n", port); + else + printf("probing 0x%04x, failed (0x%02x), data returns 0x%02x\n", + port, inb(port), inb(port+1)); + return; + } + + id <<= 8; + + // Read Chip ID Byte 2 + id |= regval(port, 0x21); + + // Read Chip Version, only bit 3..0 for all IT87xx + chipver = regval(port, 0x22) & 0x0f; + + /* ID Mapping Table + unknown -> IT8711 (no datasheet) + unknown -> IT8722 (no datasheet) + 0x8702 -> IT8702 + 0x8705 -> IT8700 or IT8705 + 0x8710 -> IT8710 + 0x8712 -> IT8712 + 0x8716 -> IT8716 or IT8726 (identical except CPU voltage control) + 0x8718 -> IT8718 + */ + printf("ITE? SuperIO found at 0x%02x: id=0x%04x, chipver=0x%01x\n", + port, id, chipver); + + switch(id) { + case 0x8702: + case 0x8705: + case 0x8710: //pointless, IT8710 has different enable sequence + case 0x8712: + case 0x8716: + case 0x8718: + dump_ite(port, id); + break; + default: + printf("no dump for id 0x%04x\n", id); + break; + } + // disable configuration + regwrite(port, 0x02, 0x02); +} + +void probe_superio(unsigned short port) { probe_idregs_simple(port); probe_idregs_fintek(port); + probe_idregs_ite(port); } int

3 5

[LinuxBIOS] r2749 build service
by LinuxBIOS information 27 Aug '07

27 Aug '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2749 to the LinuxBIOS source repository and caused the following changes: Change Log: This patch rewrites probe_superio almost completely. Common code sequences have been factored out, the code has been made more generic, has better handling of corner cases and is actually much shorter. It also adds probing for almost all recent (since 1999) ITE Super I/O chips to probe_superio. I did verify against all ITE datasheets (including those not available any more) that the probing was non-destructive. For the ITE IT8712F, the complete configuration is dumped and as comparison the default value from the data sheet is printed. More information can be extracted easily, however this needs loads of datasheet surfing. This code has been tested extensively, dumping for other ITE chips will follow as a separate patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2749&device=hdama&vendor=… Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2749&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2749&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2749&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2749&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2749&device=dk8x&vendor=i… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] r2749 - trunk/LinuxBIOSv2/util/probe_superio
by svn＠openbios.org 27 Aug '07

27 Aug '07

Author: stepan Date: 2007-08-27 09:28:28 +0200 (Mon, 27 Aug 2007) New Revision: 2749 Modified: trunk/LinuxBIOSv2/util/probe_superio/probe_superio.c Log: This patch rewrites probe_superio almost completely. Common code sequences have been factored out, the code has been made more generic, has better handling of corner cases and is actually much shorter. It also adds probing for almost all recent (since 1999) ITE Super I/O chips to probe_superio. I did verify against all ITE datasheets (including those not available any more) that the probing was non-destructive. For the ITE IT8712F, the complete configuration is dumped and as comparison the default value from the data sheet is printed. More information can be extracted easily, however this needs loads of datasheet surfing. This code has been tested extensively, dumping for other ITE chips will follow as a separate patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/util/probe_superio/probe_superio.c =================================================================== --- trunk/LinuxBIOSv2/util/probe_superio/probe_superio.c 2007-08-23 16:08:21 UTC (rev 2748) +++ trunk/LinuxBIOSv2/util/probe_superio/probe_superio.c 2007-08-27 07:28:28 UTC (rev 2749) @@ -3,6 +3,7 @@ * * Copyright (C) 2006 Ronald Minnich <rminnich(a)gmail.com> * Copyright (C) 2006 coresystems GmbH <info(a)coresystems.de> + * Copyright (C) 2007 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,11 +33,16 @@ * if we need this. */ -unsigned char regval(unsigned short port, unsigned short reg) { +unsigned char regval(unsigned short port, unsigned char reg) { outb(reg, port); return inb(port+1); } +void regwrite(unsigned short port, unsigned char reg, unsigned char val) { + outb(reg, port); + outb(val, port+1); +} + void dump_ns8374(unsigned short port) { printf("Enables: 21=%02x, 22=%02x, 23=%02x, 24=%02x, 26=%02x\n", @@ -46,15 +52,13 @@ /* check COM1. This is all we care about at present. */ printf("COM 1 is Globally %s\n", regval(port,0x26)&8 ? "disabled" : "enabled"); /* select com1 */ - outb(0x7, port); - outb(3, port+1); + regwrite(port, 0x07, 0x03); printf("COM 1 is locally %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("COM1 60=%02x, 61=%02x, 70=%02x, 71=%02x, 74=%02x, 75=%02x, f0=%02x\n", regval(port, 0x60), regval(port, 0x61), regval(port, 0x70), regval(port, 0x71), regval(port, 0x74), regval(port, 0x75), regval(port, 0xf0)); /* select gpio */ - outb(0x7, port); - outb(7, port+1); + regwrite(port, 0x07, 0x07); printf("GPIO is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("GPIO 60=%02x, 61=%02x, 70=%02x, 71=%02x, 74=%02x, 75=%02x, f0=%02x\n", regval(port, 0x60), regval(port, 0x61), regval(port, 0x70), regval(port, 0x71), @@ -85,38 +89,33 @@ printf("2b=%02x\n", regval(port, 0x2b)); /* select UART 1 */ - outb(0x07, port); - outb(0x01, port+1); + regwrite(port, 0x07, 0x01); printf("UART1 is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("UART1 base=%02x%02x, irq=%02x, mode=%s\n", regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f, regval(port, 0xf0)&0x10 ? "RS485":"RS232"); /* select UART 2 */ - outb(0x07, port); - outb(0x02, port+1); + regwrite(port, 0x07, 0x02); printf("UART2 is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("UART2 base=%02x%02x, irq=%02x, mode=%s\n", regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f, regval(port, 0xf0)&0x10 ? "RS485":"RS232"); /* select Parport */ - outb(0x07, port); - outb(0x03, port+1); + regwrite(port, 0x07, 0x03); printf("PARPORT is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("PARPORT base=%02x%02x, irq=%02x\n", regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f); /* select hw monitor */ - outb(0x07, port); - outb(0x04, port+1); + regwrite(port, 0x07, 0x04); printf("HW monitor is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("HW monitor base=%02x%02x, irq=%02x\n", regval(port, 0x60), regval(port, 0x61), regval(port, 0x70)&0x0f); /* select gpio */ - outb(0x07, port); - outb(0x06, port+1); + regwrite(port, 0x07, 0x05); printf("GPIO is %s\n", regval(port, 0x30) & 1 ? "enabled" : "disabled"); printf("GPIO 70=%02x, e0=%02x, e1=%02x, e2=%02x, e3=%02x, e4=%02x, e5=%02x\n", regval(port, 0x70), regval(port, 0xe0), regval(port, 0xe1), regval(port, 0xe2), @@ -130,8 +129,152 @@ } +//End Of Table +#define EOT -1 +//NO LDN needed +#define NOLDN -2 +//Not Available +#define NANA -3 +//Biggest LDN +#define MAXLDN 0xa +//MAXimum NUMber of Indexes +#define MAXNUMIDX 70 +const static struct ite_registers { + signed short superio_id; //yes, it should be unsigned, but then EOT has to be positive + struct ite_ldnidx { + signed short ldn; + signed short idx[MAXNUMIDX+1]; + signed short def[MAXNUMIDX+1]; + } ldn[MAXLDN+3]; //biggestLDN+0+NOLDN+EOT +} ite_reg_table[] = { + {0x8712,{ + {NOLDN, + {0x07,0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, + {NANA,0x87,0x12,0x08,0x00,0x00,0x00,EOT}}, + {0x0, + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x00,0x00,EOT}}, + {0x1, + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x03,0xf8,0x04,0x00,0x50,0x00,0x7f,EOT}}, + {0x2, + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x02,0xf8,0x03,0x00,0x50,0x00,0x7f,EOT}}, + {0x3, + {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,EOT}, + {0x00,0x03,0x78,0x07,0x78,0x07,0x03,0x03,EOT}}, + {0x4, + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,EOT}, + {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00,0x00,0x00,NANA,NANA,EOT}}, + {0x5, + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x00,EOT}}, + {0x6, + {0x30,0x70,0x71,0xf0,EOT}, + {0x00,0x0c,0x02,0x00,EOT}}, + {0x7, + {0x25,0x26,0x27,0x28,0x29,0x2a,0x2c,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0x72,0x73,0x74,0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xc0,0xc1,0xc2,0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc,0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,EOT}, + {0x01,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,0x00,EOT}}, + {0x8, + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0x00,0x0a,0x00,EOT}}, + {0x9, + {0x30,0x60,0x61,EOT}, + {0x00,0x02,0x01,EOT}}, + {0xa, + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0x10,0x0b,0x00,EOT}}, + {EOT}}}, + {EOT} +}; void +dump_ite(unsigned short port, unsigned short id) +{ + int i, j, k; + signed short *idx; + printf ("ITE "); + + + /* ID Mapping Table + unknown -> IT8711 (no datasheet) + unknown -> IT8722 (no datasheet) + 0x8702 -> IT8702 + 0x8705 -> IT8700 or IT8705 + 0x8708 -> IT8708 + 0x8710 -> IT8710 + 0x8712 -> IT8712 + 0x8716 -> IT8716 or IT8726 (identical except CPU voltage control) + 0x8718 -> IT8718 + 0x8726 does not exist according to datasheet, but experience differs + */ + switch(id) { + case 0x8702: + printf ("IT8702\n"); + break; + case 0x8705: + printf ("IT8700 or IT8705\n"); + break; + case 0x8710: + printf ("IT8710\n"); + break; + case 0x8712: + printf ("IT8712\n"); + for (i=0;; i++) { + if (ite_reg_table[i].superio_id == EOT) + break; + if ((unsigned short)ite_reg_table[i].superio_id != id) + continue; + for (j=0;; j++) { + if (ite_reg_table[i].ldn[j].ldn == EOT) + break; + if (ite_reg_table[i].ldn[j].ldn != NOLDN) { + printf("switching to LDN 0x%01x\n", ite_reg_table[i].ldn[j].ldn); + regwrite(port, 0x07, ite_reg_table[i].ldn[j].ldn); + } + idx = ite_reg_table[i].ldn[j].idx; + printf("idx "); + for (k=0;; k++) { + if (idx[k] == EOT) + break; + printf("%02x ", idx[k]); + } + printf("\nval "); + for (k=0;; k++) { + if (idx[k] == EOT) + break; + printf("%02x ", regval(port, idx[k])); + } + printf("\ndef "); + idx = ite_reg_table[i].ldn[j].def; + for (k=0;; k++) { + if (idx[k] == EOT) + break; + if (idx[k] == NANA) + printf("NA "); + else + printf("%02x ", idx[k]); + } + printf("\n"); + } + + } + break; + case 0x8716: + printf ("IT8716 or IT8726\n"); + break; + case 0x8718: + printf ("IT8718\n"); + break; + default: + printf ("unknown ITE chip, id=%04x\n", id); + for (i=0x20; i<=0x24; i++) + printf("index %02x=%02x\n", i, regval(port, i)); + break; + } +} + +void probe_idregs_simple(unsigned short port){ unsigned char id; outb(0x20, port); @@ -167,9 +310,10 @@ void probe_idregs_fintek(unsigned short port){ - unsigned int vid, did; + unsigned int vid, did, success = 0; // Enable configuration sequence (Fintek uses this for example) + // Older ITE chips have the same enable sequence outb(0x87, port); outb(0x87, port); @@ -185,13 +329,10 @@ } did = inb(port+1); - outb(0x21, port); - did = did|(inb(port+1)<<8); + did = did|(regval(port, 0x21)<<8); - outb(0x23, port); - vid = inb(port+1); - outb(0x24, port); - vid = vid|(inb(port+1)<<8); + vid = regval(port, 0x23); + vid = vid|(regval(port, 0x24)<<8); printf("SuperIO found at 0x%02x: vid=0x%04x/did=0x%04x\n", port, vid, did); @@ -199,23 +340,104 @@ return; // printf("%s\n", familyid[id]); + switch(did) { + case 0x0887: // reversed for ITE8708 + case 0x1087: // reversed for ITE8710 + success = 1; + dump_ite(port, ((did & 0xff) << 8) | ((did & 0xff00) >> 8)); + // disable configuration + regwrite(port, 0x02, 0x02); + break; + default: + break; + } switch(vid) { case 0x3419: + success = 1; dump_fintek(port, did); break; default: - printf("no dump for 0x%04x/0x%04x\n", vid, did); break; } + if (!success) + printf("no dump for vid 0x%04x, did 0x%04x\n", vid, did); - // disable configuration + // disable configuration (for Fintek, doesn't hurt ITE) outb(0xaa, port); } void +probe_idregs_ite(unsigned short port){ + unsigned int id, chipver; + + // Enable configuration sequence (ITE uses this for newer IT87[012]x) + // IT871[01] uses 0x87, 0x87 -> fintek detection should handle it + // IT8761 uses 0x87, 0x61, 0x55, 0x55/0xaa + // IT86xx series uses different ports + // IT8661 uses 0x86, 0x61, 0x55/0xaa, 0x55/0xaa and 32 more writes + // IT8673 uses 0x86, 0x80, 0x55/0xaa, 0x55/0xaa and 32 more writes + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + if (port == 0x2e) + outb(0x55, port); + else + outb(0xAA, port); + + // Read Chip ID Byte 1 + id = regval(port, 0x20); + if (id != 0x87) { + if (inb(port) == 0xff ) + printf ("No SuperIO chip found at 0x%04x\n", port); + else + printf("probing 0x%04x, failed (0x%02x), data returns 0x%02x\n", + port, inb(port), inb(port+1)); + return; + } + + id <<= 8; + + // Read Chip ID Byte 2 + id |= regval(port, 0x21); + + // Read Chip Version, only bit 3..0 for all IT87xx + chipver = regval(port, 0x22) & 0x0f; + + /* ID Mapping Table + unknown -> IT8711 (no datasheet) + unknown -> IT8722 (no datasheet) + 0x8702 -> IT8702 + 0x8705 -> IT8700 or IT8705 + 0x8710 -> IT8710 + 0x8712 -> IT8712 + 0x8716 -> IT8716 or IT8726 (identical except CPU voltage control) + 0x8718 -> IT8718 + */ + printf("ITE? SuperIO found at 0x%02x: id=0x%04x, chipver=0x%01x\n", + port, id, chipver); + + switch(id) { + case 0x8702: + case 0x8705: + case 0x8710: //pointless, IT8710 has different enable sequence + case 0x8712: + case 0x8716: + case 0x8718: + dump_ite(port, id); + break; + default: + printf("no dump for id 0x%04x\n", id); + break; + } + // disable configuration + regwrite(port, 0x02, 0x02); +} + +void probe_superio(unsigned short port) { probe_idregs_simple(port); probe_idregs_fintek(port); + probe_idregs_ite(port); } int

1 0

[LinuxBIOS] [PATCH] flashrom: Move code into C files
by Uwe Hermann 26 Aug '07

26 Aug '07

This is the first in a row of many cleanup patches for flashrom. Step 1: Move all code into *.c files, not *.h files. I don't see a reason to have them in header files. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

4 6

[LinuxBIOS] [PATCH][v3] small lar fix
by Patrick Georgi 26 Aug '07

26 Aug '07

Hi, the checksum creation in lar starts somewhere in the lar image, and ends at the end of a temporary buffer, which doesn't look right to me (and segfaults if between those two there's an unmapped region, as happened here) Attached patch should fix that, but I'd like to have someone look over it to make sure it checksums the right area. Regards, Patrick Georgi

3 2

[LinuxBIOS] r480 - LinuxBIOSv3/util/lar
by svn＠openbios.org 26 Aug '07

26 Aug '07

Author: uwe Date: 2007-08-26 14:12:22 +0200 (Sun, 26 Aug 2007) New Revision: 480 Modified: LinuxBIOSv3/util/lar/stream.c Log: The checksum creation in lar starts somewhere in the lar image, and ends at the end of a temporary buffer, which doesn't look right to me (and segfaults if between those two there's an unmapped region, as happened here). Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: LinuxBIOSv3/util/lar/stream.c =================================================================== --- LinuxBIOSv3/util/lar/stream.c 2007-08-26 12:06:51 UTC (rev 479) +++ LinuxBIOSv3/util/lar/stream.c 2007-08-26 12:12:22 UTC (rev 480) @@ -666,7 +666,7 @@ csum = 0; for (walk = (u32 *) (lar->map + offset); - walk < (u32 *) (temp + complen + hlen); + walk < (u32 *) (lar->map + complen + hlen); walk++) { csum += ntohl(*walk); }

1 0

← Newer
1
...
5
6
7
8
9
10
11
...
21
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot August 2007