coreboot August 2007

coreboot@coreboot.org

78 participants
202 discussions

[LinuxBIOS] [PATCH] v3: code documentation fixes

by Carl-Daniel Hailfinger

Correct typo, fix stage2 code documentation, add dtsname printing to differentiate between identically named objects during boot. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3/include/device/device.h =================================================================== --- LinuxBIOSv3/include/device/device.h (Revision 485) +++ LinuxBIOSv3/include/device/device.h (Arbeitskopie) @@ -202,7 +202,7 @@ struct resource resource[MAX_RESOURCES]; unsigned int resources; - /* link are (down sream) buses attached to the device, usually a leaf + /* link are (downstream) buses attached to the device, usually a leaf * device with no children have 0 buses attached and a bridge has 1 bus */ struct bus link[MAX_LINKS]; Index: LinuxBIOSv3/device/device.c =================================================================== --- LinuxBIOSv3/device/device.c (Revision 485) +++ LinuxBIOSv3/device/device.c (Arbeitskopie) @@ -260,8 +260,10 @@ for (curdev = bus->children; curdev; curdev = curdev->sibling) { unsigned int links; int i; - printk(BIOS_SPEW, "%s: %s(%s) have_resources %d enabled %d\n", + printk(BIOS_SPEW, + "%s: %s(%s) dtsname %s have_resources %d enabled %d\n", __func__, bus->dev->dtsname, dev_path(bus->dev), + curdev->dtsname, curdev->have_resources, curdev->enabled); if (curdev->have_resources) { continue; Index: LinuxBIOSv3/lib/stage2.c =================================================================== --- LinuxBIOSv3/lib/stage2.c (Revision 485) +++ LinuxBIOSv3/lib/stage2.c (Arbeitskopie) @@ -31,8 +31,9 @@ /** * Main function of the DRAM part of LinuxBIOS. * - * LinuxBIOS is divided into pre-DRAM part and DRAM part. The phases before - * this part are phase 0 and phase 1. This part contains phases x through y. + * LinuxBIOS is divided into pre-DRAM part and DRAM part. The stages before + * this part are stage 0 and stage 1. This part contains stage 2, which + * consists of phases 1 through 6. * * Device Enumeration: in the dev_enumerate() phase. * @@ -53,6 +54,7 @@ post_code(0x20); + /* TODO: Explain why we use printk here although it is impossible */ printk(BIOS_NOTICE, console_test); dev_init();

13 years, 7 months

[LinuxBIOS] EFI Payload help: how to identify the resource types and attributes in LB

by Xiong Yi

Hi, all I am developing the EFI payload for LB (see http://code.google.com/soc/2007/coresystems/appinfo.html?csaid=83B941F46A422 F1A). And I am unifying the resource management of LB and EFI. In more details, I am parsing the LB table and converting it to the HOB structures of Tiano EFI. I described this idea several days ago. (http://www.linuxbios.org/pipermail/linuxbios/2007-June/022340.html) But there is a problem: The Tiano EFI describes the system resources as types and attributes, such as the following definition: //********************************************************* // EFI_RESOURCE_TYPE (define the resource type) //********************************************************* typedef UINT32 EFI_RESOURCE_TYPE; #define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000 (system memory resource) #define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001 (memory-mapped IO) #define EFI_RESOURCE_IO 0x00000002 (Processor IO space) #define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003 (Memory-mapped firmware device) #define EFI_RESOURCE_MEMORY_RESERVED 0x00000005 (Reserved memory address space) #define EFI_RESOURCE_IO_RESERVED 0x00000006 (Reserved IO address space) //************************************************************************** ******** // EFI_RESOURCE_ATTRIBUTE_TYPE(define the resource attributes) //************************************************************************** ******** typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE; // These types can be ORed together as needed. #define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001 (the memory region exists) #define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002 (the memory region has been initialized) #define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004 (the memory region has been tested) And there are similar definitions in the LB's /src/include/device/resourch.h file. But I can just find IORESOURCE_MEM | IORESOURCE_CACHEABLE (system memory) resources types and LB_MEM_RAM, LB_MEM_TABLE attributes in the LB tables. So how to identify other resource types and attributes in LB? Or the current LB implementation just describes these types and attributes, I need to construct the rest resource types and attributes in the payload itself as the exact requirement? By the way, I built the LB with qemu emulation and just track qemu emulation LB's source codes. Thanks & Best regards, Xiong Yi

13 years, 7 months

[LinuxBIOS] [RFC] Call for Action: LinuxBIOS foundations

by Carl-Daniel Hailfinger

Hi, since we're aiming for broader coverage in LinuxBIOS and related tools, I think we should publish a "Call for Action" which urges interested people to give us dumps of their board configuration etc. Example of such a call (for flashrom only, though): http://lists.us.dell.com/pipermail/firmware-tools-devel/2007-August/000121.… Right now, I'd like to get a list of stuff we potentially could use: - flashrom -V - lspci -nvx - dmidecode - probe_superio - /proc/interrupts? - board name/model Comments? Regards, Carl-Daniel

13 years, 7 months

[LinuxBIOS] LinuxBios with SuperIO Winbond W83627HG-AW

by Steffen D.

Dear Mailinglist, im trying to build a bios for GeodeLX cpu. I have a development board from LogicPC. Afaik this is the same board that was used for the development for OLCP. I try it with the svn version Linuxbios-3. I have made a image with make menuconfig and configured everything cleary for the geodelx board. I flash the rom with windows and a galep 5 flash device. Im very sure that the flashing works because i can clone the bios which comes with the board. I dont get any output over rs232. Im using SST 49LF004B roms with 4mbit. Maybe here is the problem? I have made linuxbios.rom with a target size of 2mb. I also tryed "cat linuxbios.rom linuxbios.rom > linuxbios4m.rom". I found this hin here in the ml. Every help is welcome! Regards, Steffen

13 years, 7 months

[LinuxBIOS] #86: filo sata boot delay patch

by LinuxBIOS

#86: filo sata boot delay patch --------------------------------+------------------------------------------- Reporter: ward | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: code | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs work | --------------------------------+------------------------------------------- I've been using the attached patch to filo on machines that need to boot from SATA disks. It's only necessary on cold boot, as the problem is the physical spin-up of the drives. The patch is very crude, and there have been reports that a shorter delay is sufficient. I have not had time to test a shorter delay, and I suspect that the length of the delay might depend somewhat on the drives used. Ideally there would be a way for FILO to see if the boot was cold or warm so that it could apply the delay in the cold-boot case only. Also, this delay should be configurable in FILO's Config file. -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/86> LinuxBIOS <http://www.linuxbios.org/>

13 years, 7 months

Re: [LinuxBIOS] [PATCH] Reimplementation/fixing of CS5530/CS5530A southbridge code

by Jonathan Sturges

On Wed, Aug 15, 2007 at 11:02:29PM -0400, Jonathan Sturges wrote: > Thanks for the updated 5530 code! > However, I'm having some difficulty enabling the IDE controllers when using > this patch. As far as I can tell, configuration parsing doesn't appear to > work for new ideX_enable flags. > > The 'register "ide0_enable" = "1"' configuration option seemed to have no > effect on my 5530 system. Even though both IDE controllers were enabled in > Config.lb, when I'd test the resulting image, IDE0 would be disabled and > IDE1 enabled. In the end, to make it work, I changed: > "if (conf->ide0_enable) {" > to: > "if ( 1 ) {" > ...in cs5530_ide.c to get IDE0 enabled. This forces it to work. The placement of the ide0_enable lines is important. I think they should _not_ be within the IDE section. Check src/mainboard/asi/mb_5blmp/Config.lb for an example which worked for me, and please report if that fixes the problem. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org Uwe, I'm still having problems. The ideX_enable register values are within the "chip southbridge/amd/cs5530" context in my Config.lb, which matches the ASI mb-5blmp you cited. This is grasping at straws, but my Config.lb inconsistently uses tabs and spaces... any issues there, beyond aesthetics? Anyway, FWIW, I attached the Config.lb I'm working from. Any hints appreciated. thanks, Jonathan ____________________________________________________________________________________ Pinpoint customers who are looking for what you sell. http://searchmarketing.yahoo.com/

13 years, 7 months

[LinuxBIOS] [PATCH] Initial support for the MSI MS-6178 (i810-based)

by Uwe Hermann

Hi, here's an initial patch for the MSI MS-6178 mainboard. It boots up to a login prompt, but there are a number of issues which need to be fixed before we can call this fully supported. I'll post a list of working and non-working parts later, need to do more tests... One major issue is that the booting (and operation afterwards) is _really_ slow, a full boot takes more than 10 or 20 minutes! I suspect RAM init problems or cache (L1/L2) problems, but I haven't yet found out what's really going on. Full boot log of LinuxBIOS + the original BIOS attached. I guess (from looking at the boot log diffs) that this may be the reason for the slow boot, but how do I fix it? CPU: L1 I cache: 16K, L1 D cache: 16K -CPU: L2 cache: 128K (i.e., it seems the L2 cache is never enabled when using LinuxBIOS) Here's the SPD dump of the RAM I used (64 MB in slot 0): 00: 80 08 04 0c 09 01 40 00 01 a0 60 00 80 08 00 01 10: 8f 04 07 01 01 00 0f f0 70 00 00 1e 14 1e 32 10 20: 20 10 20 10 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 6a 40: 00 00 00 00 00 00 00 00 00 42 50 42 36 37 38 31 50: 41 00 00 00 00 00 00 00 00 00 00 00 00 29 62 00 60: 00 00 00 ff ff ff ff ff ff ff ff ff ff ff ff ff 70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff 64 04 80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f0: ff ff ff ff ff fe ff ff ff ff ff ff ff ff fe ff $ lspci -nn (from vendor BIOS) 00:00.0 Host bridge [0600]: Intel Corporation 82810 GMCH [Graphics Memory Controller Hub] [8086:7120] (rev 03) 00:01.0 VGA compatible controller [0300]: Intel Corporation 82810 CGC [Chipset Graphics Controller] [8086:7121] (rev 03) 00:1e.0 PCI bridge [0604]: Intel Corporation 82801AB PCI Bridge [8086:2428] (rev 01) 00:1f.0 ISA bridge [0601]: Intel Corporation 82801AB ISA Bridge (LPC) [8086:2420] (rev 01) 00:1f.1 IDE interface [0101]: Intel Corporation 82801AB IDE [8086:2421] (rev 01) 00:1f.2 USB Controller [0c03]: Intel Corporation 82801AB USB [8086:2422] (rev 01) 00:1f.5 Multimedia audio controller [0401]: Intel Corporation 82801AB AC'97 Audio [8086:2425] (rev 01) 00:1f.6 Modem [0703]: Intel Corporation 82801AB AC'97 Modem [8086:2426] (rev 01) 01:00.0 VGA compatible controller [0300]: S3 Inc. 86c325 [ViRGE] [5333:5631] (rev 06) 01:01.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8029(AS) [10ec:8029] $ lspci -xxx 00:00.0 Host bridge: Intel Corporation 82810 GMCH [Graphics Memory Controller Hub] (rev 03) 00: 86 80 20 71 06 00 80 20 03 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 20 71 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 68 51 a0 3c 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: c6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 9a dd 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

13 years, 8 months

[LinuxBIOS] LinuxBIOS - Booting Windows XP

by Augusto Pedroza

I have created two diff's, the first one is for linuxBIOSv2 (xpboot.diff) the second is for LinuxBIOSv3, it adds ADLO to v3. details: http://www.linuxbios.org/Booting_Windows_using_LinuxBIOS Feel free to test it and give some feedback!! We hope Vista comes soon. Regards, -- Augusto Pedroza

13 years, 8 months

[LinuxBIOS] problems with reboot on K8

by Rudolf Marek

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all, I cant get the reboot working. I have set CPU reboot to INIT in my SB, so INIT is generated when booting via KBD/92, Linuxbios will jump to real_main, same way as it boots from cold, but got freeze on setup_default_resource_map(); I'm using default usermap from K8, sometimes it writes more entries to 0:18.1 sometimes just first (the code which takes the resource table and simply do the pci writes, with correct and and or mask) I dont know even if my code should reboot this way? But the devel guide from AMD suggest that this must be set up again. I dont know at all what is wrong? The soft_reset is called from init_cpus, maybe too early for the NB? Any help is kindly appreciated. Other stuff is working fine, I'm using LB on daily use. Once reboot work I will release my KT890/VT8237 on Asus A8V-E SE mb LB code to public testing and review. thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFG0bkB3J9wPJqZRNURArXZAKC4hgRju24kgym7x5auicd49Re56ACdHHTu 7vvFeslx3Zx4s1GUgDY8sPk= =2ucY -----END PGP SIGNATURE-----

13 years, 8 months

[LinuxBIOS] [PATCH][v3] Support for multiple LinuxBIOS payloads

by Uwe Hermann

Hi, here's a first (draft) implementation for having multiple LinuxBIOS payloads in one image, which will be executed one after the other. This is part of my GЅoC project work; it's needed for lbmenu, the LinuxBIOS runtime config tool. More details in the patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

13 years, 8 months

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coreboot August 2007