coreboot April 2007

coreboot@coreboot.org

76 participants
281 discussions

[LinuxBIOS] GA-2CEWH suppored?
by Petter Sulwik 03 Apr '07

03 Apr '07

Hi 1. 2x Opteron 250 (CG), nForce Professional 2200, 2050 and AMD 8132 chipset. 2. Running server2003ee today (does aida32 supply same info?) 3. nForce4 / EMC6w201 + IT8712F 4. ServerBios, P4, Phoenix2000, 000274276 5. http://www.gigabyte.com.tw/Support/Networking/BIOS_Model.aspx?ClassValue=Ne… 6. GA-2CEWH (1.0) Support dual AMD(r) Opteron™ 200 series processors NVIDIA(r) nForce™ Professional 2200, 2050 and AMD(r) 8132 chipset Dual PCI-E x16 graphic slots with SLI supported Maximum 32GB Registered DDR333/400 Support four SATAII with RAID 0,1, 0+1 JBOD One Broadcom(r) BCM5751 and one Broadcom(r) B5011U Gigabit LAN I have also a question when ECC, chipkill and NUMA will be supported? Best regards Petter Sulwik

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[LinuxBIOS] r2580 build service
by LinuxBIOS information 03 Apr '07

03 Apr '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2580 to the LinuxBIOS source repository and caused the following changes: Change Log: Add initial framework for the Tyan S1846. It's not fully working, among other things because the Intel 440BX northbridge isn't working, yet. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of gigabyte:m57sli is still broken Configuration of msi:ms9282 is still broken Compilation of nvidia:l1_2pvv is still broken Compilation of supermicro:h8dmr is still broken Compilation of tyan:s2912 is still broken If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] r2580 - in trunk/LinuxBIOSv2: src/mainboard/tyan src/mainboard/tyan/s1846 targets/tyan targets/tyan/s1846
by svn＠openbios.org 03 Apr '07

03 Apr '07

Author: uwe Date: 2007-04-03 12:45:53 +0200 (Tue, 03 Apr 2007) New Revision: 2580 Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/chip.h trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/failover.c trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/mainboard.c trunk/LinuxBIOSv2/targets/tyan/s1846/ trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb Log: Add initial framework for the Tyan S1846. It's not fully working, among other things because the Intel 440BX northbridge isn't working, yet. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb 2007-04-03 10:45:53 UTC (rev 2580) @@ -0,0 +1,135 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +#if HAVE_PIRQ_TABLE object irq_tables.o end +#object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +# TODO. +chip northbridge/intel/i440bx + device pci_domain 0 on + end + chip cpu/intel/slot_2 + end +end + Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Options.lb 2007-04-03 10:45:53 UTC (rev 2580) @@ -0,0 +1,150 @@ +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 256*1024 + +### +### Build options +### + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=0 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=0 +default IRQ_SLOT_COUNT=4 +#object irq_tables.o + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_PAYLOAD = 1 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=9 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=9 + +default CONFIG_UDELAY_TSC=1 + +end + Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c 2007-04-03 10:45:53 UTC (rev 2580) @@ -0,0 +1,86 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "mainboard/bitworks/ims/debug.c" // FIXME +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "superio/nsc/pc87309/pc87309_early_serial.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x2e, PC87309_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" +#include "sdram/generic_sdram.c" + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .channel0 = { + (0xa << 3) | 0, + (0xa << 3) | 1, + (0xa << 3) | 2, + (0xa << 3) | 3, + }, + }, + }; + + /* Skip this if there was a built in self test failure. */ + if (bist == 0) { + early_mtrr_init(); + } + + pc87309_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + enable_smbus(); + + dump_spd_registers(&memctrl[0]); + + sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + + /* Check 64 MB of RAM. */ + ram_check(0x00000000, 0x04000000); +} Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/chip.h 2007-04-03 10:45:53 UTC (rev 2580) @@ -0,0 +1,24 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_tyan_s1846_ops; + +struct mainboard_tyan_s1846_config { +}; Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/failover.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/failover.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/failover.c 2007-04-03 10:45:53 UTC (rev 2580) @@ -0,0 +1,32 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ + /* This is the primary cpu how should I boot? */ + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} Added: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/mainboard.c 2007-04-03 10:45:53 UTC (rev 2580) @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_tyan_s1846_ops = { + CHIP_NAME("Tyan S1846 Mainboard") +}; Added: trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb 2007-04-03 10:45:53 UTC (rev 2580) @@ -0,0 +1,38 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target s1846 +mainboard tyan/s1846 + +option ROM_SIZE = 256 * 1024 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option LINUXBIOS_EXTRA_VERSION = ".0Normal" + payload /etc/hosts # TODO +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + payload /etc/hosts # TODO +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

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[LinuxBIOS] r2579 build service
by LinuxBIOS information 02 Apr '07

02 Apr '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2579 to the LinuxBIOS source repository and caused the following changes: Change Log: The *_early_serial.c pre-RAM code should do just that -- enable the serial port(s), and nothing else. The code in superio.c will initialize the rest when RAM is available... Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of gigabyte:m57sli is still broken Configuration of msi:ms9282 is still broken Compilation of nvidia:l1_2pvv is still broken Compilation of supermicro:h8dmr is still broken Compilation of tyan:s2912 is still broken If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] [PATCH] *_early_serial.c Super I/O fixes
by Uwe Hermann 02 Apr '07

02 Apr '07

I messed up the ITE Super I/Os, time to fix them... More patches will follow. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

3 3

[LinuxBIOS] r2579 - in trunk/LinuxBIOSv2/src/superio/ite: it8661f it8671f it8673f it8705f it8712f it8718f
by svn＠openbios.org 02 Apr '07

02 Apr '07

Author: uwe Date: 2007-04-02 18:57:32 +0200 (Mon, 02 Apr 2007) New Revision: 2579 Modified: trunk/LinuxBIOSv2/src/superio/ite/it8661f/it8661f_early_serial.c trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c trunk/LinuxBIOSv2/src/superio/ite/it8673f/it8673f_early_serial.c trunk/LinuxBIOSv2/src/superio/ite/it8705f/it8705f_early_serial.c trunk/LinuxBIOSv2/src/superio/ite/it8712f/it8712f_early_serial.c trunk/LinuxBIOSv2/src/superio/ite/it8718f/it8718f_early_serial.c Log: The *_early_serial.c pre-RAM code should do just that -- enable the serial port(s), and nothing else. The code in superio.c will initialize the rest when RAM is available... Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/superio/ite/it8661f/it8661f_early_serial.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/ite/it8661f/it8661f_early_serial.c 2007-04-01 20:00:32 UTC (rev 2578) +++ trunk/LinuxBIOSv2/src/superio/ite/it8661f/it8661f_early_serial.c 2007-04-02 16:57:32 UTC (rev 2579) @@ -80,12 +80,9 @@ PP (3), IR (4). Bits 5-7 are reserved. */ it8661f_sio_write(0x00, IT8661F_CONFIG_REG_LDE, 0x1f); - /* Enable all devices. */ - it8661f_sio_write(IT8661F_FDC, 0x30, 0x1); /* Floppy */ + /* Enable serial port(s). */ it8661f_sio_write(IT8661F_SP1, 0x30, 0x1); /* Serial port 1 */ it8661f_sio_write(IT8661F_SP2, 0x30, 0x1); /* Serial port 2 */ - it8661f_sio_write(IT8661F_PP, 0x30, 0x1); /* Parallel port */ - it8661f_sio_write(IT8661F_IR, 0x30, 0x1); /* IR */ /* Select 24MHz CLKIN (clear bit 1) and clear software suspend mode (clear bit 0). */ Modified: trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c 2007-04-01 20:00:32 UTC (rev 2578) +++ trunk/LinuxBIOSv2/src/superio/ite/it8671f/it8671f_early_serial.c 2007-04-02 16:57:32 UTC (rev 2579) @@ -80,13 +80,9 @@ PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */ it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f); - /* Activate all devices. */ - it8671f_sio_write(IT8671F_FDC, 0x30, 0x01); /* Floppy */ + /* Enable serial port(s). */ it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */ it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */ - it8671f_sio_write(IT8671F_PP, 0x30, 0x01); /* Parallel port */ - it8671f_sio_write(IT8671F_KBCK, 0x30, 0x01); /* Keyboard */ - it8671f_sio_write(IT8671F_KBCM, 0x30, 0x01); /* Mouse */ /* Select 24MHz CLKIN (clear bit 6) and clear software suspend mode (clear bit 0). */ Modified: trunk/LinuxBIOSv2/src/superio/ite/it8673f/it8673f_early_serial.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/ite/it8673f/it8673f_early_serial.c 2007-04-01 20:00:32 UTC (rev 2578) +++ trunk/LinuxBIOSv2/src/superio/ite/it8673f/it8673f_early_serial.c 2007-04-02 16:57:32 UTC (rev 2579) @@ -77,13 +77,8 @@ /* (2) Modify the data of configuration registers. */ /* Enable all devices. */ - it8673f_sio_write(IT8673F_FDC, 0x30, 0x1); /* Floppy */ it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */ it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */ - it8673f_sio_write(IT8673F_PP, 0x30, 0x1); /* Parallel port */ - it8673f_sio_write(IT8673F_FAN, 0x30, 0x1); /* Fan controller */ - it8673f_sio_write(IT8673F_KBCK, 0x30, 0x1); /* Keyboard */ - it8673f_sio_write(IT8673F_KBCM, 0x30, 0x1); /* Mouse */ /* Select 24MHz CLKIN (clear bit 0). */ it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00); Modified: trunk/LinuxBIOSv2/src/superio/ite/it8705f/it8705f_early_serial.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/ite/it8705f/it8705f_early_serial.c 2007-04-01 20:00:32 UTC (rev 2578) +++ trunk/LinuxBIOSv2/src/superio/ite/it8705f/it8705f_early_serial.c 2007-04-02 16:57:32 UTC (rev 2579) @@ -67,15 +67,9 @@ If this register is not written, both chips are configured. */ /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */ - /* Enable all devices. */ - it8705f_sio_write(IT8705F_FDC, 0x30, 0x1); /* Floppy */ + /* Enable serial port(s). */ it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */ it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */ - it8705f_sio_write(IT8705F_PP, 0x30, 0x1); /* Parallel port */ - it8705f_sio_write(IT8705F_EC, 0x30, 0x1); /* Environment controller */ - it8705f_sio_write(IT8705F_GAME, 0x30, 0x1); /* GAME port */ - it8705f_sio_write(IT8705F_IR, 0x30, 0x1); /* Consumer IR */ - it8705f_sio_write(IT8705F_MIDI, 0x30, 0x1); /* MIDI port */ /* Select 24MHz CLKIN (set bit 0). */ it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01); Modified: trunk/LinuxBIOSv2/src/superio/ite/it8712f/it8712f_early_serial.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/ite/it8712f/it8712f_early_serial.c 2007-04-01 20:00:32 UTC (rev 2578) +++ trunk/LinuxBIOSv2/src/superio/ite/it8712f/it8712f_early_serial.c 2007-04-02 16:57:32 UTC (rev 2579) @@ -65,17 +65,9 @@ If this register is not written, both chips are configured. */ /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */ - /* Enable all devices. */ - it8712f_sio_write(IT8712F_FDC, 0x30, 0x1); /* Floppy */ + /* Enable serial port(s). */ it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ - it8712f_sio_write(IT8712F_PP, 0x30, 0x1); /* Parallel port */ - it8712f_sio_write(IT8712F_EC, 0x30, 0x1); /* Environment controller */ - it8712f_sio_write(IT8712F_KBCK, 0x30, 0x1); /* Keyboard */ - it8712f_sio_write(IT8712F_KBCM, 0x30, 0x1); /* Mouse */ - it8712f_sio_write(IT8712F_MIDI, 0x30, 0x1); /* MIDI port */ - it8712f_sio_write(IT8712F_GAME, 0x30, 0x1); /* GAME port */ - it8712f_sio_write(IT8712F_IR, 0x30, 0x1); /* Consumer IR */ /* Select 24MHz CLKIN (set bit 0). */ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x01); Modified: trunk/LinuxBIOSv2/src/superio/ite/it8718f/it8718f_early_serial.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/ite/it8718f/it8718f_early_serial.c 2007-04-01 20:00:32 UTC (rev 2578) +++ trunk/LinuxBIOSv2/src/superio/ite/it8718f/it8718f_early_serial.c 2007-04-02 16:57:32 UTC (rev 2579) @@ -66,14 +66,8 @@ /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable all devices. */ - it8718f_sio_write(IT8718F_FDC, 0x30, 0x1); /* Floppy */ it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */ it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */ - it8718f_sio_write(IT8718F_PP, 0x30, 0x1); /* Parallel port */ - it8718f_sio_write(IT8718F_EC, 0x30, 0x1); /* Environment controller */ - it8718f_sio_write(IT8718F_KBCK, 0x30, 0x1); /* Keyboard */ - it8718f_sio_write(IT8718F_KBCM, 0x30, 0x1); /* Mouse */ - it8718f_sio_write(IT8718F_IR, 0x30, 0x1); /* Consumer IR */ /* Select 24MHz CLKIN (set bit 0). */ it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x01);

1 0

Re: [LinuxBIOS] Fallback checking normal
by Thomas Ekstrand 02 Apr '07

02 Apr '07

> -----Original Message----- > From: Stefan Reinauer [*mailto:stepan@coresystems.de*<stepan(a)coresystems.de>] > Sent: den 23 mars 2007 17:55 > To: Thomas Ekstrand (AL/EAB) > Cc: linuxbios(a)linuxbios.org > Subject: Re: [LinuxBIOS] Fallback checking normal > > * Thomas Ekstrand thomas.ekstrand(a)gmail.com > [070323 17:02]: > > I'm wondering wether the fallback ever checks the normal image to see > > if it is ok before jumping to it? > > LinuxBIOSv3 will do this. Is there a date set for LinuxBIOSv3? > > > If not, why? > > The mechanism works in a real life check. A flag is set > before the image is jumped to, and that flag is cleared by > the OS loader (or by the OS, if you wish). Whenever the > system is booted with the flag set, it uses the fallback > image instead of the normal image. > > So this check does not only check for a correct checksum, but > whether the normal image was actually able to boot the OS. > This makes this feature not only usable for flash failures > but also for developer failures. ;-) > > > How is LinuxBIOS support for: > > SMBIOS > > SMI > > LinuxBIOS does "support" having those (ie. it does not > prevent them) but does not implement any system management > functionality, as it is not needed (and even discouraged) to > have them. What do you need them for? Donno, just checking things out! :) I'm doing a technical report on LinuxBIOS as part of a school project. Maybe it can be of some use in the documenation or something? I will say that I'm no expert so it's basically a summary of what you can find on the internet. but still... > > > Vmware > > Some people on this list have been working on vmware support. > See the web archive. Is there a search engine for the archive? It's kinda hard to know which month to look at :) > > Stefan > > -- > coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. > Tel.: +49 761 7668825 • Fax: +49 761 7664613 > Email: info(a)coresystems.de • *http://www.coresystems.de/*<http://www.coresystems.de/> > Thanks for taking your time! /Thomas

7 10

[LinuxBIOS] #75: xslt error with trunk
by LinuxBIOS 02 Apr '07

02 Apr '07

#75: xslt error with trunk --------------------------------------------+------------------------------- Reporter: twisti(a)complang.tuwien.ac.at | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: code | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | --------------------------------------------+------------------------------- This happens with debian testing (upcoming etch) on powerpc with svn rev114: {{{ $ make Building OpenBIOS on ppc for sparc32 Cleaning up... ok Initializing build tree...ok. Creating target Makefile...runtime error: file config/xml/dictionary.xsl line 13 element param Unexpected XSLT element 'param'. runtime error: file config/xml/dictionary.xsl line 22 element if Variable 'conditions' has not been declared. make: *** [xml] Error 10 }}} -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/75> LinuxBIOS <http://www.linuxbios.org/>

1 2

[LinuxBIOS] [PATCH] Intel 44BX RAM initialization framework
by Uwe Hermann 02 Apr '07

02 Apr '07

This is a first version of my RAM init code for the 440BX. It does _not_ work, yet. Don't try to use it unless you know what you're doing. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

3 4

[LinuxBIOS] ICH7DH: flash_enable failed
by Anton 02 Apr '07

02 Apr '07

flashrom's output below. what I've missed so far? Calibrating delay loop... Setting up microsecond timing loop 798M loops per second ok No LinuxBIOS table found. Enabling flash write on ICH7DH...tried to set 0xdc to 0x3 on ICH7DH failed (WARNING ONLY) Trying Am29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Trying Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Trying AE49F2008, 256 KB probe_jedec: id1 0xff, id2 0xff Trying At29C040A, 512 KB probe_jedec: id1 0xff, id2 0xff Trying Mx29f002, 256 KB probe_29f002: id1 0xff, id2 0xff Trying SST29EE020A, 256 KB probe_jedec: id1 0xff, id2 0xff Trying SST25LF080A, 1024 KB probe_jedec: id1 0x0, id2 0x0 Trying SST28SF040A, 512 KB probe_28sf040: id1 0xff, id2 0xff Trying SST39SF010A, 128 KB probe_jedec: id1 0xff, id2 0xff Trying SST39SF020A, 256 KB

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coreboot April 2007