coreboot March 2007

coreboot@coreboot.org

118 participants
226 discussions

[LinuxBIOS] GA-M57SLI-S4 continuity test on the second plcc socket.
by Beth 29 Mar '07

29 Mar '07

Hi guys (and girls). Good morning (at least here GMT+1) ;). Well this morning I did with the help of the multimeter a continuity test between the soldered bios and the pins that seems to be a second bios socket, you know. The majority of the pins are directly connected, but there are a few that aren't. Here are what pins are NOT connected to each other on the two sockets: 1,9,10,11,12,19,20,21,22,24,26,27 Maybe are unused, I don't know, and worst, I dont understand on the datasheet of the chip what means the three names that are given to the pins, each for these columns: A/A Mux, LPC, FWH. If someone can clarify it ... Another thing is something that a friend of mine says yesterday: why instead of removing the chip, take and desolder only the vcc pin, put a micro-switch on it, solder another chip on top of the existing and do the same with its vcc pin, so with two micro-switches you can select wich bios chip use. What do you think about this solution?. If the other socked is directly connected, I don't understand the three modes of operation of the chip as I say previously, it will be a good thing installing the switches to both sockets and leave the original for backup and life-guard, and use the second for testing,working,etc. Thats all folks, for the moment ;). Have a nice day. Jose.

4 3

[LinuxBIOS] Porting linuxbios to the VIA CN700
by Tom Kirkpatrick 29 Mar '07

29 Mar '07

Hi, I'm hoping someone is up for the task of porting linuxbios to the VIA CN700 chipset. I was asking around in the IRC room and was told that this info might help someone out: The lspci output looks a little screwed... not sure why tho. root@STC:~$ lspci 00:00.0 Class 0600: Unknown device 1106:0314 00:00.1 Class 0600: Unknown device 1106:1314 00:00.2 Class 0600: Unknown device 1106:2314 00:00.3 Class 0600: Unknown device 1106:3208 00:00.4 Class 0600: Unknown device 1106:4314 00:00.7 Class 0600: Unknown device 1106:7314 00:01.0 Class 0604: Unknown device 1106:b198 00:0a.0 Class 0c00: Unknown device 1106:3044 (rev 80) 00:0f.0 Class 0101: Unknown device 1106:3149 (rev 80) 00:0f.1 Class 0101: Unknown device 1106:0571 (rev 06) 00:10.0 Class 0c03: Unknown device 1106:3038 (rev 81) 00:10.1 Class 0c03: Unknown device 1106:3038 (rev 81) 00:10.2 Class 0c03: Unknown device 1106:3038 (rev 81) 00:10.3 Class 0c03: Unknown device 1106:3038 (rev 81) 00:10.4 Class 0c03: Unknown device 1106:3104 (rev 86) 00:11.0 Class 0601: Unknown device 1106:3227 00:11.5 Class 0401: Unknown device 1106:3059 (rev 60) 00:12.0 Class 0200: Unknown device 1106:3065 (rev 78) 01:00.0 Class 0300: Unknown device 1106:3344 (rev 01) root@STC:~$ dmidecode # dmidecode 2.9 SMBIOS 2.3 present. 34 structures occupying 984 bytes. Table at 0x000F0000. Handle 0x0000, DMI type 0, 20 bytes BIOS Information Vendor: Phoenix Technologies, LTD Version: 6.00 PG Release Date: 09/15/2006 Address: 0xE0000 Runtime Size: 128 kB ROM Size: 512 kB Characteristics: ISA is supported PCI is supported PNP is supported APM is supported BIOS is upgradeable BIOS shadowing is allowed Boot from CD is supported Selectable boot is supported BIOS ROM is socketed EDD is supported 5.25"/360 KB floppy services are supported (int 13h) 5.25"/1.2 MB floppy services are supported (int 13h) 3.5"/720 KB floppy services are supported (int 13h) 3.5"/2.88 MB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) ACPI is supported USB legacy is supported AGP is supported LS-120 boot is supported ATAPI Zip drive boot is supported BIOS boot specification is supported Handle 0x0001, DMI type 1, 25 bytes System Information Manufacturer: Product Name: Version: Serial Number: UUID: Not Present Wake-up Type: Power Switch Handle 0x0002, DMI type 177, 69 bytes OEM-specific Type Header and Data: B1 45 02 00 00 30 18 AB 97 D8 01 00 02 01 06 11 65 30 06 11 1F 10 00 00 00 00 03 08 09 0E 03 00 40 82 73 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 Strings: VIA3177-MAC Handle 0x0003, DMI type 2, 8 bytes Base Board Information Manufacturer: Product Name: CN700-8237 Version: Serial Number: Handle 0x0004, DMI type 3, 17 bytes Chassis Information Manufacturer: Type: Desktop Lock: Not Present Version: Serial Number: Asset Tag: Boot-up State: Unknown Power Supply State: Unknown Thermal State: Unknown Security Status: Unknown OEM Information: 0x00000000 Handle 0x0005, DMI type 4, 35 bytes Processor Information Socket Designation: Socket 370 Type: Central Processor Family: Other Manufacturer: Intel ID: A9 06 00 00 FF BA C9 A7 Version: VIA Eden Voltage: 3.3 V External Clock: 100 MHz Max Speed: 1500 MHz Current Speed: 1200 MHz Status: Populated, Enabled Upgrade: ZIF Socket L1 Cache Handle: 0x0009 L2 Cache Handle: 0x000A L3 Cache Handle: Not Provided Serial Number: Asset Tag: Part Number: Handle 0x0006, DMI type 5, 20 bytes Memory Controller Information Error Detecting Method: None Error Correcting Capabilities: None Supported Interleave: One-way Interleave Current Interleave: Four-way Interleave Maximum Memory Module Size: 32 MB Maximum Total Memory Size: 64 MB Supported Speeds: 70 ns 60 ns Supported Memory Types: Standard EDO Memory Module Voltage: 5.0 V Associated Memory Slots: 2 0x0007 0x0008 Enabled Error Correcting Capabilities: None Handle 0x0007, DMI type 6, 12 bytes Memory Module Information Socket Designation: A0 Bank Connections: 0 Current Speed: 37 ns Type: Other Installed Size: 256 MB (Single-bank Connection) Enabled Size: 256 MB (Single-bank Connection) Error Status: OK Handle 0x0008, DMI type 6, 12 bytes Memory Module Information Socket Designation: A1 Bank Connections: None Current Speed: 37 ns Type: Other Installed Size: Not Installed Enabled Size: Not Installed Error Status: OK Handle 0x0009, DMI type 7, 19 bytes Cache Information Socket Designation: Internal Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 32 KB Maximum Size: 32 KB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Unknown System Type: Unknown Associativity: Unknown Handle 0x000A, DMI type 7, 19 bytes Cache Information Socket Designation: External Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: External Installed Size: 0 KB Maximum Size: 0 KB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Unknown System Type: Unknown Associativity: Unknown Handle 0x000B, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: PRIMARY IDE Internal Connector Type: On Board IDE External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x000C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: SECONDARY IDE Internal Connector Type: On Board IDE External Reference Designator: Not Specified External Connector Type: None Port Type: Other Handle 0x000D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: FDD Internal Connector Type: On Board Floppy External Reference Designator: Not Specified External Connector Type: None Port Type: 8251 FIFO Compatible Handle 0x000E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: COM1 Internal Connector Type: 9 Pin Dual Inline (pin 10 cut) External Reference Designator: External Connector Type: DB-9 male Port Type: Serial Port 16450 Compatible Handle 0x000F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: COM2 Internal Connector Type: 9 Pin Dual Inline (pin 10 cut) External Reference Designator: External Connector Type: DB-9 male Port Type: Serial Port 16450 Compatible Handle 0x0010, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: LPT1 Internal Connector Type: DB-25 female External Reference Designator: External Connector Type: DB-25 female Port Type: Parallel Port ECP/EPP Handle 0x0011, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Keyboard Internal Connector Type: PS/2 External Reference Designator: External Connector Type: PS/2 Port Type: Keyboard Port Handle 0x0012, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: PS/2 Mouse Internal Connector Type: PS/2 External Reference Designator: External Connector Type: PS/2 Port Type: Mouse Port Handle 0x0013, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: Not Specified Internal Connector Type: None External Reference Designator: USB0 External Connector Type: Other Port Type: USB Handle 0x0014, DMI type 9, 13 bytes System Slot Information Designation: PCI0 Type: 32-bit PCI Current Usage: Available Length: Long ID: 1 Characteristics: 5.0 V is provided PME signal is supported Handle 0x0015, DMI type 9, 13 bytes System Slot Information Designation: PCI1 Type: 32-bit PCI Current Usage: Available Length: Long ID: 2 Characteristics: 5.0 V is provided PME signal is supported Handle 0x0016, DMI type 9, 13 bytes System Slot Information Designation: PCI2 Type: 32-bit PCI Current Usage: In Use Length: Long ID: 3 Characteristics: 5.0 V is provided PME signal is supported Handle 0x0017, DMI type 9, 13 bytes System Slot Information Designation: PCI3 Type: 32-bit PCI Current Usage: Available Length: Long ID: 4 Characteristics: 5.0 V is provided PME signal is supported Handle 0x0018, DMI type 9, 13 bytes System Slot Information Designation: AGP Type: 32-bit AGP Current Usage: In Use Length: Long ID: 8 Characteristics: 5.0 V is provided Handle 0x0019, DMI type 13, 22 bytes BIOS Language Information Installable Languages: 3 n|US|iso8859-1 n|US|iso8859-1 r|CA|iso8859-1 Currently Installed Language: n|US|iso8859-1 Handle 0x001A, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 1 GB Error Information Handle: Not Provided Number Of Devices: 2 Handle 0x001B, DMI type 17, 27 bytes Memory Device Array Handle: 0x001A Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: 256 MB Form Factor: DIMM Set: None Locator: A0 Bank Locator: Bank0/1 Type: Unknown Type Detail: None Speed: Unknown Manufacturer: None Serial Number: None Asset Tag: None Part Number: None Handle 0x001C, DMI type 17, 27 bytes Memory Device Array Handle: 0x001A Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: A1 Bank Locator: Bank2/3 Type: Unknown Type Detail: None Speed: Unknown Manufacturer: None Serial Number: None Asset Tag: None Part Number: None Handle 0x001D, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0000FFFFFFF Range Size: 256 MB Physical Array Handle: 0x001A Partition Width: 0 Handle 0x001E, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0000FFFFFFF Range Size: 256 MB Physical Device Handle: 0x001B Memory Array Mapped Address Handle: 0x001D Partition Row Position: 1 Handle 0x001F, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000000003FF Range Size: 1 kB Physical Device Handle: 0x001C Memory Array Mapped Address Handle: 0x001D Partition Row Position: 1 Handle 0x0020, DMI type 32, 11 bytes System Boot Information Status: No errors detected Handle 0x0021, DMI type 127, 4 bytes End Of Table

2 1

[LinuxBIOS] uart_init hangs?
by Corey Osgood 29 Mar '07

29 Mar '07

Alright, I know I ask too many questions, but what would cause uart_init to hang? I'm trying to get serial output on ite it8705f, and my POST card tells me that it's hanging during uart_init. I've made a bunch of changes to it8705f_early_serial.c, mainly to set up serial port 1 manually, but nothing seems to help. Also, there's one small error in the last line of that file, according to the datasheet: it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02); //need to change 0x02 to 0x01 Before I "fixed" that, LB got clear to the jump to RAM (according to the POST card), but I had no serial output. Now I still have no serial output and a hang at some point during uart_init. My mainboard code is mostly a copy-and-paste of Via Epia-M, with the vga init code ripped out for now. I'm using the "normal" 115200 baud and 8-N-1 settings, and I've already checked that my serial setup is working, and according to linux, the serial header is actually COM1/ttyS0. The other question is, does anything have to be done to the via vt8235 before serial setup? Just for reference, if anyone wants them, datasheets: ITE IT8705f: http://www.iteusa.com/product_info/file/pc/IT8705F_V.0.4.1.pdf Via vt8235m: http://www.datasheetarchive.com/datasheet.php?article=3833808 Thanks, Corey

3 8

[LinuxBIOS] Intel 440FX
by Graeme Brett Houston 27 Mar '07

27 Mar '07

Hi can the 440FX chipset be supported, if so how long to implment, also what is the minimum flashrom size for Linuxbios? thanks

3 2

[LinuxBIOS] northbridge docs
by joe＠smittys.pointclark.net 27 Mar '07

27 Mar '07

Hello, I am working on the code for my northbridge (Intel 82830). Particularly the raminit.c file. By looking at the sources from the other northbridges and my datasheets, I am getting a little lost. My datasheet (Intel) lists all the registers and their defaults but doesn't really explain the memory initialization process. Could someone direct me to some good docs that explain how memory initialization happens at boot time? The more detail the better. I am using SDRAM so SDRAM specific would be great. I was looking at the code from the via vt8601, but it seems like alot of the registers are hardcoded into the code (no disrespect Ron, I saw you converted it to C). I would like to write one that is a lot more dynamic (more definitions to uniqe code) so it can also be used to as sort of a template for other SDRAM based northbridges. Thanks - Joe

6 12

[LinuxBIOS] K8T800Pro/VT8237 documentation
by Enno Fennema 27 Mar '07

27 Mar '07

Hello, I have been lurking in the background of this mailing list for a few weeks. My immediate interest is not LinuxBios but understanding the BIOS supplied with my mainboard with AMD Athlon and the above chips. Does anyone know where I can find the datasheets/docs for the above bridges. I can guess a few things about their internals but am foxed by many details of the setup. Thanks in advance, Enno Fennema

2 2

[LinuxBIOS] Intel 440bx
by Alfred Wanga 26 Mar '07

26 Mar '07

Corey Osgood wrote: > So, I commented all the do_ram_commands out (since I can't see > the problem with it) and did ram init using pci_write_config16, setting > what I know the values should be, and then NOP would not report as being > set (and ram still failed). So, I set up a for loop to set NOP until the > northbridge reported that it was set...I got an infinite loop. My loop > might be wrong (it's a bit hackish), can someone tell me if it should > work? Or does NOP simply not set? > > /* 3. Apply NOP. */ > RAM_DEBUG_MESSAGE("Ram Enable 3: Apply NOP\r\n"); > int s; > for( s = 0; s != 0110; s = pci_read_config16( ctrl->d0, SDRAMC ) ) { > RAM_DEBUG_MESSAGE("Do NOPs til it cooperates!\r\n"); > pci_write_config8(ctrl->d0, SDRAMC, 0x0110); > read32(0x04000000); > EXTRA_DELAY > } Hello Everyone, I am also new to LinuxBIOS and I've been working on porting and updating the SPD code from v1 assembly to v2. I think odinhorse's previous comment is likely to be true, although I think this is probably what he meant to say: for( s = 0; (s & 0x3ff) != 0x0110; s = pci_read_config16( ctrl->d0, SDRAMC ) ) { or: for( s = 0; s != 0x0110; s = pci_read_config16( ctrl->d0, SDRAMC ) & 0x3fff ) { I don't know which one is more correct, so whatever floats your boat. Other than that, I don't see why it wouldn't work. I don't have a suitable test system to test this with, so hope it helps! Alfred

2 1

Re: [LinuxBIOS] Intel SE440BX support
by Corey Osgood 26 Mar '07

26 Mar '07

First of all, please CC the list. Oscar Molin wrote: > I see your point there, it could be a lot of work. > But then again there are a LOT of these boards and I'm sure there is > demand for it. Yep, there is, at least for people with older hardware. Uwe and I have both been working (off and on) on support for the i440bx northbridge (on different boards, with socketed bios chips), which is required for ram initialization. Neither of us has gotten it to work, yet. I could whip off a rom that would probably give you serial output, but that's all it would ever do again. > It would mean breaking one board but I can probably get more for next to > nothing, I see them sometimes at recycling stations I would only need to > get extra flash chips that work. If you're serious about this, get the flash chips, and either find a place that does electronics work or do it yourself, but put a socket on the motherboard, you should be able to map the pins of the TSOP to a DIP32 socket, then get DIP32 chips to fit it (or better yet, an IOSS BIOS Savior). I'm sure one of the other guys on the list will correct me if I'm wrong on that. Mouser.com I've found is usually the cheapest place to get the chips/sockets, and FrozenCPU.com has BIOS Saviors, I can figure out what you need later, should you decide you want to do this. Avnet also carries BIOS chips and sockets, they might be cheaper for your needs. Once you have a socket on the mainboard, I'll go back and find my code for the FDC37C777 SuperI/O (which is as-yet untested), so maybe we can get some serial output. But understand that RAM init is still not working, so until that's working, there's no hope for a complete boot. Also, you'll probably want a POST card, if you don't have one already, these can be very handy for debugging serial output. You have to understand, right now I'm working on a PCChips M789CG, which is a board that we *already* have support for all the chips for. So far, I've done at least 30 flashes of the BIOS chip, and still haven't gotten serial output. Getting things exactly right the first time is far from easy. > That is assuming the board doesnt stall when you try to hotswap the > chips to reflash. > I'm not very knowledgable on how linuxbios works exactly when flashing, > but all these boards have a emergency boot block on them that you can > access with a floppy drive and it supports ISA videocards also. > I have one somewhere that I remember works (videocard that is). > If linuxbios doesnt overwrite the boot block area, that would make > things a lot easier aswell. Linuxbios does overwrite the boot block, so dualbios/backup bios/bios failsafe systems are all useless, for now. In the future, we *may* have support for dual-bios systems (where there are two physical bios chips on the board) from vendors like gigabyte, but so far it's been just talk. > If you feel like it, you could try and make some bare minimum bios for > me and I will try it out on the board I dislike the most. > Send me an email if you want to know chip models and such I already have all the info I need, I'm looking at one of mine right now ;) I don't have the hardware skills to replace the bios though, and I already have another 440bx development board. -Corey P.S. Sorry if I seem a bit cranky, it's another monday night with no Heroes :-(

1 0

[LinuxBIOS] Summer of Code: Last chance!
by Carl-Daniel Hailfinger 26 Mar '07

26 Mar '07

Hi, the submission deadline is approaching fast and maybe some people are still not sure what project idea to pick. You surely have read the list of projects by now. http://linuxbios.org/GSoC One more idea (not yet in the wiki) is mentioned in the mail quoted below: On 22.03.2007 15:35, Carl-Daniel Hailfinger wrote: > On 22.03.2007 15:24, Stefan Reinauer wrote: >> > * Anton <anton.borisov(a)gmail.com> [070322 15:22]: >>> >> On Thu, 22 Mar 2007 15:16:42 +0100 >>> >> Stefan Reinauer <stepan(a)coresystems.de> wrote: >>> >> >>>> >>> * Stefan Reinauer <stepan(a)openbios.org> [070322 15:08]: >>>>> >>>> This is a structure found in every award bios image >>>> >>> A similar structure is found in ASUS branden bioses. Look at >>>> >>> ASUSBIOS.PAS in uniflash >>> >> Feature of which could be possibly incorporated into flashrom, in order >>> >> not to have stuck system while detecting flash-chip (on ASUS boards). >> > >> > Yes. This should work. The one disadvantage is that it stops working as >> > soon as you flashed linuxbios for the first time, because it does not >> > provide that information. >> > >> > (Maybe it should, btw, when we want to save configuration stuff in a >> > flash block?) > > Why not use an extra utility for this (detect_flash_enable_strategy)? > > # ./detect_flash_enable_strategy > Performing PCI and SuperIO config space dump 1... > Calling Flash enable hooks in proprietary BIOS.... > Performing PCI and SuperIO config space dump 2... > Diffing dumps... > PCI config space byte 0x13 of device 00:1e.0 changed from 0x20 to 0x30 > Please mail the above information with lspci -nv and a description > of your mainboard to linuxbios(a)linuxbios.org. If you implement a utility which automatically determines the flash enable strategy for a mainboard by analyzing the vendor BIOS and calling the flash enable hooks in the proprietary BIOS with lrmi or another vm86 wrapper, you have a really good project idea and good chances. Regards, Carl-Daniel

1 0

[LinuxBIOS] Silly Question
by joe＠smittys.pointclark.net 26 Mar '07

26 Mar '07

This is a silly question but, when I see something like this (2<<20) in raminit.c it is saying to change bit 20 to a value of 2?? Is that correct?? That would have to be a binary value than right? Than what would that look like?? Just trying to understand the whole registry setting thing better. Thanks - Joe

2 2

← Newer
1
2
3
4
5
6
7
8
9
...
23
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2007