coreboot November 2007

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[LinuxBIOS] r2929 - in trunk/LinuxBIOSv2: src/mainboard/ibm/e325 src/mainboard/ibm/e326 targets/ibm/e326
by svn＠openbios.org 02 Nov '07

02 Nov '07

Author: stepan Date: 2007-11-02 13:35:30 +0100 (Fri, 02 Nov 2007) New Revision: 2929 Added: trunk/LinuxBIOSv2/src/mainboard/ibm/e325/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/ibm/e326/cache_as_ram_auto.c trunk/LinuxBIOSv2/targets/ibm/e326/Config.lb Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Config.lb trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Options.lb trunk/LinuxBIOSv2/src/mainboard/ibm/e325/auto.c trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Config.lb trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Options.lb trunk/LinuxBIOSv2/src/mainboard/ibm/e326/auto.c Log: fix up IBM servers. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Config.lb 2007-11-02 11:06:40 UTC (rev 2928) +++ trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Config.lb 2007-11-02 12:35:30 UTC (rev 2929) @@ -47,6 +47,26 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o +if USE_DCACHE_RAM + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end +else ## ## Romcc output ## @@ -69,14 +89,28 @@ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end +end + ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## -mainboardinit cpu/x86/16bit/entry16.inc +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds +end + mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end + ## ## Build our reset vector (This is where linuxBIOS is entered) ## @@ -88,8 +122,11 @@ ldscript /cpu/x86/32bit/reset32.lds end +if USE_DCACHE_RAM +else ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc +end ## ## Include an id string (For safe flashing) @@ -97,15 +134,26 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc end +end ### ### O.k. We aren't just an intermediary anymore! @@ -114,17 +162,30 @@ ## ## Setup RAM ## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else + +## +## Setup RAM +## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc mainboardinit ./auto.inc mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc +end ## ## Include the secondary Configuration files ## -dir /pc80 config chip.h Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Options.lb 2007-11-02 11:06:40 UTC (rev 2928) +++ trunk/LinuxBIOSv2/src/mainboard/ibm/e325/Options.lb 2007-11-02 12:35:30 UTC (rev 2929) @@ -44,7 +44,9 @@ uses CC uses HOSTCC uses OBJCOPY - +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT @@ -110,6 +112,14 @@ default CONFIG_IOAPIC=1 ## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcf000 +default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=0 + +## ## Clean up the motherboard id strings ## default MAINBOARD_PART_NUMBER="E325" Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e325/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/ibm/e325/auto.c 2007-11-02 11:06:40 UTC (rev 2928) +++ trunk/LinuxBIOSv2/src/mainboard/ibm/e325/auto.c 2007-11-02 12:35:30 UTC (rev 2929) @@ -66,50 +66,6 @@ } } -static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) -{ - /* Routing Table Node i - * - * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c - * i: 0, 1, 2, 3, 4, 5, 6, 7 - * - * [ 0: 3] Request Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [11: 8] Response Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [19:16] Broadcast route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - */ - - uint32_t ret = 0x00010101; /* default row entry */ - - static const unsigned int rows_2p[2][2] = { - { 0x00090101, 0x00010808 }, - { 0x00010808, 0x00090101 } - }; - - if (maxnodes > 2) { - print_debug("this mainboard is only designed for 2 cpus\r\n"); - maxnodes = 2; - } - - - if (!(node >= maxnodes || row >= maxnodes)) { - ret = rows_2p[node][row]; - } - - return ret; -} - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ Added: trunk/LinuxBIOSv2/src/mainboard/ibm/e325/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/ibm/e325/cache_as_ram_auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/ibm/e325/cache_as_ram_auto.c 2007-11-02 12:35:30 UTC (rev 2929) @@ -0,0 +1,218 @@ +#define ASSEMBLY 1 +#define __ROMCC__ + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" + +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" + +#if CONFIG_USE_INIT == 0 +#include "lib/memcpy.c" +#endif + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/nsc/pc87366/pc87366_early_serial.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1) + +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" + +static void memreset_setup(void) +{ + if (is_cpu_pre_c0()) { + /* Set the memreset low */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); + /* Ensure the BIOS has control of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + } else { + /* Ensure the CPU has controll of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); + } +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ + if (is_cpu_pre_c0()) { + udelay(800); + /* Set memreset_high */ + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); + udelay(90); + } +} + + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#define QRANK_DIMM_SUPPORT 1 + +#include "northbridge/amd/amdk8/raminit.c" +#include "resourcemap.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "sdram/generic_sdram.c" + +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif +#include "cpu/amd/dualcore/dualcore.c" + +#define FIRST_CPU 1 +#define SECOND_CPU 1 +#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) + +#include "cpu/amd/car/copy_and_run.c" + +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" + + +#if USE_FALLBACK_IMAGE == 1 + +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + unsigned last_boot_normal_x = last_boot_normal(); + + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ + ); + + fallback_image: + ; +} +#endif + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + +#if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); +#endif + real_main(bist, cpu_init_detectedx); + +} + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const struct mem_controller cpu[] = { + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x18, 0), + .f1 = PCI_DEV(0, 0x18, 1), + .f2 = PCI_DEV(0, 0x18, 2), + .f3 = PCI_DEV(0, 0x18, 3), + .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, + .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + }, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + { + .node_id = 1, + .f0 = PCI_DEV(0, 0x19, 0), + .f1 = PCI_DEV(0, 0x19, 1), + .f2 = PCI_DEV(0, 0x19, 2), + .f3 = PCI_DEV(0, 0x19, 3), + .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, + .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + }, +#endif + }; + + int needs_reset; + + if (bist == 0) { + init_cpus(cpu_init_detectedx); + } + + pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + setup_ibm_e325_resource_map(); + + needs_reset = setup_coherent_ht_domain(); + +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + start_other_cores(); +#endif + // automatically set that for you, but you might meet tight space + needs_reset |= ht_setup_chains_x(); + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + enable_smbus(); + + memreset_setup(); + sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + + post_cache_as_ram(); + +} Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Config.lb 2007-11-02 11:06:40 UTC (rev 2928) +++ trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Config.lb 2007-11-02 12:35:30 UTC (rev 2929) @@ -47,6 +47,26 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o +if USE_DCACHE_RAM + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end +else ## ## Romcc output ## @@ -69,14 +89,28 @@ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end +end + ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## -mainboardinit cpu/x86/16bit/entry16.inc +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds +end + mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end + ## ## Build our reset vector (This is where linuxBIOS is entered) ## @@ -88,8 +122,11 @@ ldscript /cpu/x86/32bit/reset32.lds end +if USE_DCACHE_RAM +else ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc +end ## ## Include an id string (For safe flashing) @@ -97,15 +134,26 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc end +end ### ### O.k. We aren't just an intermediary anymore! @@ -114,17 +162,30 @@ ## ## Setup RAM ## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else + +## +## Setup RAM +## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc mainboardinit ./auto.inc mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc +end ## ## Include the secondary Configuration files ## -dir /pc80 config chip.h Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Options.lb 2007-11-02 11:06:40 UTC (rev 2928) +++ trunk/LinuxBIOSv2/src/mainboard/ibm/e326/Options.lb 2007-11-02 12:35:30 UTC (rev 2929) @@ -46,7 +46,9 @@ uses OBJCOPY uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN - +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT @@ -116,6 +118,14 @@ default CONFIG_PCI_ROM_RUN=1 ## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcf000 +default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=0 + +## ## Clean up the motherboard id strings ## default MAINBOARD_PART_NUMBER="E326" Modified: trunk/LinuxBIOSv2/src/mainboard/ibm/e326/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/ibm/e326/auto.c 2007-11-02 11:06:40 UTC (rev 2928) +++ trunk/LinuxBIOSv2/src/mainboard/ibm/e326/auto.c 2007-11-02 12:35:30 UTC (rev 2929) @@ -66,50 +66,6 @@ } } -static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) -{ - /* Routing Table Node i - * - * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c - * i: 0, 1, 2, 3, 4, 5, 6, 7 - * - * [ 0: 3] Request Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [11: 8] Response Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [19:16] Broadcast route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - */ - - uint32_t ret = 0x00010101; /* default row entry */ - - /* CPU0 LDT2 <-> LDT2 CPU1 */ - static const unsigned int rows_2p[2][2] = { - { 0x00090101, 0x00010808 }, - { 0x00010808, 0x00090101 } - }; - - if (maxnodes > 2) { - print_debug("this mainboard is only designed for 2 cpus\r\n"); - maxnodes = 2; - } - - if (!(node >= maxnodes || row >= maxnodes)) { - ret = rows_2p[node][row]; - } - - return ret; -} - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ Added: trunk/LinuxBIOSv2/src/mainboard/ibm/e326/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/ibm/e326/cache_as_ram_auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/ibm/e326/cache_as_ram_auto.c 2007-11-02 12:35:30 UTC (rev 2929) @@ -0,0 +1,218 @@ +#define ASSEMBLY 1 +#define __ROMCC__ + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" + +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" + +#if CONFIG_USE_INIT == 0 +#include "lib/memcpy.c" +#endif + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/nsc/pc87366/pc87366_early_serial.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1) + +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" + +static void memreset_setup(void) +{ + if (is_cpu_pre_c0()) { + /* Set the memreset low */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); + /* Ensure the BIOS has control of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + } else { + /* Ensure the CPU has controll of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); + } +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ + if (is_cpu_pre_c0()) { + udelay(800); + /* Set memreset_high */ + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); + udelay(90); + } +} + + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#define QRANK_DIMM_SUPPORT 1 + +#include "northbridge/amd/amdk8/raminit.c" +#include "resourcemap.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "sdram/generic_sdram.c" + +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif +#include "cpu/amd/dualcore/dualcore.c" + +#define FIRST_CPU 1 +#define SECOND_CPU 1 +#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) + +#include "cpu/amd/car/copy_and_run.c" + +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" + + +#if USE_FALLBACK_IMAGE == 1 + +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + unsigned last_boot_normal_x = last_boot_normal(); + + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ + ); + + fallback_image: + ; +} +#endif + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + +#if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); +#endif + real_main(bist, cpu_init_detectedx); + +} + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const struct mem_controller cpu[] = { + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x18, 0), + .f1 = PCI_DEV(0, 0x18, 1), + .f2 = PCI_DEV(0, 0x18, 2), + .f3 = PCI_DEV(0, 0x18, 3), + .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, + .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + }, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + { + .node_id = 1, + .f0 = PCI_DEV(0, 0x19, 0), + .f1 = PCI_DEV(0, 0x19, 1), + .f2 = PCI_DEV(0, 0x19, 2), + .f3 = PCI_DEV(0, 0x19, 3), + .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, + .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + }, +#endif + }; + + int needs_reset; + + if (bist == 0) { + init_cpus(cpu_init_detectedx); + } + + pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + setup_ibm_e326_resource_map(); + + needs_reset = setup_coherent_ht_domain(); + +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + start_other_cores(); +#endif + // automatically set that for you, but you might meet tight space + needs_reset |= ht_setup_chains_x(); + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + enable_smbus(); + + memreset_setup(); + sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + + post_cache_as_ram(); + +} Added: trunk/LinuxBIOSv2/targets/ibm/e326/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/ibm/e326/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/ibm/e326/Config.lb 2007-11-02 12:35:30 UTC (rev 2929) @@ -0,0 +1,30 @@ +# the IBM E326 +# This will make a target directory of ./e326 + +target e326 +mainboard ibm/e326 + +### +### Compute the start location and size size of +### The linuxBIOS bootloader. +### + +romimage "normal" + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x20000 + option LINUXBIOS_EXTRA_VERSION=".0Normal" +# payload ../../filo.elf + payload ../../../payloads/filo.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option LINUXBIOS_EXTRA_VERSION=".0Fallback" +# payload ../../filo.elf + payload ../../../payloads/filo.elf +# use this to test a build if you don't have the etherboot +# payload /etc/hosts +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

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[LinuxBIOS] r2927 build service
by LinuxBIOS information 02 Nov '07

02 Nov '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2927 to the LinuxBIOS source repository and caused the following changes: Change Log: fix juki 511p abuild by adding a Config-abuild.lb. (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2927&device=hdama&vendor=… Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2927&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2927&device=e326&vendor=i… Compilation of iei:juki-511p has been fixed Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2927&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2927&device=dk8x&vendor=i… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] M57SLI interrupt routing
by Torsten Duwe 02 Nov '07

02 Nov '07

irqpoll rulez !-) With this kernel option I get full performance from glxgears, but the interrupts show up under the driver for the only working PCI slot, not the primary PCIe! Looking at the board layout I see that this one is exactly 4 slots further -- maybe Gigabyte did the classic INT rotation over all slots? I cannot pursue this further right now, this is just a quick note, in case someone has a naked board and a multimeter handy :) Torsten

1 0

[LinuxBIOS] r2928 - trunk/LinuxBIOSv2/src/mainboard/arima/hdama
by svn＠openbios.org 02 Nov '07

02 Nov '07

Author: stepan Date: 2007-11-02 12:06:40 +0100 (Fri, 02 Nov 2007) New Revision: 2928 Added: trunk/LinuxBIOSv2/src/mainboard/arima/hdama/cache_as_ram_auto.c Modified: trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Config.lb trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Options.lb trunk/LinuxBIOSv2/src/mainboard/arima/hdama/auto.c Log: get arima hdama building again. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Config.lb 2007-11-02 10:36:15 UTC (rev 2927) +++ trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Config.lb 2007-11-02 11:06:40 UTC (rev 2928) @@ -46,6 +46,26 @@ if HAVE_MP_TABLE object mptable.o end if HAVE_PIRQ_TABLE object irq_tables.o end +if USE_DCACHE_RAM + +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end +else ## ## Romcc output ## @@ -68,14 +88,28 @@ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end +end + ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## -mainboardinit cpu/x86/16bit/entry16.inc +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds +end + mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end + ## ## Build our reset vector (This is where linuxBIOS is entered) ## @@ -87,8 +121,11 @@ ldscript /cpu/x86/32bit/reset32.lds end +if USE_DCACHE_RAM +else ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc +end ## ## Include an id string (For safe flashing) @@ -96,15 +133,26 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc end +end ### ### O.k. We aren't just an intermediary anymore! @@ -113,17 +161,30 @@ ## ## Setup RAM ## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else + +## +## Setup RAM +## mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc mainboardinit ./auto.inc mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc +end ## ## Include the secondary Configuration files ## -dir /pc80 config chip.h # config for arima/hdama Modified: trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Options.lb 2007-11-02 10:36:15 UTC (rev 2927) +++ trunk/LinuxBIOSv2/src/mainboard/arima/hdama/Options.lb 2007-11-02 11:06:40 UTC (rev 2928) @@ -51,7 +51,9 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses CONFIG_LOGICAL_CPUS - +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT ### @@ -120,6 +122,14 @@ ## default CONFIG_IOAPIC=1 +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcf000 +default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=0 + #VGA default CONFIG_CONSOLE_VGA=1 default CONFIG_PCI_ROM_RUN=1 Modified: trunk/LinuxBIOSv2/src/mainboard/arima/hdama/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/arima/hdama/auto.c 2007-11-02 10:36:15 UTC (rev 2927) +++ trunk/LinuxBIOSv2/src/mainboard/arima/hdama/auto.c 2007-11-02 11:06:40 UTC (rev 2928) @@ -83,50 +83,6 @@ } } -static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) -{ - /* Routing Table Node i - * - * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c - * i: 0, 1, 2, 3, 4, 5, 6, 7 - * - * [ 0: 3] Request Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [11: 8] Response Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - * [19:16] Broadcast route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 - */ - - uint32_t ret = 0x00010101; /* default row entry */ - - /* CPU0 LDT1 <-> LDT1 CPU1 */ - static const unsigned int rows_2p[2][2] = { - { 0x00050101, 0x00010404 }, - { 0x00010404, 0x00050101 } - }; - - if (maxnodes > 2) { - print_spew("this mainboard is only designed for 2 cpus\r\n"); - maxnodes = 2; - } - - if (!(node >= maxnodes || row >= maxnodes)) { - ret = rows_2p[node][row]; - } - - return ret; -} - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ Added: trunk/LinuxBIOSv2/src/mainboard/arima/hdama/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/arima/hdama/cache_as_ram_auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/arima/hdama/cache_as_ram_auto.c 2007-11-02 11:06:40 UTC (rev 2928) @@ -0,0 +1,222 @@ +#define ASSEMBLY 1 +#define __ROMCC__ + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" + +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" + +#if CONFIG_USE_INIT == 0 +#include "lib/memcpy.c" +#endif + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/nsc/pc87360/pc87360_early_serial.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) + +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" + +/* + * GPIO28 of 8111 will control H0_MEMRESET_L + * GPIO29 of 8111 will control H1_MEMRESET_L + */ +static void memreset_setup(void) +{ + if (is_cpu_pre_c0()) { + /* Set the memreset low */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); + } + else { + /* Ensure the CPU has controll of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); + } +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ + if (is_cpu_pre_c0()) { + udelay(800); + /* Set memreset_high */ + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + udelay(90); + } +} + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#define QRANK_DIMM_SUPPORT 1 + +#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/resourcemap.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "sdram/generic_sdram.c" + +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif +#include "cpu/amd/dualcore/dualcore.c" + +#define FIRST_CPU 1 +#define SECOND_CPU 1 +#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) + +#include "cpu/amd/car/copy_and_run.c" + +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" + + +#if USE_FALLBACK_IMAGE == 1 + +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + unsigned last_boot_normal_x = last_boot_normal(); + + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) , "b" (cpu_init_detectedx) /* inputs */ + ); + + fallback_image: + ; +} +#endif + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + +#if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); +#endif + real_main(bist, cpu_init_detectedx); + +} + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const struct mem_controller cpu[] = { + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x18, 0), + .f1 = PCI_DEV(0, 0x18, 1), + .f2 = PCI_DEV(0, 0x18, 2), + .f3 = PCI_DEV(0, 0x18, 3), + .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, + .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + }, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + { + .node_id = 1, + .f0 = PCI_DEV(0, 0x19, 0), + .f1 = PCI_DEV(0, 0x19, 1), + .f2 = PCI_DEV(0, 0x19, 2), + .f3 = PCI_DEV(0, 0x19, 3), + .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, + .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + }, +#endif + }; + + int needs_reset; + + if (bist == 0) { + init_cpus(cpu_init_detectedx); + } + + pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + setup_default_resource_map(); + + needs_reset = setup_coherent_ht_domain(); + +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + start_other_cores(); +#endif + // automatically set that for you, but you might meet tight space + needs_reset |= ht_setup_chains_x(); + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + enable_smbus(); + + memreset_setup(); + sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + + post_cache_as_ram(); + +}

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[LinuxBIOS] r2926 build service
by LinuxBIOS information 02 Nov '07

02 Nov '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2926 to the LinuxBIOS source repository and caused the following changes: Change Log: This patch fixes the superio of the khepri 2100e as detected: > superiotool r2922 > Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x0d) at 0x2e Don't use the non-working trident driver for the blade3d (onboard vga in the rom emulator has not been tested either) It also adds some preliminary CAR support to the board, so it has a chance to build again. This board was broken since a couple of months, and the changes are minimal, so I consider this a trivial change -- It doesn't change anything that was used, obviously Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2926&device=hdama&vendor=… Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2926&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2926&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2926&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2926&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2926&device=dk8x&vendor=i… Compilation of newisys:khepri has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] r2927 - trunk/LinuxBIOSv2/targets/iei/juki-511p
by svn＠openbios.org 02 Nov '07

02 Nov '07

Author: stepan Date: 2007-11-02 11:36:15 +0100 (Fri, 02 Nov 2007) New Revision: 2927 Added: trunk/LinuxBIOSv2/targets/iei/juki-511p/Config-abuild.lb Log: fix juki 511p abuild by adding a Config-abuild.lb. (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/LinuxBIOSv2/targets/iei/juki-511p/Config-abuild.lb =================================================================== --- trunk/LinuxBIOSv2/targets/iei/juki-511p/Config-abuild.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/iei/juki-511p/Config-abuild.lb 2007-11-02 10:36:15 UTC (rev 2927) @@ -0,0 +1,29 @@ +# abuild config file for JUKI-511P + +target iei_juki-511p +mainboard iei/juki-511p + +__COMPRESSION__ + +option ROM_SIZE=256*1024 +### +### Compute the location and size of where this firmware image +### (linuxBIOS plus bootloader) will live in the boot rom chip. +### +option FALLBACK_SIZE=128*1024 + +romimage "normal" + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=64*1024 + option LINUXBIOS_EXTRA_VERSION=".0-Normal" + payload __PAYLOAD__ +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=64*1024 + option LINUXBIOS_EXTRA_VERSION=".0-Fallback" + payload __PAYLOAD__ +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

1 0

[LinuxBIOS] r2926 - trunk/LinuxBIOSv2/src/mainboard/newisys/khepri
by svn＠openbios.org 02 Nov '07

02 Nov '07

Author: stepan Date: 2007-11-02 10:48:14 +0100 (Fri, 02 Nov 2007) New Revision: 2926 Added: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/cache_as_ram_auto.c Modified: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c Log: This patch fixes the superio of the khepri 2100e as detected: > superiotool r2922 > Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x0d) at 0x2e Don't use the non-working trident driver for the blade3d (onboard vga in the rom emulator has not been tested either) It also adds some preliminary CAR support to the board, so it has a chance to build again. This board was broken since a couple of months, and the changes are minimal, so I consider this a trivial change -- It doesn't change anything that was used, obviously Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb 2007-11-02 00:31:11 UTC (rev 2925) +++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Config.lb 2007-11-02 09:48:14 UTC (rev 2926) @@ -47,8 +47,27 @@ if HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -dir /drivers/trident/blade3d +if USE_DCACHE_RAM +if CONFIG_USE_INIT + +makerule ./auto.o + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" +end + +else + +makerule ./auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" +end + +end +else + ## ## Romcc output ## @@ -71,14 +90,28 @@ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" end +end + ## ## Build our 16 bit and 32 bit linuxBIOS entry code ## -mainboardinit cpu/x86/16bit/entry16.inc +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/entry16.inc + ldscript /cpu/x86/16bit/entry16.lds +end + mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds +if USE_DCACHE_RAM + if CONFIG_USE_INIT + ldscript /cpu/x86/32bit/entry32.lds + end + + if CONFIG_USE_INIT + ldscript /cpu/amd/car/cache_as_ram.lds + end +end + ## ## Build our reset vector (This is where linuxBIOS is entered) ## @@ -91,23 +124,36 @@ end ### Should this be in the northbridge code? +if USE_DCACHE_RAM +else mainboardinit arch/i386/lib/cpu_reset.inc - +end ## ## Include an id string (For safe flashing) ## mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds +if USE_DCACHE_RAM +## +## Setup Cache-As-Ram +## +mainboardinit cpu/amd/car/cache_as_ram.inc +end + ### ### This is the early phase of linuxBIOS startup ### Things are delicate and we test to see if we should ### failover to another image. ### if USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds +if USE_DCACHE_RAM + ldscript /arch/i386/lib/failover.lds +else + ldscript /arch/i386/lib/failover.lds mainboardinit ./failover.inc end +end ### ### O.k. We aren't just an intermediary anymore! @@ -116,6 +162,20 @@ ## ## Setup RAM ## +if USE_DCACHE_RAM + +if CONFIG_USE_INIT +initobject auto.o +else +mainboardinit ./auto.inc +end + +else + +## +## Setup RAM +## + mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/sse/enable_sse.inc @@ -123,13 +183,22 @@ mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/mmx/disable_mmx.inc -## -## Include the secondary Configuration files -## -dir /pc80 +end + config chip.h +# FIXME: ROM for onboard VGA + chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + chip cpu/amd/socket_940 + device apic 1 on end + end + end + device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on end # LDT 0 @@ -148,36 +217,45 @@ device pci 1.0 on end end device pci 1.0 on - chip superio/nsc/pc87360 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT - + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end end end device pci 1.1 on end @@ -201,13 +279,5 @@ device pci 19.3 on end end end - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - chip cpu/amd/socket_940 - device apic 1 on end - end - end end Modified: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb 2007-11-02 00:31:11 UTC (rev 2925) +++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/Options.lb 2007-11-02 09:48:14 UTC (rev 2926) @@ -7,6 +7,7 @@ uses HAVE_OPTION_TABLE uses CONFIG_MAX_CPUS uses CONFIG_MAX_PHYSICAL_CPUS +uses CONFIG_LOGICAL_CPUS uses CONFIG_IOAPIC uses CONFIG_SMP uses FALLBACK_SIZE @@ -18,6 +19,7 @@ uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD uses PAYLOAD_SIZE uses _ROMBASE uses XIP_ROM_SIZE @@ -31,6 +33,8 @@ uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses MAINBOARD +uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID +uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses LINUXBIOS_EXTRA_VERSION uses _RAMBASE uses TTYS0_BAUD @@ -40,11 +44,20 @@ uses MAXIMUM_CONSOLE_LOGLEVEL uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL uses CONFIG_CONSOLE_SERIAL8250 +uses HAVE_INIT_TIMER +uses CONFIG_GDB_STUB uses CROSS_COMPILE uses CC uses HOSTCC uses OBJCOPY +uses CONFIG_CHIP_NAME +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses HW_MEM_HOLE_SIZEK +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE uses CONFIG_USE_INIT ### @@ -59,6 +72,8 @@ ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## +#default FALLBACK_SIZE=131072 +#256K default FALLBACK_SIZE=0x40000 ## @@ -75,7 +90,7 @@ ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=9 +default IRQ_SLOT_COUNT=15 ## ## Build code to export an x86 MP table @@ -100,10 +115,30 @@ ## Only worry about 2 micro processors ## default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 +default CONFIG_MAX_CPUS=4 default CONFIG_MAX_PHYSICAL_CPUS=2 +default CONFIG_LOGICAL_CPUS=1 +#CHIP_NAME ? +default CONFIG_CHIP_NAME=1 + +#1G memory hole +default HW_MEM_HOLE_SIZEK=0x100000 + +#VGA Console +default CONFIG_CONSOLE_VGA=1 +default CONFIG_PCI_ROM_RUN=1 + + ## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xcf000 +default DCACHE_RAM_SIZE=0x1000 +default CONFIG_USE_INIT=0 + +## ## Build code to setup a generic IOAPIC ## default CONFIG_IOAPIC=1 @@ -113,6 +148,8 @@ ## default MAINBOARD_PART_NUMBER="Khepri" default MAINBOARD_VENDOR="Newisys" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010 ### ### LinuxBIOS layout values @@ -157,6 +194,11 @@ default HOSTCC="gcc" ## +## Disable the gdb stub by default +## +default CONFIG_GDB_STUB=0 + +## ## The Serial Console ## Modified: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c 2007-11-02 00:31:11 UTC (rev 2925) +++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/auto.c 2007-11-02 09:48:14 UTC (rev 2926) @@ -19,11 +19,11 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <cpu/amd/model_fxx_rev.h> -#include "superio/nsc/pc87360/pc87360_early_serial.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/x86/bist.h" -#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) static void hard_reset(void) { @@ -115,7 +115,7 @@ k8_init_and_stop_secondaries(); } /* Setup the console */ - pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE); + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); Added: trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/cache_as_ram_auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/newisys/khepri/cache_as_ram_auto.c 2007-11-02 09:48:14 UTC (rev 2926) @@ -0,0 +1,249 @@ +/* + * This code is derived from the Tyan s2882 cache_as_ram_auto.c + * Adapted by Stefan Reinauer <stepan(a)coresystems.de> + * Additional (C) 2007 coresystems GmbH + */ +#define ASSEMBLY 1 +#define __ROMCC__ + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" + +#if 0 +static void post_code(uint8_t value) { +#if 1 + int i; + for(i=0;i<0x80000;i++) { + outb(value, 0x80); + } +#endif +} +#endif + +#include <cpu/amd/model_fxx_rev.h> + +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" + +#if CONFIG_USE_INIT == 0 +#include "lib/memcpy.c" +#endif + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" + +static void memreset_setup(void) +{ + if (is_cpu_pre_c0()) { + /* Set the memreset low */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); + } + else { + /* Ensure the CPU has controll of the memory lines */ + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); + } +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ + if (is_cpu_pre_c0()) { + udelay(800); + /* Set memreset_high */ + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + udelay(90); + } +} + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#define QRANK_DIMM_SUPPORT 1 + +#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "sdram/generic_sdram.c" + + /* newisys khepri does not want the default */ +#include "resourcemap.c" + +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif +#include "cpu/amd/dualcore/dualcore.c" + + +#include "cpu/amd/car/copy_and_run.c" + +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" + + +#if USE_FALLBACK_IMAGE == 1 + +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + unsigned last_boot_normal_x = last_boot_normal(); + + /* Is this a cpu only reset? or Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal_x) { + goto normal_image; + } else { + goto fallback_image; + } + } + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + + /* Setup the ck804 */ + amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ +// post_code(0x22); + if (bios_reset_detected() && last_boot_normal_x) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: +// post_code(0x23); + __asm__ volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ + ); + + fallback_image: +// post_code(0x25); + ; +} +#endif + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + +#if USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); +#endif + real_main(bist, cpu_init_detectedx); + +} + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr [] = { + (0xa<<3)|0, (0xa<<3)|2, 0, 0, + (0xa<<3)|1, (0xa<<3)|3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + (0xa<<3)|4, (0xa<<3)|6, 0, 0, + (0xa<<3)|5, (0xa<<3)|7, 0, 0, +#endif + }; + + int needs_reset; + unsigned bsp_apicid = 0; + + struct mem_controller ctrl[8]; + unsigned nodes; + + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx); + } + +// post_code(0x32); + + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + +// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + setup_khepri_resource_map(); +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif + + needs_reset = setup_coherent_ht_domain(); + + wait_all_core0_started(); +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + + needs_reset |= ht_setup_chains_x(); + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + + allow_all_aps_stop(bsp_apicid); + + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr); + + enable_smbus(); + + memreset_setup(); + sdram_initialize(nodes, ctrl); + +#if 0 + dump_pci_devices(); +#endif + + post_cache_as_ram(); + +}

1 0

[LinuxBIOS] dualcore trouble with LB - opteron 175
by Rudolf Marek 02 Nov '07

02 Nov '07

Hello all, I have new CPU opteron 175 - sigle cpu dualcore, I'm not able to initialize AP properly. http://assembler.cz/download/minicom_dc.txt It seems I can boot them, but they never arrive to check point. Any idea what might be wrong? Also I don't know why my core1 have APIC ID 0x11 instead of APIC ID 0x1... Any help very appreciated. Thanks, Rudolf

11 39

[LinuxBIOS] r2925 build service
by LinuxBIOS information 02 Nov '07

02 Nov '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2925 to the LinuxBIOS source repository and caused the following changes: Change Log: trivial fix for the .data problem Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=hdama&vendor=… Compilation of gigabyte:ga_2761gxdk has been fixed Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=dk8x&vendor=i… Compilation of newisys:khepri is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2925&device=khepri&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] r2925 - trunk/LinuxBIOSv2/src/southbridge/sis/sis966
by svn＠openbios.org 02 Nov '07

02 Nov '07

Author: stepan Date: 2007-11-02 01:31:11 +0100 (Fri, 02 Nov 2007) New Revision: 2925 Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c Log: trivial fix for the .data problem Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c 2007-11-01 15:15:14 UTC (rev 2924) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_early_smbus.c 2007-11-02 00:31:11 UTC (rev 2925) @@ -23,7 +23,7 @@ #define SMBUS0_IO_BASE 0x8D0 -uint8_t SiS_LPC_init[33][3]={ +static const uint8_t SiS_LPC_init[33][3]={ {0x04, 0xF8, 0x07}, //Reg 0x04 {0x45, 0x00, 0x00}, //Reg 0x45 //Enable Rom Flash {0x46, 0x00, 0x3D}, //Reg 0x46 @@ -59,7 +59,7 @@ {0xDF, 0x00, 0xAA}, //Reg 0xDF {0x00, 0x00, 0x00} //End of table }; -uint8_t SiS_NBPCIE_init[43][3]={ +static const uint8_t SiS_NBPCIE_init[43][3]={ {0x3D, 0x00, 0x00}, //Reg 0x3D {0x1C, 0xFE, 0x01}, //Reg 0x1C {0x1D, 0xFE, 0x01}, //Reg 0x1D @@ -105,7 +105,7 @@ {0x4F, 0x00, 0x00}, //Reg 0x4F {0x00, 0x00, 0x00} //End of table }; -uint8_t SiS_ACPI_init[10][3]={ +static const uint8_t SiS_ACPI_init[10][3]={ {0x1B, 0xBF, 0x40}, //Reg 0x1B {0x84, 0x00, 0x0E}, //Reg 0x84 {0x85, 0x00, 0x29}, //Reg 0x85 @@ -117,7 +117,7 @@ {0x6F, 0xFF, 0x14}, //Reg 0x6F {0x00, 0x00, 0x00} //End of table }; -uint8_t SiS_SBPCIE_init[13][3]={ +static const uint8_t SiS_SBPCIE_init[13][3]={ {0x48, 0x00 ,0x07}, //Reg 0x48 {0x49, 0x00 ,0x06}, //Reg 0x49 {0x4A, 0x00 ,0x0C}, //Reg 0x4A @@ -135,7 +135,7 @@ #if 1 -uint8_t SiS_NB_init[56][3]={ +static const uint8_t SiS_NB_init[56][3]={ {0x04, 0x00 ,0x07}, //Reg 0x04 {0x05, 0x00 ,0x00}, //Reg 0x05 // alex {0x0D, 0x00 ,0x20}, //Reg 0x0D @@ -201,7 +201,7 @@ }; #else -uint8_t SiS_NB_init[61][3]={ +static const uint8_t SiS_NB_init[61][3]={ {0x04, 0x00 ,0x07}, //Reg 0x04 {0x05, 0x00 ,0x00}, //Reg 0x05 // alex {0x0D, 0x00 ,0x20}, //Reg 0x0D @@ -270,7 +270,7 @@ #endif #if 1 -uint8_t SiS_NBAGP_init[34][3]={ +static const uint8_t SiS_NBAGP_init[34][3]={ {0xCF, 0xDF, 0x00}, //HT issue {0x06, 0xDF, 0x20}, {0x1E, 0xDF, 0x20}, @@ -314,7 +314,7 @@ #else //uint8_t SiS_NBAGP_init[53][3]={ -uint8_t SiS_NBAGP_init[40][3]={ +static const uint8_t SiS_NBAGP_init[40][3]={ {0x04, 0x00 ,0x07}, //Reg 0x04 {0x05, 0x00 ,0x01}, //Reg 0x05 // alex @@ -381,7 +381,7 @@ #endif -uint8_t SiS_ACPI_2_init[56][3]={ +static const uint8_t SiS_ACPI_2_init[56][3]={ {0x00, 0x00, 0xFF}, //Reg 0x00 {0x01, 0x00, 0xFF}, //Reg 0x01 {0x02, 0x00, 0x00}, //Reg 0x02 @@ -441,7 +441,7 @@ }; #if 0 -uint8_t SiS_SiS1183_init[60][3]={ +static const uint8_t SiS_SiS1183_init[60][3]={ {0x04, 0x00, 0x05}, {0x09, 0x00, 0x05}, {0x2C, 0x00, 0x39}, @@ -511,7 +511,7 @@ #else -uint8_t SiS_SiS1183_init[44][3]={ +static const uint8_t SiS_SiS1183_init[44][3]={ {0x04, 0x00, 0x05}, {0x09, 0x00, 0x05}, {0x2C, 0x00, 0x39},

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coreboot November 2007