coreboot November 2007

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[LinuxBIOS] r525 - in LinuxBIOSv3/mainboard/pcengines: . alix1c
by svn＠openbios.org 27 Nov '07

27 Nov '07

Author: rminnich Date: 2007-11-27 17:19:34 +0100 (Tue, 27 Nov 2007) New Revision: 525 Modified: LinuxBIOSv3/mainboard/pcengines/Kconfig LinuxBIOSv3/mainboard/pcengines/alix1c/Makefile LinuxBIOSv3/mainboard/pcengines/alix1c/dts LinuxBIOSv3/mainboard/pcengines/alix1c/initram.c LinuxBIOSv3/mainboard/pcengines/alix1c/stage1.c Log: This gets as far as pll_reset and dies. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: LinuxBIOSv3/mainboard/pcengines/Kconfig =================================================================== --- LinuxBIOSv3/mainboard/pcengines/Kconfig 2007-11-27 14:44:54 UTC (rev 524) +++ LinuxBIOSv3/mainboard/pcengines/Kconfig 2007-11-27 16:19:34 UTC (rev 525) @@ -30,6 +30,7 @@ select OPTION_TABLE select NORTHBRIDGE_AMD_GEODELX select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF help PC Engines ALIX1.C. Modified: LinuxBIOSv3/mainboard/pcengines/alix1c/Makefile =================================================================== --- LinuxBIOSv3/mainboard/pcengines/alix1c/Makefile 2007-11-27 14:44:54 UTC (rev 524) +++ LinuxBIOSv3/mainboard/pcengines/alix1c/Makefile 2007-11-27 16:19:34 UTC (rev 525) @@ -21,9 +21,8 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ +INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ $(obj)/northbridge/amd/geodelx/raminit.o \ - $(obj)/southbridge/amd/cs5536/smbus_initram.o \ $(obj)/arch/x86/geodelx/geodelx.o STAGE2_MAINBOARD_OBJ = Modified: LinuxBIOSv3/mainboard/pcengines/alix1c/dts =================================================================== --- LinuxBIOSv3/mainboard/pcengines/alix1c/dts 2007-11-27 14:44:54 UTC (rev 524) +++ LinuxBIOSv3/mainboard/pcengines/alix1c/dts 2007-11-27 16:19:34 UTC (rev 525) @@ -37,5 +37,9 @@ pcipath = "0xf,1"; enabled; }; + superio { + /config/("superio/winbond/w83627hf"); + com1enable = "1"; + }; }; }; Modified: LinuxBIOSv3/mainboard/pcengines/alix1c/initram.c =================================================================== --- LinuxBIOSv3/mainboard/pcengines/alix1c/initram.c 2007-11-27 14:44:54 UTC (rev 524) +++ LinuxBIOSv3/mainboard/pcengines/alix1c/initram.c 2007-11-27 16:19:34 UTC (rev 525) @@ -30,47 +30,117 @@ #include <io.h> #include <amd_geodelx.h> #include <northbridge/amd/geodelx/raminit.h> +#include <spd.h> -#define MANUALCONF 0 /* Do automatic strapped PLL config. */ - -#define PLLMSRHI 0x00001490 /* Manual settings for the PLL */ +#define MANUALCONF 0 /* Do automatic strapped PLL config */ +#define PLLMSRHI 0x00001490 /* manual settings for the PLL */ #define PLLMSRLO 0x02000030 - #define DIMM0 ((u8) 0xA0) #define DIMM1 ((u8) 0xA2) +/* The part is a Hynix hy5du121622ctp-d43. + * + * HY 5D U 12 16 2 2 C <blank> T <blank> P D43 + * Hynix + * DDR SDRAM (5D) + * VDD 2.5 VDDQ 2.5 (U) + * 512M 8K REFRESH (12) + * x16 (16) + * 4banks (2) + * SSTL_2 (2) + * 4th GEN die (C) + * Normal Power Consumption (<blank> ) + * TSOP (T) + * Single Die (<blank>) + * Lead Free (P) + * DDR400 3-3-3 (D43) + */ +/* SPD array */ +static const u8 spdbytes[] = { + [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10, + [SPD_BANK_DENSITY] = 0x40, + [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff, + [SPD_MEMORY_TYPE] = 7, + [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */ + [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */ + [SPD_NUM_BANKS_PER_SDRAM] = 4, + [SPD_PRIMARY_SDRAM_WIDTH] = 8, + [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */ + [SPD_NUM_COLUMNS] = 0xa, + [SPD_NUM_ROWS] = 3, + [SPD_REFRESH] = 0x3a, + [SPD_SDRAM_CYCLE_TIME_2ND] = 60, + [SPD_SDRAM_CYCLE_TIME_3RD] = 75, + [SPD_tRAS] = 40, + [SPD_tRCD] = 15, + [SPD_tRFC] = 70, + [SPD_tRP] = 15, + [SPD_tRRD] = 10, +}; + +u8 spd_read_byte(u16 device, u8 address) +{ + printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); + + if (device != (0x50 << 1)) { + printk(BIOS_DEBUG, " returns 0xff\n"); + return 0xff; + } + + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbytes[address]); + + return spdbytes[address]; +} + /** - * Placeholder in case we ever need it. Since this file is a template for - * other boards, we want this here and we want the call in the right place. - */ + * Place holder in case we ever need it. Since this file is a + * template for other motherboards, we want this here and we want the + * call in the right place. + */ + static void mb_gpio_init(void) { /* Early mainboard specific GPIO setup */ } -/** - * Main for initram for the PC Engines ALIX1.C. It might seem that you could - * somehow do these functions in, e.g., the CPU code, but the order of - * operations and what those operations are is VERY strongly mainboard - * dependent. It's best to leave it in the mainboard code. - */ +/** + * main for initram for the PC Engines Alix 1C. It might seem that you + * could somehow do these functions in, e.g., the cpu code, but the + * order of operations and what those operations are is VERY strongly + * mainboard dependent. It's best to leave it in the mainboard code. + */ int main(void) { - u8 smb_devices[] = { DIMM0, DIMM1 }; - + u8 smb_devices[] = { + DIMM0, DIMM1 + }; + printk(BIOS_DEBUG, "Hi there from stage1\n"); post_code(POST_START_OF_MAIN); system_preinit(); + printk(BIOS_DEBUG, "done preinit\n"); + mb_gpio_init(); + printk(BIOS_DEBUG, "done gpio init\n"); + pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO); + printk(BIOS_DEBUG, "done pll reset\n"); + cpu_reg_init(0, DIMM0, DIMM1); + printk(BIOS_DEBUG, "done cpu reg init\n"); sdram_set_registers(); + printk(BIOS_DEBUG, "done sdram set registers\n"); + sdram_set_spd_registers(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram set spd registers\n"); + sdram_enable(DIMM0, DIMM1); + printk(BIOS_DEBUG, "done sdram enable\n"); - /* Check memory. */ - /* ram_check(0, 640 * 1024); */ + /* Check low memory */ + /*ram_check(0x00000000, 640*1024); */ + printk(BIOS_DEBUG, "stage1 returns\n"); return 0; } Modified: LinuxBIOSv3/mainboard/pcengines/alix1c/stage1.c =================================================================== --- LinuxBIOSv3/mainboard/pcengines/alix1c/stage1.c 2007-11-27 14:44:54 UTC (rev 524) +++ LinuxBIOSv3/mainboard/pcengines/alix1c/stage1.c 2007-11-27 16:19:34 UTC (rev 525) @@ -28,20 +28,24 @@ #include <io.h> #include <amd_geodelx.h> #include <southbridge/amd/cs5536/cs5536.h> +#include <superio/winbond/w83627hf/w83627hf.h> +#define SERIAL_DEV W83627HF_SP1 +#define SERIAL_IOBASE 0x3f8 + void hardware_stage1(void) { + void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase); post_code(POST_START_OF_MAIN); - geodelx_msr_init(); cs5536_stage1(); - /* NOTE: Must do this AFTER the early_setup! It is counting on some - * early MSR setup for the CS5536. We do this early for debug. - * Real setup should be done in chipset init via Config.lb. - * - * TODO: Drop Config.lb reference, update comment. + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536. */ - cs5536_setup_onchipuart(); + cs5536_disable_internal_uart(); + w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); + }

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Re: [LinuxBIOS] r523 - in LinuxBIOSv3: arch/x86 lib mainboard/adl/msm800sev mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/emulation/qemu-x86 mainboard/pcengines/alix1c
by Peter Stuge 27 Nov '07

27 Nov '07

On Tue, Nov 27, 2007 at 03:38:43PM +0100, svn(a)openbios.org wrote: > As added benefit, we obsolete a lot of code without introducing > new code. This is sweet. It would be great to get rid of that obsolete code sooner rather than later now that it isn't needed anymore, when it's fresh in memory. //Peter

1 0

[LinuxBIOS] r524 - LinuxBIOSv3/arch/x86
by svn＠openbios.org 27 Nov '07

27 Nov '07

Author: hailfinger Date: 2007-11-27 15:44:54 +0100 (Tue, 27 Nov 2007) New Revision: 524 Modified: LinuxBIOSv3/arch/x86/Makefile LinuxBIOSv3/arch/x86/stage1.c Log: Convert stage2 handling from binary blob to multi-segment LAR which is created by parsing the ELF file linuxbios.stage2.o. That way, we avoid manual specification of the entry point for stage2 code. A few LAR functions are now unused and can be removed in a following cleanup session. Another suggested cleanup would be factoring out a load_all_segments function, resulting in less code duplication. Ron says: > This is great. We killed the blob. In the movie, it was impossible. > FYI, the new approach works on real hardware, I am getting nice printk > messages from stage1! Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: LinuxBIOSv3/arch/x86/Makefile =================================================================== --- LinuxBIOSv3/arch/x86/Makefile 2007-11-27 14:38:43 UTC (rev 523) +++ LinuxBIOSv3/arch/x86/Makefile 2007-11-27 14:44:54 UTC (rev 524) @@ -36,7 +36,7 @@ ROM_SIZE := $(shell expr $(CONFIG_LINUXBIOS_ROMSIZE_KB) \* 1024) -LARFILES := nocompress:normal/initram.o normal/stage2 nocompress:normal/option_table +LARFILES := nocompress:normal/initram.o normal/stage2.o nocompress:normal/option_table ifneq ($(CONFIG_PAYLOAD_NONE),y) LARFILES += normal/payload endif @@ -57,12 +57,12 @@ COMPRESSFLAG := -C nrv2b endif -$(obj)/linuxbios.rom $(obj)/linuxbios.map: $(obj)/linuxbios.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/linuxbios.initram.o $(obj)/linuxbios.stage2 $(obj)/option_table +$(obj)/linuxbios.rom $(obj)/linuxbios.map: $(obj)/linuxbios.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/linuxbios.initram.o $(obj)/linuxbios.stage2.o $(obj)/option_table $(Q)rm -rf $(obj)/lar.tmp $(Q)mkdir $(obj)/lar.tmp $(Q)mkdir $(obj)/lar.tmp/normal $(Q)cp $(obj)/linuxbios.initram.o $(obj)/lar.tmp/normal/initram.o - $(Q)cp $(obj)/linuxbios.stage2 $(obj)/lar.tmp/normal/stage2 + $(Q)cp $(obj)/linuxbios.stage2.o $(obj)/lar.tmp/normal/stage2.o $(Q)cp $(obj)/option_table $(obj)/lar.tmp/normal/option_table ifeq ($(CONFIG_PAYLOAD_NONE),y) $(Q)printf " PAYLOAD none (as specified by user)\n" @@ -198,13 +198,11 @@ STAGE2_OBJ += $(obj)/util/x86emu/libx86emu.a $(LIBGCC_FILE_NAME) endif -$(obj)/linuxbios.stage2 $(obj)/linuxbios.stage2.map: $(obj)/stage0.init $(STAGE2_OBJ) +$(obj)/linuxbios.stage2.o $(obj)/linuxbios.stage2.map: $(obj)/stage0.init $(STAGE2_OBJ) $(Q)# leave a .o with full symbols in it for debugging. $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x1000 --entry=stage2 \ -o $(obj)/linuxbios.stage2.o $(STAGE2_OBJ) - $(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.stage2.o $(obj)/linuxbios.stage2 $(Q)$(NM) $(obj)/linuxbios.stage2.o | sort -u > $(obj)/linuxbios.stage2.map # Modified: LinuxBIOSv3/arch/x86/stage1.c =================================================================== --- LinuxBIOSv3/arch/x86/stage1.c 2007-11-27 14:38:43 UTC (rev 523) +++ LinuxBIOSv3/arch/x86/stage1.c 2007-11-27 14:44:54 UTC (rev 524) @@ -161,7 +161,12 @@ /* Turn off Cache-As-Ram */ disable_car(); - ret = run_file(&archive, "normal/stage2", (void *)0x1000); + entry = load_file(&archive, "normal/stage2.o/segment0"); + if (entry == (void *)-1) + die("FATAL: Failed loading stage2 segment0."); + if (load_file(&archive, "normal/stage2.o/segment1") == (void *)-1) + die("FATAL: Failed loading stage2 segment1."); + ret = run_address(entry); if (ret) die("FATAL: Failed in stage2 code.");

1 0

[LinuxBIOS] patch: prepare v3 tree for new way of doing initram
by ron minnich 27 Nov '07

27 Nov '07

This is a set of proposed changes for doing initram which are backward-compatible (and tested) on qemu. The change is to exploit the elf-parsing abilities of lar to better set up the initram files in LAR, and get away from worrying about potential gld bugs, now and in the future. The change is to use the elf-parsing capabilities of LAR to parse the initram.o file, and create a valid LAR header with an entry value. This will fix the problems I am having on the ALIX 1C and probably allow it to boot. It also sets the text base of the .o to 0, instead of whatever wacky value gld is choosing, so all platforms will have the same value. I would appreciate comments on this, and I wonder if we shouldn't just drop the "binary blob" initram immediately. I don't see a need for it at this point. That said, this is backwards-compatible for now. Note that we can next apply this to stage 2, and completely remove the dreaded "binary blobs" from the LAR, and also remove our use of objcopy for this use. ron thanks ron

3 4

[LinuxBIOS] r523 - in LinuxBIOSv3: arch/x86 lib mainboard/adl/msm800sev mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/emulation/qemu-x86 mainboard/pcengines/alix1c
by svn＠openbios.org 27 Nov '07

27 Nov '07

Author: hailfinger Date: 2007-11-27 15:38:43 +0100 (Tue, 27 Nov 2007) New Revision: 523 Modified: LinuxBIOSv3/arch/x86/Makefile LinuxBIOSv3/arch/x86/stage1.c LinuxBIOSv3/lib/lar.c LinuxBIOSv3/mainboard/adl/msm800sev/Makefile LinuxBIOSv3/mainboard/amd/norwich/Makefile LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile LinuxBIOSv3/mainboard/emulation/qemu-x86/initram.c LinuxBIOSv3/mainboard/pcengines/alix1c/Makefile Log: Use the elf-parsing capabilities of LAR to parse the initram.o file, and create a valid LAR header with an entry value. This will fix the problems Ron is having on the ALIX 1C and probably allow it to boot. It also sets the text base of the .o to 0, instead of whatever wacky value gld is choosing, so all platforms will have the same value. Get away from worrying about potential gld bugs, now and in the future. As added benefit, we obsolete a lot of code without introducing new code. Qemu target entry point debugging has been added to be able to spot problems with entry points in the future. This patch is a joint work of Ron and Carl-Daniel. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: LinuxBIOSv3/arch/x86/Makefile =================================================================== --- LinuxBIOSv3/arch/x86/Makefile 2007-11-27 01:12:48 UTC (rev 522) +++ LinuxBIOSv3/arch/x86/Makefile 2007-11-27 14:38:43 UTC (rev 523) @@ -36,7 +36,7 @@ ROM_SIZE := $(shell expr $(CONFIG_LINUXBIOS_ROMSIZE_KB) \* 1024) -LARFILES := nocompress:normal/initram normal/stage2 nocompress:normal/option_table +LARFILES := nocompress:normal/initram.o normal/stage2 nocompress:normal/option_table ifneq ($(CONFIG_PAYLOAD_NONE),y) LARFILES += normal/payload endif @@ -57,11 +57,11 @@ COMPRESSFLAG := -C nrv2b endif -$(obj)/linuxbios.rom $(obj)/linuxbios.map: $(obj)/linuxbios.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/linuxbios.initram $(obj)/linuxbios.stage2 $(obj)/option_table +$(obj)/linuxbios.rom $(obj)/linuxbios.map: $(obj)/linuxbios.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/linuxbios.initram.o $(obj)/linuxbios.stage2 $(obj)/option_table $(Q)rm -rf $(obj)/lar.tmp $(Q)mkdir $(obj)/lar.tmp $(Q)mkdir $(obj)/lar.tmp/normal - $(Q)cp $(obj)/linuxbios.initram $(obj)/lar.tmp/normal/initram + $(Q)cp $(obj)/linuxbios.initram.o $(obj)/lar.tmp/normal/initram.o $(Q)cp $(obj)/linuxbios.stage2 $(obj)/lar.tmp/normal/stage2 $(Q)cp $(obj)/option_table $(obj)/lar.tmp/normal/option_table ifeq ($(CONFIG_PAYLOAD_NONE),y) @@ -122,10 +122,12 @@ endif endif + +# We now parse initram as ELF, so we need PARSEELF enabled unconditionally. ifeq ($(CONFIG_PAYLOAD_PREPARSE_ELF), y) PARSEELF = -e else - PARSEELF = + PARSEELF = -e endif STAGE0_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE0_LIB_OBJ)) \ Modified: LinuxBIOSv3/arch/x86/stage1.c =================================================================== --- LinuxBIOSv3/arch/x86/stage1.c 2007-11-27 01:12:48 UTC (rev 522) +++ LinuxBIOSv3/arch/x86/stage1.c 2007-11-27 14:38:43 UTC (rev 523) @@ -138,17 +138,17 @@ // find first initram if (check_normal_boot_flag()) { printk(BIOS_DEBUG, "Choosing normal boot.\n"); - ret = execute_in_place(&archive, "normal/initram"); + ret = execute_in_place(&archive, "normal/initram.o/segment0"); } else { printk(BIOS_DEBUG, "Choosing fallback boot.\n"); - ret = execute_in_place(&archive, "fallback/initram"); + ret = execute_in_place(&archive, "fallback/initram.o/segment0"); /* Try a normal boot if fallback doesn't exist in the lar. * TODO: There are other ways to do this. * It could be ifdef or the boot flag could be forced. */ if (ret) { printk(BIOS_DEBUG, "Fallback failed. Try normal boot\n"); - ret = execute_in_place(&archive, "normal/initram"); + ret = execute_in_place(&archive, "normal/initram.o/segment0"); } } Modified: LinuxBIOSv3/lib/lar.c =================================================================== --- LinuxBIOSv3/lib/lar.c 2007-11-27 01:12:48 UTC (rev 522) +++ LinuxBIOSv3/lib/lar.c 2007-11-27 14:38:43 UTC (rev 523) @@ -263,9 +263,9 @@ filename); return 1; } - where = result.start; + where = result.start + (u32)result.entry; } - printk(BIOS_SPEW, "where is %p\n", where); + printk(BIOS_SPEW, "Entry point is %p\n", where); ret = run_address(where); printk(BIOS_SPEW, "run_file returns with %d\n", ret); return ret; Modified: LinuxBIOSv3/mainboard/adl/msm800sev/Makefile =================================================================== --- LinuxBIOSv3/mainboard/adl/msm800sev/Makefile 2007-11-27 01:12:48 UTC (rev 522) +++ LinuxBIOSv3/mainboard/adl/msm800sev/Makefile 2007-11-27 14:38:43 UTC (rev 523) @@ -32,14 +32,11 @@ $(obj)/southbridge/amd/cs5536/smbus_initram.o \ $(obj)/arch/x86/geodelx/geodelx.o -$(obj)/linuxbios.initram $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) +$(obj)/linuxbios.initram.o $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) $(Q)# initram links against stage0 $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(LD) --entry main -N -R $(obj)/stage0-prefixed.o \ + $(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \ $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) -o $(obj)/linuxbios.initram.o - $(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \ - $(obj)/linuxbios.initram $(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n" $(Q)$(NM) $(obj)/linuxbios.initram.o | sort -u > $(obj)/linuxbios.initram.map Modified: LinuxBIOSv3/mainboard/amd/norwich/Makefile =================================================================== --- LinuxBIOSv3/mainboard/amd/norwich/Makefile 2007-11-27 01:12:48 UTC (rev 522) +++ LinuxBIOSv3/mainboard/amd/norwich/Makefile 2007-11-27 14:38:43 UTC (rev 523) @@ -32,14 +32,11 @@ $(Q)printf " BUILD DUMMY VPD\n" $(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT) -$(obj)/linuxbios.initram $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) +$(obj)/linuxbios.initram.o $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) $(Q)# initram links against stage0 $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(LD) --entry main -N -R $(obj)/stage0-prefixed.o \ + $(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \ $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) -o $(obj)/linuxbios.initram.o - $(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \ - $(obj)/linuxbios.initram $(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n" $(Q)$(NM) $(obj)/linuxbios.initram.o | sort -u > $(obj)/linuxbios.initram.map Modified: LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile =================================================================== --- LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile 2007-11-27 01:12:48 UTC (rev 522) +++ LinuxBIOSv3/mainboard/artecgroup/dbe61/Makefile 2007-11-27 14:38:43 UTC (rev 523) @@ -30,14 +30,11 @@ INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ $(obj)/arch/x86/geodelx/geodelx.o -$(obj)/linuxbios.initram $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) +$(obj)/linuxbios.initram.o $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) $(Q)# initram links against stage0 $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(LD) --entry main -N -R $(obj)/stage0-prefixed.o \ + $(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \ $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) -o $(obj)/linuxbios.initram.o - $(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \ - $(obj)/linuxbios.initram $(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n" $(Q)$(NM) $(obj)/linuxbios.initram.o | sort -u > $(obj)/linuxbios.initram.map Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile =================================================================== --- LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile 2007-11-27 01:12:48 UTC (rev 522) +++ LinuxBIOSv3/mainboard/emulation/qemu-x86/Makefile 2007-11-27 14:38:43 UTC (rev 523) @@ -42,14 +42,11 @@ INITRAM_OBJ = $(obj)/mainboard/$(MAINBOARDDIR)/initram.o -$(obj)/linuxbios.initram $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) +$(obj)/linuxbios.initram.o $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) $(Q)# initram links against stage0 $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(LD) --entry main -N -R $(obj)/stage0-prefixed.o \ + $(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \ $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) -o $(obj)/linuxbios.initram.o - $(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \ - $(obj)/linuxbios.initram $(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n" $(Q)$(NM) $(obj)/linuxbios.initram.o | sort -u > $(obj)/linuxbios.initram.map Modified: LinuxBIOSv3/mainboard/emulation/qemu-x86/initram.c =================================================================== --- LinuxBIOSv3/mainboard/emulation/qemu-x86/initram.c 2007-11-27 01:12:48 UTC (rev 522) +++ LinuxBIOSv3/mainboard/emulation/qemu-x86/initram.c 2007-11-27 14:38:43 UTC (rev 523) @@ -21,10 +21,24 @@ #include <console.h> +/* printktest1() is here to increase the likelihood of main() not ending up at + * the beginning of the file, so we can check whether the entry point at main() + * was honored. + */ +int printktest1(void) +{ + printk(BIOS_INFO, "printktest1: If the immediately preceding line does" + " not say \"Nothing to do.\", then execution did not start at" + " main()\n"); + + return 0; +} + int main(void) { printk(BIOS_INFO, "RAM init code started.\n"); printk(BIOS_INFO, "Nothing to do.\n"); + printktest1(); return 0; } Modified: LinuxBIOSv3/mainboard/pcengines/alix1c/Makefile =================================================================== --- LinuxBIOSv3/mainboard/pcengines/alix1c/Makefile 2007-11-27 01:12:48 UTC (rev 522) +++ LinuxBIOSv3/mainboard/pcengines/alix1c/Makefile 2007-11-27 14:38:43 UTC (rev 523) @@ -32,14 +32,11 @@ $(Q)printf " BUILD DUMMY VPD\n" $(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT) -$(obj)/linuxbios.initram $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) +$(obj)/linuxbios.initram.o $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) $(Q)# initram links against stage0 $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(LD) --entry main -N -R $(obj)/stage0-prefixed.o \ + $(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \ $(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) -o $(obj)/linuxbios.initram.o - $(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \ - $(obj)/linuxbios.initram $(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n" $(Q)$(NM) $(obj)/linuxbios.initram.o | sort -u > $(obj)/linuxbios.initram.map

1 0

Re: [LinuxBIOS] flashrom support for AMD CS5536
by Alan Alexander 27 Nov '07

27 Nov '07

I really should do more reading before bothering you guys. It would seem that the answer to my questions is CMOS non-volatile RAM, accessed via IO ports. How very odd. Thanks again, Alan Alexander mailto:alan@icerasemi.com Software Toolchain Engineering Icera Inc, 2520 The Quadrant, Aztec west, Bristol BS32 4AQ, UK Tel. +44 (0)1454 284805 -----Original Message----- From: linuxbios-bounces(a)linuxbios.org [mailto:linuxbios-bounces@linuxbios.org] On Behalf Of Alan Alexander Sent: 27 November 2007 11:09 To: bari Cc: linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] flashrom support for AMD CS5536 Many thanks to all of the help regarding flashing of the Pm49fl004 device through the AMD CS5536 chipset on my IEI Nano LX board. I am now able to erase and write the entire 512KByte region as desired. Unfortunately, it would appear that I have overlooked something in my quest for an automatic way to modify the legacy bios settings in our embedded Linux devices. Although I can now alter the BIOS at my hearts content, it seems that the actual BIOS settings themselves are stored elsewhere. For example: 0) BIOS settings are set to configuration 'a' 1) I make a change to the Legacy BIOS settings (using the BIOS boot menu) - configuration now 'b' (not equal to 'a') 2) I save the BIOS image (with configuration 'b') from the Pm49fl004 device via flashrom -r. 3) I revert the BIOS settings back to configuration 'a' using the BIOS boot menu. 4) I re-apply the saved image ('b') using flashrom -w and verify it with flashrom -v 5) On reboot the settings change applied in configuration 'b' are missing. So, my conclusion is that the actual BIOS settings must be stored elsewhere. I suspect that this is probably obvious to you guys. Could someone please tell me if this is the usual setup (i.e. BIOS flash + some other storage device for settings). If so, could someone also point me at a likely interface/device/address range for this 'other' storage device. Is it likely to be a SPI flash or something? Any help greatly appreciated. Best regards, Alan Alexander mailto:alan@icerasemi.com Software Toolchain Engineering Icera Inc, 2520 The Quadrant, Aztec west, Bristol BS32 4AQ, UK Tel. +44 (0)1454 284805 -----Original Message----- From: bari [mailto:bari@onelabs.com] Sent: 23 November 2007 18:35 To: Alan Alexander Cc: linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] flashrom support for AMD CS5536 Alan Alexander wrote: > Many thanks for the information. Unfortunately I don't have access to > the board schematics and getting technical support from the board > supplier is proving rather difficult. > > I have confirmed via an oscilloscope that both the WP# and TBL# pins are > permanently pulled high - indicating that no hardware write protection > is enabled (so it looks like I may have side stepped the GPIO locking > issue). The pins WP# and TBL# are active low and would be tied high even in the case of having write protection. Have you seen the WP# or TBL# go low on the scope during any of your write attempts? I have also observed activity on the LFRAME#/FWH4 pin when > flashrom is attempting to write to the flash. Since I don't have access > to X-ray equipment I think my best shot is to take a look at waveforms > produced during a byte program cycle. I just need to get hold of that > Logic Analyzer....... > That will tell you how much you have working during an attempt at a byte program cycle. Are you able now to write to the memory area below the top-boot-block of the Flash? If so, all you have left to do is find out how they control the TBL#. -Bari -- ************************************************************************ ****************** This e-mail (including any attachments) is intended only for the recipient(s) named above. It may contain confidential or privileged information and should not be read, copied or otherwise used by any other person. If you are not a named recipient, please contact the sender by telephone (+44-1454-284800) and destroy the original message. Any statement and/or opinion not related to this company's business and expressed in this message is that of the author and does not necessarily reflect those of Icera. This company does not take any responsibility for the views of the author in any matter not related to the company's objective. ************************************************************************ ****************** -- linuxbios mailing list linuxbios(a)linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios -- ****************************************************************************************** This e-mail (including any attachments) is intended only for the recipient(s) named above. It may contain confidential or privileged information and should not be read, copied or otherwise used by any other person. If you are not a named recipient, please contact the sender by telephone (+44-1454-284800) and destroy the original message. Any statement and/or opinion not related to this company's business and expressed in this message is that of the author and does not necessarily reflect those of Icera. This company does not take any responsibility for the views of the author in any matter not related to the company's objective. ******************************************************************************************

1 0

Re: [LinuxBIOS] flashrom support for AMD CS5536
by Alan Alexander 27 Nov '07

27 Nov '07

Many thanks to all of the help regarding flashing of the Pm49fl004 device through the AMD CS5536 chipset on my IEI Nano LX board. I am now able to erase and write the entire 512KByte region as desired. Unfortunately, it would appear that I have overlooked something in my quest for an automatic way to modify the legacy bios settings in our embedded Linux devices. Although I can now alter the BIOS at my hearts content, it seems that the actual BIOS settings themselves are stored elsewhere. For example: 0) BIOS settings are set to configuration 'a' 1) I make a change to the Legacy BIOS settings (using the BIOS boot menu) - configuration now 'b' (not equal to 'a') 2) I save the BIOS image (with configuration 'b') from the Pm49fl004 device via flashrom -r. 3) I revert the BIOS settings back to configuration 'a' using the BIOS boot menu. 4) I re-apply the saved image ('b') using flashrom -w and verify it with flashrom -v 5) On reboot the settings change applied in configuration 'b' are missing. So, my conclusion is that the actual BIOS settings must be stored elsewhere. I suspect that this is probably obvious to you guys. Could someone please tell me if this is the usual setup (i.e. BIOS flash + some other storage device for settings). If so, could someone also point me at a likely interface/device/address range for this 'other' storage device. Is it likely to be a SPI flash or something? Any help greatly appreciated. Best regards, Alan Alexander mailto:alan@icerasemi.com Software Toolchain Engineering Icera Inc, 2520 The Quadrant, Aztec west, Bristol BS32 4AQ, UK Tel. +44 (0)1454 284805 -----Original Message----- From: bari [mailto:bari@onelabs.com] Sent: 23 November 2007 18:35 To: Alan Alexander Cc: linuxbios(a)linuxbios.org Subject: Re: [LinuxBIOS] flashrom support for AMD CS5536 Alan Alexander wrote: > Many thanks for the information. Unfortunately I don't have access to > the board schematics and getting technical support from the board > supplier is proving rather difficult. > > I have confirmed via an oscilloscope that both the WP# and TBL# pins are > permanently pulled high - indicating that no hardware write protection > is enabled (so it looks like I may have side stepped the GPIO locking > issue). The pins WP# and TBL# are active low and would be tied high even in the case of having write protection. Have you seen the WP# or TBL# go low on the scope during any of your write attempts? I have also observed activity on the LFRAME#/FWH4 pin when > flashrom is attempting to write to the flash. Since I don't have access > to X-ray equipment I think my best shot is to take a look at waveforms > produced during a byte program cycle. I just need to get hold of that > Logic Analyzer....... > That will tell you how much you have working during an attempt at a byte program cycle. Are you able now to write to the memory area below the top-boot-block of the Flash? If so, all you have left to do is find out how they control the TBL#. -Bari -- ****************************************************************************************** This e-mail (including any attachments) is intended only for the recipient(s) named above. It may contain confidential or privileged information and should not be read, copied or otherwise used by any other person. If you are not a named recipient, please contact the sender by telephone (+44-1454-284800) and destroy the original message. Any statement and/or opinion not related to this company's business and expressed in this message is that of the author and does not necessarily reflect those of Icera. This company does not take any responsibility for the views of the author in any matter not related to the company's objective. ******************************************************************************************

1 0

Re: [LinuxBIOS] GIGABYTE GA-2761GXDK
by 蔡明耀 (my_tsai) 27 Nov '07

27 Nov '07

----- Original Message ----- From: "Uwe Hermann" <uwe(a)hermann-uwe.de> To: "Morgan Tsai /SiS" <my_tsai(a)sis.com> Cc: <linuxbios(a)linuxbios.org>; "Ray Wang /SiS" <ray_wang(a)sis.com>; "Jordan Crouse" <jordan.crouse(a)amd.com>; "Eric Lin /SiS" <ericlin(a)sis.com> Sent: Tuesday, November 20, 2007 11:52 PM Subject: Re: [LinuxBIOS] GIGABYTE GA-2761GXDK > On Tue, Nov 20, 2007 at 06:53:59PM +0800, Morgan Tsai /SiS wrote: >> Change Log: >> >> 1. Fix pirq routing table setting for GA-2761GXDK. >> 2. Southbridge PCIe slots are working correctly now. >> 3. Disable keyboard & mouse ports for GA-2761GXDK. >> >> >> Signed-off-by: Morgan Tsai <my_tsai(a)sis.com> > > Looks good, but why disable PS/2 keyboard and mouse? Aren't these > connectors available at all on the board or should the keyboard/mouse > init be done by the southbridge (there is some code in *_lpc.c)? There is no connector and pin available on board. So it didn't need any resource. Attachment is the board's picture. > > Also, can you please fill the status table in the wiki about which > hardware on the board works fine and which is work in progress? > > Please see > http://linuxbios.org/GIGABYTE_GA-2761GXDK_Build_Tutorial > where I have created an empty table. Do you have a wiki account > already to change the page? You can contact Stefan Reinauer > <stepan(a)coresystems.de> for an account. > > Alternatively, you can also post the status via email, I can fix up the > wiki then. Please use "OK" for fully working parts, "N/A" for hardware > which is not available on the board, "WIP" for parts which you are still > working on. > > I'm currently writing a page to explain how to test all the hardware, > but it's not finished yet: http://linuxbios.org/Board_Testing_HOWTO > Now I fill the current status I am certain. There is a identical board I have deliverd for Ron Minnich. We can check it with him. > Here's the whole status table for the board: > > |CPU_status = OK > |CPU_L1_status = OK > |CPU_L2_status = OK > |CPU_L3_status = N/A > |CPU_multiple_status = WIP > |CPU_multicore_status = WIP > |CPU_virt_status = ?? > > |RAM_EDO_status = N/A > |RAM_SDRAM_status = N/A > |RAM_SODIMM_status = N/A > |RAM_DDR_status = N/A > |RAM_DDR2_status = OK > |RAM_DDR3_status = N/A > |RAM_dualchannel_status = N/A > |RAM_ecc_status = WIP > > |IDE_status = N/A > |IDE_CF_status = N/A > |IDE_25_status = N/A > |CDROM_DVD_status = WIP > |SATA_status = WIP > |USB_status = WIP > |Onboard_VGA_status = OK > |Onboard_ethernet_status = WIP > |Onboard_audio_status = WIP > |Onboard_modem_status = N/A > |Onboard_firewire_status = N/A > |Smartcard_status = N/A > |Onboard_CF_status = N/A > |Onboard_PCMCIA_status = N/A > > |ISA_cards_status = N/A > |AMR_cards_status = N/A > |AGP_cards_status = N/A > |PCI_cards_status = OK > |PCIE_x1_status = OK > |PCIE_x2_status = N/A > |PCIE_x4_status = N/A > |PCIE_x8_status = N/A > |PCIE_x16_status = N/A > |PCIE_x32_status = N/A > |HTX_status = N/A > > |Floppy_status = N/A > |COM1_status = OK > |COM2_status = N/A > |PP_status = N/A > |PS2_keyboard_status = N/A > |PS2_mouse_status = N/A > |Game_port_status = N/A > |IR_status = N/A > |Speaker_status = N/A > |DiskOnChip_status = N/A > > |Sensors_status = > |Watchdog_status = > |CAN_bus_status = N/A > |CPUfreq_status = > |Powersave_status = > |ACPI_status = > |Reboot_status = > |Poweroff_status = > |LEDs_status = > |HPET_status = > |RNG_status = > |WakeOnModem_status = > |WakeOnLAN_status = > |WakeOnKeyboard_status = > |WakeOnMouse_status = > |Flashrom_status = > > > Thanks, Uwe. > -- > http://www.hermann-uwe.de | http://www.holsham-traders.de > http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

4 4

[LinuxBIOS] USB 2.0 Controller without debug port
by Wander Winkelhorst 27 Nov '07

27 Nov '07

Hello, I was just reading the LinuxBIOS pages and saw that you wanted reports on debug port capability of USB 2.0 controllers. I have a VIA SP13000 motherboard that wasn't listed and doesn't have the debug port capability: lspci -v: 0000:00:10.4 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 86) (prog-if 20 [EHCI]) Subsystem: VIA Technologies, Inc. USB 2.0 Flags: bus master, medium devsel, latency 176, IRQ 11 Memory at ec000000 (32-bit, non-prefetchable) [size=256] Capabilities: [80] Power Management version 2 lspci -n: 0000:00:10.4 0c03: 1106:3104 (rev 86) I hope this helps! Regards, Wander Winkelhorst

2 1

[LinuxBIOS] Board support
by Klaus Stammermann 27 Nov '07

27 Nov '07

Hi The bios of my MINI-ITX board from VIA is booting too slow. So I am looking for an alternative bios and found this project. But my board is not listed at supported motherboard list. I am using an VIA EPIA ME6000G (NB CLE266, SB VT8235). Is it possible to run linuxBIOS on this board? If it doesn't is it planed to support this board (is anyone working at it)? Or is it better to change board? Greetings from Germany Klaus Stammermann

4 3

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coreboot November 2007