coreboot May 2005

coreboot@coreboot.org

36 participants
85 discussions

[LinuxBIOS] Adding Support for ATA Freeze Command.
by Ralph Corderoy 23 May '05

23 May '05

Hi, Are people generally aware of the ATA security commands? They allow a password to be set on a hard drive. It's the hard drive that's doing the password storing, not the motherboard, so the drive's still locked if it's moved to another machine. On boot-up the BIOS recognises the drive's locked and prompts the user for the password. It's also the normal UI for setting it in the first place. Anyway, my point is passwords are typically not set. This means something malicous can set it and the next time the machine boots the user's locked out of his own drive. The c't magazine had an article on it recently. http://www.heise.de/ct/english/05/08/172/ Once a drive's locked with an unknown user password then it's a dead drive unless the manufacturer can be persuade to give you the higher level password that allows a security format of the device to be done. This normally requires a paper-chase to prove you're the rightful owner. Options are for users to set the password on their drives so it can't be set malicously to something unknown to them but that's a pain because it needs supplying on boot-up. Or, for the ATA Freeze command to be used soon after boot-up. This puts the drive in a state where it won't accept any password setting until after the next boot. (The ATA-3 spec. is http://www.t13.org/project/d2008r7b-ATA-3.pdf -- see pages 33 and 75 by the number written on the page.) Ideally, the Freeze needs to be done as soon as possible in the BIOS -> bootloader -> OS chain to make it harder to set the password before the freeze is done. That's why I'm here. :-) It LinuxBIOS were to add support for Freeze drives it would be another advantage over other BIOSes. Am I right in thinking that LinuxBIOS itself knows nothing about ATA and that's left to FILO? Is that the only payload that deals with ATA? (I'm also going to lobby the Grub people for those of us that don't have BIOS support for ATA Freeze.) Cheers, Ralph.

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[LinuxBIOS] http://wiki.linuxbios.org/ not found.
by Ken Fuchs 21 May '05

21 May '05

When I try to access http://wiki.linuxbios.org/ I get wiki.linuxbios.org is not found. http://www.linuxbios.org/ works fine. It would be nice if any access within the linuxbios.org domain responds with something more useful than <host>.linuxbios.org is not found. Sincerely, Ken Fuchs <kfuchs(a)winternet.com>

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[LinuxBIOS] I"ve updated the dns for www.linuxbios.org
by Ronald G. Minnich 21 May '05

21 May '05

let's see if it works in 24 hours. ron

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[LinuxBIOS] Bug in pnp_set_drq()?
by Steven J. Magnani 20 May '05

20 May '05

I ran across the following code in src/devices/pnp_device.c: void pnp_set_drq(device_t dev, unsigned drq, unsigned index) { /* Index == 0x74 */ pnp_write_config(dev, index, drq & 0xff); } static void pnp_set_resource(device_t dev, struct resource *resource) { ... /* Now store the resource */ if (resource->flags & IORESOURCE_IO) { pnp_set_iobase(dev, resource->index, resource->base); } else if (resource->flags & IORESOURCE_DRQ) { pnp_set_drq(dev, resource->index, resource->base); } ... } The declaration of pnp_set_drq() looks backwards to me. Shouldn't it be void pnp_set_drq(device_t dev, unsigned index, unsigned drq) to match the way it's being called? Steve Magnani Digital Design Corporation www.digidescorp.com

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Re: Fwd: [LinuxBIOS] still no luck on smartcore-p5
by Kjell Svensson 20 May '05

20 May '05

Hi again, I just tried the romimage - It didn't work! Well, the LinuxBIOS booted and everything looked OK up until the same point as I have seen before from my builds; elfboot is started, but the payload seems completely dead... :-( Since I saw the payload in the romimage was etherboot, I also hooked up the ethernet and started sniffing it with ethereal, but no packets were ever sent on the ethernet. I have also checked that nothing comes out on the VGA console. My conclusion is that the Etherboot payload either never is reached, or crashes at an early stage. Well, I guess this anyway gives me lots of hints by ruling out all the doubts I had about my config and build process; now I guess there must be something different between our Smartcore-P5 based hardwares... Could I please ask you to check what cardtype/revision you're using? My HW config looks as follows: DigitalLogic MSM-P5SEN, V3.9, Rev A. It's also marked 03.04 which I guess is the manufacturing date(?) This card has a SmartCore-P5 module clocked at 166MHz. There is only one Revision label on this module, but it has no revision mark on it... The MSM-P5SEN variant comes without VGA cirquitry, but I have also tried LinuxBIOS on the VGA-equipped variant we have around here with the same result. The onboard Flash is a Winbond 29C020CP (i.e 256kB), but LinuxBIOS boots equally well also from 128kB and 512kB flashes I've tried in the socket. The card has one SDRAM slot, which we have equipped with a 128MB large module. Looking for simple answers; could you possibly be using a different size (larger) RAM, and could the elfboot for this platform have some code fragments not checking the detected RAM size so that it relocates the payload out inito the void? -- Cheers. /Kjell Quoting Kjell Svensson <lists(a)endian.se>: > > > > Begin forwarded message: > > > From: "Ronald G. Minnich" <rminnich(a)lanl.gov> > > Date: 19 maj 2005 16:45:16 MET > > To: Kjell Svensson <lists(a)endian.se> > > Subject: Re: [LinuxBIOS] still no luck on smartcore-p5 > > > > > > > > no guarantees, but this might be it. > > > > it's a 512KB image. What size rom do you have? > > > > ron

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[LinuxBIOS] RE: Intel 82801 southbridge NMI configuration
by Steven J. Magnani 20 May '05

20 May '05

A correction to the corrected code, for the record...the outb() parameters were reversed... #include <arch/io.h> static void lpc_init(struct device *dev) { ... /* Set up NMI on errors */ byte = inb(0x61); byte &= ~(1 << 3); /* IOCHK# NMI Enable */ byte &= ~(1 << 2); /* PCI SERR# Enable */ outb(byte, 0x61); byte = inb(0x70); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ outb(byte, 0x70); } ... } --Steve

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[LinuxBIOS] Intel 82801 southbridge NMI configuration
by Steven J. Magnani 20 May '05

20 May '05

It's me again. Further down in the 82801{er | dbm} LPC initialization code, there is a block that configures NMI handling: static void lpc_init(struct device *dev) { ... /* Set up NMI on errors */ byte = pci_read_config8(dev, 0x61); byte |= (1 << 3); /* IOCHK# NMI Enable */ byte |= (1 << 6); /* PCI SERR# Enable */ pci_write_config8(dev, 0x61, byte); byte = pci_read_config8(dev, 0x70); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { byte |= (1 << 7); /* set NMI */ pci_write_config8(dev, 0x70, byte); } ... } >From the ICH-5 ('ER) documentation, it looks to me like this is meant to be accessing NMI_SC and NMI_EN, the NMI Status and Control and NMI Enable registers, which are at 0x61 and 0x70 in processor I/O space, not PCI configuration space. So inb()/outb() should be used instead of pci_read_config8()/pci_write_config8(). If these are the correct registers, SERR# enable is controlled by bit 2, not bit 6. Also it looks like the code does the opposite of what was intended, enabling NMIs when it should be disabling them, and vice versa. This is because Intel defines the NMI bits used above with reverse polarity...set to 1 to DISable, 0 to ENable. So the code should read instead as: #include <arch/io.h> static void lpc_init(struct device *dev) { ... /* Set up NMI on errors */ byte = inb(0x61); byte &= ~(1 << 3); /* IOCHK# NMI Enable */ byte &= ~(1 << 2); /* PCI SERR# Enable */ outb(0x61, byte); byte = inb(0x70); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ outb(0x70, byte); } ... } It this looks right, I'm willing to attempt folding this change into the source (never used arch before...), but I have no way to test that it does anything other than compile. Regards, Steve Magnani Digital Design Corporation www.digidescorp.com

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Re: Fwd: [LinuxBIOS] still no luck on smartcore-p5
by Ronald G. Minnich 20 May '05

20 May '05

On Fri, 20 May 2005, Stefan Reinauer wrote: > * Ronald G. Minnich <rminnich(a)lanl.gov> [050520 17:32]: > > Also, the memory that has worked well for us is Apacer. What I have on my > > SC520 is the Apacer 128MB UBN PC133 CL3 memory. ^^^^^ Smartcore P5. typo! ron

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[LinuxBIOS] Posted memory write enable...incorrect?
by Steven J. Magnani 20 May '05

20 May '05

Hi, In looking over the Intel 82801ER (ICH-5) southbridge code, I noticed some statements that modify LPC PCI config register 0x46 to enable PCI posted memory writes (src/southbridge/intel/i82801er/i82801er_lpc.c): static void lpc_init(struct device *dev) { ... /* posted memory write enable */ byte = pci_read_config8(dev, 0x46); pci_write_config8(dev, 0x46, byte | (1<<0)); ... } The ICH-5 datasheet does not mention such a configuration register. Neither do the datasheets for the ICH-4 (82801DBM) or the AMD 8111, which have similar code. Is it possible that these were inherited (incorrectly) from code for the AMD 766 southbridge? That *does* support this functionality. Steve Magnani Digital Design Corporation www.digidescorp.com

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Re: [LinuxBIOS] still no luck on smartcore-p5
by Kjell Svensson 19 May '05

19 May '05

Hmm, interesting image you sent!... I was curious about the image, so I had a look at it in my hex editor back home while waiting to get back into work tomorrow to actually test it. I was surprised to find the image to be repeating after 256kB, i.e comparing the first 256k with the second 256k showed they were identical! Is this what a LinuxBIOS romimage is supposed to be? If so, the images my builds have generated are certainly bogus, because I never got that. If not, could you have made an error when copying the image, so that your cluster nodes actually use this image in 256kB flashes? Except for this, I couldn't see anything unusual. Cheers, /Kjell On 19 maj 2005, at 16:45, Ronald G. Minnich wrote: > > > no guarantees, but this might be it. > > it's a 512KB image. What size rom do you have? > > ron<smartcore.rom>

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coreboot May 2005