coreboot April 2005

coreboot@coreboot.org

23 participants
41 discussions

[LinuxBIOS] a great quote
by Ronald G. Minnich 12 Apr '05

12 Apr '05

"You'd need to know the confidential information about the chips to write" a free BIOS, Insyde Software's Joseph said. Right now, "that info is only available on old hardware that nobody really cares about anymore." http://news.com.com/Battle+brews+over+unlocking+PC+secrets/2100-1016_3-5654… garsh, didn't know that opterons are so obsolete. It's amazing how much lack-of-clue there is out there masquerading as knowledge. ron

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[LinuxBIOS] Re: post code "fe" means what ?
by Stefan Reinauer 12 Apr '05

12 Apr '05

* Huang-Jen Wang <huangjen.wang(a)gmail.com> [050412 10:46]: > Hi Stefan, > The message as follow: > setup_timers: CPU 2005 MHz > pci_init: Scanning PCI: found 4 devices > malloc_diag: alloc: 184 bytes (4 blocks), free: 16192 bytes (1 blocks) > pci_init: 00:18.0 1022:1100 0600 00 > pci_init: 00:18.1 1022:1101 0600 00 > pci_init: 00:18.2 1022:1102 0600 00 > pci_init: 00:18.3 1022:1103 0600 00 > Press <Enter> for default boot, or <Esc> for boot prompt... timed out > boot: hda2:/boot/vmlinuz root=/dev/hda2 console=tty0 console=ttyS0,115200 > malloc_diag: alloc: 264 bytes (5 blocks), free: 16112 bytes (1 blocks) > malloc_diag: alloc: 280 bytes (6 blocks), free: 16096 bytes (1 blocks) > file_open: dev=hda2, path=/boot/vmlinuz > find_ide_controller: PCI IDE #0 not found > IDE channel 0 not found > devopen: failed to open ide The IDE controller is not detected. Did you set PCI_BRUTE_SCAN = 1 in the filo config file? Stefan

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[LinuxBIOS] Questions about romcc
by Hamish Guthrie 11 Apr '05

11 Apr '05

I am busy doing a port of the Geode code to V2, and am running into difficulty with the RAM sizing. The issue is not the RAM sizing itself, but the behaviour of romcc. I have not looked into romcc in any depth at all, but am guessing that my problem results either from the declaration of too many variables or nesting function calls too deeply. Are there any guidelines as to variable usage and function call nesting, and will romcc give any warning messages when all the registers are used up? TIA, Hamish -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.308 / Virus Database: 266.9.5 - Release Date: 07.04.2005

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[LinuxBIOS] Mainboard Question
by Thomas Spear 08 Apr '05

08 Apr '05

I'm considering a mainboard that has a via C3 cpu and uses a chipset comprised of a via CLE266 and a via VT8235; it uses ddr266 and has integrated via 2 channel audio, 10/100 lan and UniChrome vga (64M shared mamory). I'm hoping that since this is almost identical to an epia-m board, the epia linux bios should work "as is". Is that correct? If I got a working image from someone, would the odds be good that it would work on this board?

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Re: [LinuxBIOS] Geode in Linuxbios v2
by ramesh bios 07 Apr '05

07 Apr '05

> Ramesh, I saw in one of your posts that you had > mentioned willingness to > start working on this - if you have started, maybe > we could work together on > this? > Definitely, I'd be happy to work with you on the V2 conversion. I haven't done anything on V2 yet. Maybe I'll go do a V2 build sometime this weekend and get a feel for how things are laid out there. Ramesh __________________________________ Yahoo! Messenger Show us what our next emoticon should look like. Join the fun. http://www.advision.webevents.yahoo.com/emoticontest

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[LinuxBIOS] irq_tables.c
by Peter.VanEchaute＠bench.com 07 Apr '05

07 Apr '05

Hello, I am trying to understand the "linka, linkb, linkc, linkd" part of this table. I understand the rest of the table, just not those pieces. Can someone give me a brief explanation? Thank you for your time. Cheers, Peter Van Echaute Email: Peter.VanEchaute(a)bench.com <mailto:Peter.VanEchaute@bench.com>

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RE: [LinuxBIOS] readl and read32
by YhLu 06 Apr '05

06 Apr '05

arch/ppc/lib/pci_ppc_conf1_ops.c: .read32 = ppc_conf1_read_config32, arch/i386/lib/pci_ops_conf1.c: .read32 = pci_conf1_read_config32, arch/i386/lib/pci_ops_conf2.c: .read32 = pci_conf2_read_config32, arch/i386/include/arch/romcc_io.h:static inline uint32_t read32(unsigned long addr) devices/pci_ops.c: return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary, dev->path.u.pci.devfn, where); include/device/pci.h: uint32_t (*read32) (struct bus *pbus, unsigned char bus, int devfn, int where); read32 in pci should be changed to pci_read32.... > -----Original Message----- > From: YhLu > Sent: Wednesday, April 06, 2005 12:42 PM > To: ebiederman(a)lnxi.com > Cc: linuxbios(a)openbios.org > Subject: [LinuxBIOS] readl and read32 > > Do you think > read32 arch/i386/include/arch/romcc_io.h and readl in > arch/i386/include/arch/io.h should be removed one? > > YH > > _______________________________________________ > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios >

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[LinuxBIOS] Re: RTC and linuxbios checksum versus pc checksum
by Peter Karlsson 01 Apr '05

01 Apr '05

On Thu, 31 Mar 2005, ramesh bios wrote: > Well, I got things to work in the end by copying the > standard bios's CR bit settings for the W83977AF. > Regretably though, I have gained no understanding of > why or how it's working. Amazingly, the standard bios > sets CR30 on the W83977AF, ie: the RTC enable/disable > bit to disabled. So the RTC appears to increment > properly when that bit is disabled (which makes no > sense to me at all, ie: disable the RTC and it ticks > properly?). When that bit is enabled, and no other > changes, the RTC has weird incrementation behavior. > Almost seemed like random bits in mm:ss were changing. > Also, I never understood why bytes in 0E-7F, the user > ram changes during normal ticking of the clock. Oh > well, it's working now so I guess I'll just push this > mystery to the back of my mind. If anyone happens to > understand this stuff, I'll sleep better once I've > understood this. > > Thanks. > > --- ramesh bios <ramesh_bios(a)yahoo.com> wrote: >> I was looking through linuxbios' freebios (v1) code >> and see the following: >> >> rtc_checksum_valid(PC_CKS_RANGE_START, >> >> PC_CKS_RANGE_END,PC_CKS_LOC); >> then >> rtc_checksum_valid(LB_CKS_RANGE_START, >> >> LB_CKS_RANGE_END,LB_CKS_LOC); >> then finally >> rtc_set_checksum(PC_CKS_RANGE_START, >> >> PC_CKS_RANGE_END,PC_CKS_LOC); >> >> I looked in 2.6.11's mc146818 code and I don't see >> it >> writing a checksum so I'm not certain it's valid to >> check for a checksum on boot since stuff like >> hwclock >> may/would have written to the cmos during normal >> operation. Out of curiosity, how come there is a LB >> checksum and then a PC checksum and then we write a >> PC >> checksum at the end. Is it for legacy compatibility, >> I >> didn't find any mention of it in the mailing list >> and >> google. >> >> Thanks. The @clustermatic.org mail address is not to be used anymore. If anyone knows anything about the above question please put this in the wiki-faq... Best regards Peter K

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[LinuxBIOS] Glossary update...
by Peter Karlsson 01 Apr '05

01 Apr '05

Here's another update of the glossary of acronyms I've found on this list (and other's). Unfortunately it is quite hard (sometimes impossible) to dig up information about the acronym/definition on the internet (I'm planning to buy that book that someone recommended on this list) so some info is marked with '???'. If anyone wants to update that feel free to do so, it is much appreciated. I've attached a tar-ball containing the original glossary, a diff, and the updated glossary to hopefully make it easier (?) to update the wiki. Some info may or may not be relevant (I'm on ivtv, v4l, mesa, xorg, gentoo-users, linux-from-scratch, unichrome, opengfx amongst other mail-lists so I pick up a few things)... Best regards Peter K

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RE: [LinuxBIOS] [PATCH 2/2] amd8111_nic: Set MAC address in linux bios
by YhLu 01 Apr '05

01 Apr '05

Should be in BIOS.because different MB use different MAC assigned in Factory. But in MB design, it should use another SEEPROM to store that. So the BIOS or NIC get it. YH > -----Original Message----- > From: Li-Ta Lo [mailto:ollie@lanl.gov] > Sent: Thursday, March 31, 2005 11:11 AM > To: Tao Liu > Cc: LinuxBIOS > Subject: Re: [LinuxBIOS] [PATCH 2/2] amd8111_nic: Set MAC > address in linuxbios > > On Thu, 2005-03-31 at 15:29 +0800, Tao Liu wrote: > > Hello, > > > > this patch sets 8111NIC's mac. The 48-bit mac address is > saved in OEM > > ROM, in nic_init() the driver gets the mac address through register > > oem_mac_offset, and copy it to 8111NIC's PADR register. > > > > > > Is it store is it own serial EEPROM or in the same ROM as > BIOS? If it is stored in it won EEPROM, this code sould be > in the kernel driver than BIOS. > > Ollie > > > > diff -Nur > > > freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd8111_nic.c > > freebios2-20050305-0000/src/southbridge/amd/amd8111/amd8111_nic.c > > --- > freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/amd81 > 11_nic.c 2004-10-21 > > 18:44:04.000000000 +0800 > > +++ > freebios2-20050305-0000/src/southbridge/amd/amd8111/amd811 > 1_nic.c 2005-03-31 > > 12:50:56.000000000 +0800 > > @@ -6,20 +6,99 @@ > > #include <device/pci.h> > > #include <device/pci_ids.h> > > #include <device/pci_ops.h> > > +#include <delay.h> > > #include "amd8111.h" > > > > +#undef writel > > +#undef writeb > > +#define writel(val,addr) (*(volatile uint32_t *)(addr) = (val)) > > +#define writeb(val,addr) (*(volatile uint8_t *)(addr) = (val)) > > > > +#define CMD3 0x54 > > +#define PADR 0x160 > > + > > +typedef enum { > > + VAL3 = (1 << 31), /* VAL bit for byte 3 */ > > + VAL2 = (1 << 23), /* VAL bit for byte 2 */ > > + VAL1 = (1 << 15), /* VAL bit for byte 1 */ > > + VAL0 = (1 << 7), /* VAL bit for byte 0 */ > > +}VAL_BITS; > > + > > +typedef enum { > > + /* VAL3 */ > > + ASF_INIT_DONE_ALIAS = (1 << 29), > > + /* VAL2 */ > > + JUMBO = (1 << 21), > > + VSIZE = (1 << 20), > > + VLONLY = (1 << 19), > > + VL_TAG_DEL = (1 << 18), > > + /* VAL1 */ > > + EN_PMGR = (1 << 14), > > + INTLEVEL = (1 << 13), > > + FORCE_FULL_DUPLEX = (1 << 12), > > + FORCE_LINK_STATUS = (1 << 11), > > + APEP = (1 << 10), > > + MPPLBA = (1 << 9), > > + /* VAL0 */ > > + RESET_PHY_PULSE = (1 << 2), > > + RESET_PHY = (1 << 1), > > + PHY_RST_POL = (1 << 0), > > +}CMD3_BITS; > > + > > +static void nic_init(struct device *dev) { > > + struct southbridge_amd_amd8111_config *conf; > > + struct resource *resource; > > + void *mmio; > > + unsigned char *oem_mac_addr; > > + int i; > > + > > + conf = dev->chip_info; > > + resource = find_resource(dev, PCI_BASE_ADDRESS_0); > > + mmio = (void *)(unsigned long)resource->base; > > + > > + /* Hard Reset PHY */ > > + printk_debug("Reseting PHY... "); > > + if (conf->phy_lowreset) { > > + writel(VAL0 | PHY_RST_POL | RESET_PHY , mmio + CMD3); > > + } else { > > + writel(VAL0 | RESET_PHY, mmio + CMD3); > > + } > > + mdelay(15); > > + writel(RESET_PHY, mmio + CMD3); > > + printk_debug("Done\n"); > > + > > + /* Set MAC address */ > > + printk_debug("Mac Addr "); > > + oem_mac_addr = (unsigned char *)(ROM_OEM_START + > conf->oem_mac_offset); > > + for (i = 0; i < 6; i++) { > > + printk_debug("%02X%c", oem_mac_addr[i], i == 5 > ? '\n' : ':'); > > + writeb(oem_mac_addr[i], mmio + PADR + i); > > + } > > +} > > + > > +static void lpci_set_subsystem(device_t dev, unsigned vendor, > > +unsigned device) { > > + pci_write_config32(dev, 0xc8, > > + ((device & 0xffff) << 16) | (vendor & 0xffff)); } > > + > > +static struct pci_operations lops_pci = { > > + .set_subsystem = lpci_set_subsystem, }; > > + > > static struct device_operations nic_ops = { > > .read_resources = pci_dev_read_resources, > > .set_resources = pci_dev_set_resources, > > .enable_resources = pci_dev_enable_resources, > > - .enable = amd8111_enable, > > - .init = 0, > > + .init = nic_init, > > .scan_bus = 0, > > + .enable = amd8111_enable, > > + .ops_pci = &lops_pci, > > }; > > > > static struct pci_driver nic_driver __pci_driver = { > > .ops = &nic_ops, > > .vendor = PCI_VENDOR_ID_AMD, > > - .device = 0x7462, > > + .device = PCI_DEVICE_ID_AMD_8111_NIC, > > }; > > diff -Nur > > freebios2-20050305-0000-orig/src/southbridge/amd/amd8111/chip.h > > freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h > > --- > freebios2-20050305-0000-orig/src/southbridge/amd/amd8111 > /chip.h 2004-10-21 > > 18:44:04.000000000 +0800 > > +++ > freebios2-20050305-0000/src/southbridge/amd/amd8111/chip.h > 2005-03-31 > > 12:49:32.000000000 +0800 > > @@ -5,6 +5,8 @@ > > { > > unsigned int ide0_enable : 1; > > unsigned int ide1_enable : 1; > > + unsigned int phy_lowreset : 1; > > + unsigned long oem_mac_offset; > > }; > > > > struct chip_operations; > > > > > -- > Li-Ta Lo <ollie(a)lanl.gov> > Los Alamos National Lab > > > _______________________________________________ > LinuxBIOS mailing list > LinuxBIOS(a)openbios.org > http://www.openbios.org/mailman/listinfo/linuxbios >

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coreboot April 2005