coreboot June 2004

coreboot@coreboot.org

43 participants
102 discussions

Re: testbios info?
by Li-Ta Lo 02 Jun '04

02 Jun '04

On Wed, 2004-06-02 at 06:40, Jay Miller wrote: > Can someone post a quick rundown on testbios? > > I know that you get the vgabios from the card, and run that through > testbios. But how do you get linuxbios to use the results? > Currently it is only used as a userspace program to init VGA cards after Linux is booted. After getting more test case and feedback, I will try to merge it in to LinuxBIOS. The emulator will be one of the init/configure method of the generic VGA device driver. Ollie > I'm missing something. > > Thanks, > > Jay Miller > Actuality Systems, Inc. > jmiller(a)acutality-systems.com > > > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

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Re: testbios info?
by Richard Smith 02 Jun '04

02 Jun '04

Jay Miller wrote: > Can someone post a quick rundown on testbios? > > I know that you get the vgabios from the card, and run that through > testbios. But how do you get linuxbios to use the results? > > I'm missing something. Not really. Right now thats it. Testbios is the testbed for getting the emulation layer working good enough to include into linuxBIOS. I beleive that ollie is working on mergeing in testbios into the v2 core now that it supports int10 replacemnet.

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Hibernation?
by lbios_kk＠redfenix.com 02 Jun '04

02 Jun '04

I'm sure if someone has thought of doing this before, but I haven't found mention of it anywhere. Has any work been done toward the goal of "Hibernation"? I'm writing of the type that would use a separate partition equal to ram + swap space to store the current memory state. If no one has done any work to this effect, how difficult would it be? I may be willing to help the effort. I've never programmed for a BIOS, but I've done mmap() stuff before. --Kevin

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答复: Large mmio resources and 4G+ of RAM...
by YhLu 02 Jun '04

02 Jun '04

Then in LinuxBIOS We can access the memory in 64 bit mode directly. And maybe do the memory check and test. Memory problem is a big problem in system integration. Some time 8 ways system, every cpu has 4 dimm, total memay will be 4G*4*8=128G. Regards YH -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2004年6月1日 10:41 收件人: YhLu 抄送: Stefan Reinauer; LinuxBIOS 主题: Re: Large mmio resources and 4G+ of RAM... YhLu <YhLu(a)tyan.com> writes: > Eric, > > There is something called Memory lifting or memory remapping for Opteron. > For example if 2G for one Opteron and two ways system. > > Then the CPU 0 will use [0,2G), and CPU 1 will use [4G, 6G). > > If the RAM for CPU is above 4G, then We must lost 1/2G for MMIO range, the > reason is Opteron only has two reg for RAM LOW and HIGH limit. And there is > no other regs to record the memory hole. But it seems Intel CPU has more > regs to remember the memory hole. Memory lifting is nice. And in certain specific instances it is useful. On the Opteron it is possible to move either Memory controllers, or DIMMS. At 4G per memory controller it does not work to move memory controllers, at paired singled sided 2G DIMMS you can't move DIMMS. So the other solution is to move the large MMIO resources. Moving the MMIO resources has the advantage that A) It is simple. B) It works in all circumstances (baring issues with bridges) C) Is needed if you have many large MMIO regions. D) It works on all CPUs. E) A 32bit kernel could support it with highmem type tricks... So I think I would rather pursue moving the large MMIO resources first. The limited utility of memory lifting doesn't inspire me to worry about it. Although the few circumstances the Opteron memory lifting applies to may be the only cases people really care about loosing that much memory. Eric

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Large mmio resources and 4G+ of RAM...
by ebiederman＠lnxi.com 02 Jun '04

02 Jun '04

For the longest time I have been fighting what to do with machines that have 4GB or more of memory and large memory mapped I/O resources. As the conflict in memory space can cause a loss of 1/2GB of memory. Which does not tend to be good for performance. Looking the large memory mapped I/O resources all have 64bit BARs. So I am just going to modify the LinuxBIOS resource allocator to put 64bit BARs on x86-64 boxes at least above the top of memory. There are a couple of short term hacks that I can do with relocating memory but on the Opteron the more memory I add the more problems I run into. And moving BARS above 4G looks like the right term fix. Any objections? Eric

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testbios info?
by Jay Miller 02 Jun '04

02 Jun '04

Can someone post a quick rundown on testbios? I know that you get the vgabios from the card, and run that through testbios. But how do you get linuxbios to use the results? I'm missing something. Thanks, Jay Miller Actuality Systems, Inc. jmiller(a)acutality-systems.com

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答复: USB Boot
by YhLu 01 Jun '04

01 Jun '04

OHCI usb boot ok now. But it is some slow, only 173KB/S, Full speed should be 12Mbps/8 = 1500KB/s Regards YH Mounted fat Image checksum: 000047da Loading Linux version 2.6.5 (root@tst288xsuse9) #11 SMP Mon May 10 14:58:17 PDT 2004... segment 1 addr:0x00010000 file:0x0000543c mem:0x0001a764 phdr:0xefe86654 loading... clearing... ok segment 2 addr:0x00091000 file:0x00000000 mem:0x00000070 phdr:0xefe86674 loading... clearing... ok segment 3 addr:0x00100000 file:0x001f5a40 mem:0x00700000 phdr:0xefe86694 loading... clearing... ok segment 4 addr:0x00800000 file:0x005c418e mem:0x005c418e phdr:0xefe866b4 loading... clearing... ok Loaded 8122378 bytes in 46722ms (173KB/s -----邮件原件----- 发件人: YhLu 发送时间: 2004年6月1日 17:53 收件人: Steven James 抄送: ron minnich; Jay Miller; ebiederman(a)lnxi.com; LinuxBIOS 主题: USB Boot Some good news. In OHCI, bulk transfer works well. Status: it can read sector 0 and sector 68, after that it will reboot the system. Regards YH _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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USB Boot
by YhLu 01 Jun '04

01 Jun '04

Some good news. In OHCI, bulk transfer works well. Status: it can read sector 0 and sector 68, after that it will reboot the system. Regards YH

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MSI 694t pro supported?
by Ben Johnson 01 Jun '04

01 Jun '04

Hi everybody, I perused through the documentation, but as I am really no specialist, I couldn't tell if Linuxbios would work with my motherboard, nor the way to put the whole thing up and running in the eventuality it would -is there any step-by-step howto for dummies like I ? The reason I ask is because the 694t's (aka 6309 v.5) bios is buggy as hell, and the kind folks at MSI do not offer support anymore. Hope not to be too much a burden on the list, my apologies if I am. Thank you for your attention, here's the output of lspci -vv: 0000:00:00.0 Host bridge: VIA Technologies, Inc. VT82C693A/694x [Apollo PRO133x] (rev c4) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR+ Latency: 8 Region 0: Memory at e0000000 (32-bit, prefetchable) Capabilities: [a0] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:01.0 PCI bridge: VIA Technologies, Inc. VT82C598/694x [Apollo MVP3/Pro133x AGP] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 Memory behind bridge: dde00000-dfefffff Prefetchable memory behind bridge: cdc00000-ddcfffff BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.0 ISA bridge: VIA Technologies, Inc. VT82C686 [Apollo Super South] (rev 40) Subsystem: VIA Technologies, Inc. VT82C686/A PCI to ISA Bridge Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Region 4: I/O ports at ff00 [size=16] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 1a) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. (Wrong ID) USB Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64, Cache Line Size: 0x08 (32 bytes) Interrupt: pin D routed to IRQ 10 Region 4: I/O ports at dc00 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:07.4 Bridge: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] (rev 40) Subsystem: VIA Technologies, Inc. VT82C686 [Apollo Super ACPI] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [68] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:0f.0 Ethernet controller: Macronix, Inc. [MXIC] MX987x5 (rev 25) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR+ FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (2000ns min, 14000ns max), Cache Line Size: 0x08 (32 bytes) Interrupt: pin A routed to IRQ 5 Region 0: I/O ports at d800 [size=dff80000] Region 1: Memory at dfffff00 (32-bit, non-prefetchable) [size=256] Expansion ROM at 00040000 [disabled] Capabilities: [44] Power Management version 1 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:10.0 Network controller: PLX Technology, Inc.: Unknown device 1151 (rev 01) Subsystem: PLX Technology, Inc.: Unknown device 1151 Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 3 Region 0: Memory at dffffe80 (32-bit, non-prefetchable) Region 1: I/O ports at d400 [size=128] Region 2: I/O ports at d000 [size=8] 0000:00:11.0 Multimedia audio controller: C-Media Electronics Inc CM8738 (rev 10) Subsystem: Hercules: Unknown device a650 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (500ns min, 6000ns max) Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at cc00 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:01:00.0 VGA compatible controller: nVidia Corporation NV11 [GeForce2 MX/MX 400] (rev a1) (prog-if 00 [VGA]) Subsystem: Asustek Computer, Inc.: Unknown device 4055 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (1250ns min, 250ns max) Interrupt: pin A routed to IRQ 11 Region 0: Memory at de000000 (32-bit, non-prefetchable) [size=dfef0000] Region 1: Memory at d0000000 (32-bit, prefetchable) [size=128M] Expansion ROM at 00010000 [disabled] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [44] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA- ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> Cheers! __________________________________ Do you Yahoo!? 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Re: Large mmio resources and 4G+ of RAM...
by YhLu 01 Jun '04

01 Jun '04

Eric, There is something called Memory lifting or memory remapping for Opteron. For example if 2G for one Opteron and two ways system. Then the CPU 0 will use [0,2G), and CPU 1 will use [4G, 6G). If the RAM for CPU is above 4G, then We must lost 1/2G for MMIO range, the reason is Opteron only has two reg for RAM LOW and HIGH limit. And there is no other regs to record the memory hole. But it seems Intel CPU has more regs to remember the memory hole. Regards YH

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coreboot June 2004