April 2004 - coreboot - mail.coreboot.org

答复: 答复: Flash_rom [PMX:#]
by YhLu April 12, 2004

April 12, 2004

Actually, the last 4k is erased to 0xff. But the last 4k can not be read. Only get 0x00 back. YH -----邮件原件----- 发件人: Hendricks David W. [mailto:dwh@lanl.gov] 发送时间: 2004年4月9日 15:43 收件人: YhLu 抄送: 'Li-Ta Lo'; 'ron minnich'; 'linuxbios(a)clustermatic.org' 主题: Re: ´ð¸´: Flash_rom [PMX:#] It looks like this error is not consistent. You can run flash_rom multiple times and it will eventually flash successfully using kernel 2.6.5 (Use the -v flag). Weird... On Fri, 9 Apr 2004, YhLu wrote: > Ollie, > > The problem happens in all above 4G RAM installed and in 2.6.5. > > Regards > > YH > > -----ÓÊ¼þÔ¼þ----- > ·¢¼þÈË: YhLu > ·¢ËÍÊ±¼ä: 2004Äê4ÔÂ9ÈÕ 13:15 > ÊÕ¼þÈË: YhLu; Li-Ta Lo > ³ËÍ: 'ron minnich'; 'linuxbios(a)clustermatic.org' > Ö÷Ìâ: ´ð¸´: Flash_rom > > Ollie, > > Only happens in s2885, it seems there is problem in AGP GART in 2.6.5, it > reserve [4G-4k,4G). ???? > > Regards > > YH. > > -----ÓÊ¼þÔ¼þ----- > ·¢¼þÈË: YhLu > ·¢ËÍÊ±¼ä: 2004Äê4ÔÂ9ÈÕ 10:58 > ÊÕ¼þÈË: Li-Ta Lo > ³ËÍ: 'ron minnich'; 'linuxbios(a)clustermatic.org' > Ö÷Ìâ: Flash_rom > > Ollie, > > I checked the flash_rom, and find that you remove the code for check if the > sector is really erased. > > Also I found the flash_rom can not work under 2.6.4.and 2.6.5 in x86_64 > mode, and it seems only last 4k can not be erased. [0x7f000, 0x7ffff]. > > Regards > > YH > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

2 1

Newbie with epia M-II
by Ignacio Verona April 12, 2004

April 12, 2004

hi! This is my first post. I'm trying to develop my own Car PC and using LinuxBios I hope to get faster boot times. I'm using a Via EPIA M-II 10000. What are the first steps I should take? The epia bios is socketed on 32-lead PLCC format. What is the biggest rom size I could get? It is possible to use DOC on this motherboard (may be, I could fit a usable linux system on... less than 64mb). I've reading the list archive but I'm still a little lost. All help will be aprecciated. Thanks!!

4 5

Flash_rom
by YhLu April 12, 2004

April 12, 2004

Ollie, I checked the flash_rom, and find that you remove the code for check if the sector is really erased. Also I found the flash_rom can not work under 2.6.4.and 2.6.5 in x86_64 mode, and it seems only last 4k can not be erased. [0x7f000, 0x7ffff]. Regards YH

2 1

Any possible updates for LinuxBIOS...
by Vic Berdin April 12, 2004

April 12, 2004

... supporting the AMD GX2 and CS5535 companion chip? just hoping, Vic --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com) Version: 6.0.656 / Virus Database: 421 - Release Date: 4/9/2004

2 1

Re: FILO 0.4 [PMX:#]
by Greg Watson April 12, 2004

April 12, 2004

Correct. I haven't included linux_load, though it would probably be easy to do. FILO simply calls elfboot to load the image from a filesystem. Merging FILO with etherboot is a fine idea, but it doesn't solve the loader problem for PPC. At this point I don't see any requirement to port etherboot to PPC, but if anyone would like to take it on then feel free. :-) I think the case for including a simple FILO-like loader in linuxbios is a strong one. Apart from instant PPC loader support and reducing the difficulty of deploying linuxbios, it's possible to make use of much of the existing linuxbios code which significantly reduces duplication and complexity in the payload. Greg On 04/04/2004, at 2:57 PM, Yinghai Lu wrote: > Eric, > > Greg just move the fs support from filo to linuxbios, and create > fs_stream. > > It still calls the elfboot to load the elfimage in HD. And it doesn't > support linux_load. > > So it is some kind of boot loader you said. > > It is really enhancement to ide_stream.c > > Regards > > YH > > -----邮件原件----- > 发件人: Eric W. Biederman [mailto:eric@lnxi.com] 代表 Eric W. Biederman > 发送时间: 2004年4月3日 20:33 > 收件人: Greg Watson > 抄送: Yinghai Lu; 'SONE Takeshi'; linuxbios(a)clustermatic.org > 主题: Re: g-e$: FILO 0.4 [PMX:#] > > Greg Watson <gwatson(a)lanl.gov> writes: > >> Yeah sorry, I kind of did that by stealth. Ron and I get lots of >> requests > from >> people wanting to use LB but who don't know how to deal with the >> payload >> issue. We decided that it would be really nice to have a simple >> bootloader > that >> understands some basic filesystems built into LB. That way people can >> get > going >> without having to deal with etherboot or FILO directly. A nice side >> effect > is >> that it simplifies the FILO code significantly - in fact the only code > that is >> really required is the filesystem support. Also, another major plus is > that the >> code supports PPC as well as x86. Up to now I've had no bootloaders > (etherboot >> or FILO) that work on PPC. > > Then we refactor and make building the bootloader part of the tree. > These things are policy engines. We need to separate mechanism and > policy. > > As far as I can tell this level of support crosses the line. > > etherboot is portable and would not be hard to get running on ppc. > > Eric >

3 4

Via Epia V8000 bios
by fedde＠fedde.net April 12, 2004

April 12, 2004

Hi all! Fist of all i would say linuxbios looks like a great project, and now it can maby help me. I got a Via EPia V8000 @ 800mhz (http://www.viavpsd.com/product/epia_v_spec.jsp?motherboardId=141) that is strugeling abit. It appears the onboard 1.06 bios has problems with with wireless network cards that is made of atheros due the irq sharing on the pci slot that it's sharing with the usb that is not needed. The board is booting from a CF disk on the ide, so i would also like to know if it's possible to treat the ide controller as normal, so it's possible to change the CF with a hard drive later on? So, anybody wanna have a go creating bios for this board, or give me som guidelines on how to disable and creating the bios, but i got not too much experience with bios creation. Any help would be appriciated becouse i'm stuck with two of these boards that are unusable for me. Sincerly FredriK B

1 0

EPIA-M "Magic Potion"?
by John Laur April 11, 2004

April 11, 2004

Greetings, everyone. I am fairly new to LinuxBIOS, having fooled with it for only a couple of days. Needless to say, I've been learning a lot. I have had a lot of success with this great project, but recently have been meeting with some failures as well. I'm searching for the "Magic Potion" of CVS checkout date, patches, and config file that makes it work for me, even if only passably, until the v2 port can proceed and the VGA issues can be re-addressed. I am trying to use a VIA EPIA M-1000 (Ezra) board and I'm having limited success that at this point, I cannot decide are problems with my LinuxBIOS configuration/build or problems with the code I am using. I was able to successfully build and run LinuxBIOS with the serial console and using FILO or etherboot (via-rhine and ide-disk) payloads without. I am building code from a current (Mar. 25, 2004) v1 cvs checkout. 1) The machine has 512MB SDRAM, but LinuxBIOS only sets up 128MB. Is this a problem with my config file? I know that v1 has some limitations with memory on this platform. Was there a time when this worked better on epia-m? 2) I cannot for the life of me flash the BIOS under Linux. For now, I have to reboot to a DOS floppy and flash the original BIOS, then reboot again and flash the LinuxBIOS image (AWFLASH will for some reason not flash a LinuxBIOS image over a LinuxBIOS image already on the flash part) I have run 'setpci -s 0:11.0 40.b=54' as described in the docs and on the mailing list, but flash_rom still detects no flash device. 3) Despite my sincerest efforts, VGA is doing nothing. I have extracted the VGA bios from both /proc/kcore as described in the HOWTO and from a ROM image using CBROM (padded to 64k).. neither of these work. The VGA bios I'm trying is from the latest release of the BIOS from VIA. I understand that some people are having success on epia-m/vga using a checkout from last july and a patch from Dave Ashley.. I may have mistakenly believed that all that made it into CVS, but if not, what is the correct checkout date, and where can I find the patch? Thanks in advance to the list for any assistance! John Laur

6 20

EPIA-M "Magic Potion"?
by Dave Ashley April 11, 2004

April 11, 2004

I really should check this list more often. However I've been really busy... I think I gathered that the VGA isn't showing up in the lspci. I looked at the latest CVS and found my earlysetup.inc isn't getting included in the Config in src/mainboard/via/epia-m. Actually the earlysetup.inc isn't even there. Here's what I have. This can go after mainboardinit southbridge/via/vt8235/setup_misc.inc // enable VGA device movl $CONFIG_ADDR(0, 0x00, 0xe1), %eax movb $0xbd, %dl // enable vga with 8 megs PCI_WRITE_CONFIG_BYTE // The stupid firewire device (undocumented) steps on IO 0+ on reset movl $CONFIG_ADDR(0, 0x0d*8, 0x15), %eax movb $0x1c, %dl PCI_WRITE_CONFIG_BYTE Both of the above are *required*. The following is optional but works well for me. Our application has a pci card in the slot that can impose an interrupt even after a cpu reset, so this can cause a lockup. I got around this by doing a single hard pci bus reset. In order to know if I've already done the reset once, I store a flag in the CMOS memory. I think this is a good idea but my choice of where in the CMOS to store the flag is probably not kosher. // use CMOS byte 0x0e as marker so we only reboot once movb $0x0e, %al mov $0x70, %dx outb %al, %dx inc %dx inb %dx, %al cmpb $0xda, %al je 1f movl $0x100000, %ecx 0: movw $0x70,%dx mov $0x0e,%al outb %al, %dx inc %dx movb $0xda, %al outb %al, %dx inb %dx, %al cmpb $0xda, %al je 4f dec %ecx jne 0b 4: CONSOLE_INFO_TX_CHAR($'R') CONSOLE_INFO_TX_CHAR($'B') CONSOLE_INFO_TX_CHAR($'!') movl $CONFIG_ADDR(0, 0x88, 0x4f), %eax movb $0x09, %dl PCI_WRITE_CONFIG_BYTE 2: jmp 2b 1: sub %al,%al outb %al, %dx 3: Finally, I implemented the SMBUS io for being able to access the serial eeprom on the DDR module. I had it print out the contents of the serial eeprom on bootup. I had hoped Ron or Eric or cwlinux would run with this and implement the auto ddr memory config but that didn't happen. Anyway after the topmost fix the VGA will probably appear in lspci. -Dave

2 3

epia-m
by ron minnich April 11, 2004

April 11, 2004

OK, I have an 'emergency get it going' thing this week for epia-m. So anyone working with that thing please contact me and tell me how far you are with V1 and epia-m. thanks ron

1 0

VIA EPIA Build Error MAX_REBOOT_CT
by Mathieu Deschamps April 10, 2004

April 10, 2004

I'am building a new rom but now,I got stuck because of #error "MAX_REBOOT_CNT not defined" in make process of build target even though i defined this in Config.lb Here is a process trace : ####################################################################### if (cd fallback; \ make linuxbios.rom)\ then true; else exit 1; fi; make[1]: Entering directory `/home/root/projet-07042004/freebios/freebios2/build/epia/fallbac k' cp /home/root/projet/freebios/freebios2/src/arch/i386/config/crt0.base crt0.S gcc -no-gcc -x assembler-with-cpp -DASSEMBLY -E -I/home/root/projet/freebios/freebios2/src -D __ROMCC__=0 -D__ROMCC_MINOR__=38 -I/home/root/projet/freebios/freebios2/src/include -I/home/r oot/projet/freebios/freebios2/src/arch/i386/include -I/usr/lib/gcc-lib/i486-linux/egcs-2.91.6 6/include /home/root/projet/freebios/freebios2/src/mainboard/via/epia/failover.c > ./failover.E gcc: unrecognized option `-no-gcc' In file included from /home/root/projet/freebios/freebios2/src/mainboard/via/epia/failover.c: 7: /home/root/projet/freebios/freebios2/src/pc80/mc146818rtc_early.c:5: #error "MAX_REBOOT_CNT n ot defined" make[1]: *** [failover.E] Error 1 make[1]: Leaving directory `/home/root/projet-07042004/freebios/freebios2/build/epia/fallback ' make: *** [fallback-rom] Error 1 ################################################################# What is that pc80 directory in which it errors ? The parameter MAX_BOOT_CT is the counter that holds the survival of kernel messages after # boots, isn't it ? I've also joined the Config file on which i haven't made much changes except what it asked for. Please mail me a clue, just ask if you need moer info on the slab. Thanks in advance. ################################################################ # Sample config file for EPIA # This will make a target directory of ./epia # # Change for experimentation MD # loadoptions target epia uses ARCH uses CONFIG_COMPRESS uses CONFIG_IOAPIC uses CONFIG_ROM_STREAM uses CONFIG_ROM_STREAM_START uses CONFIG_UDELAY_TSC uses CPU_FIXUP uses FALLBACK_SIZE uses HAVE_FALLBACK_BOOT uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses HAVE_HARD_RESET uses i586 uses i686 uses INTEL_PPRO_MTRR uses HEAP_SIZE uses IRQ_SLOT_COUNT uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses CONFIG_SMP uses CONFIG_MAX_CPUS uses MEMORY_HOLE uses PAYLOAD_SIZE uses _RAMBASE uses _ROMBASE uses ROM_IMAGE_SIZE uses ROM_SECTION_OFFSET uses ROM_SECTION_SIZE uses ROM_SIZE uses STACK_SIZE uses USE_FALLBACK_IMAGE uses USE_OPTION_TABLE uses HAVE_OPTION_TABLE uses MAXIMUM_CONSOLE_LOGLEVEL uses DEFAULT_CONSOLE_LOGLEVEL # Sample config file for EPIA # This will make a target directory of ./epia # # Change for experimentation MD # loadoptions target epia uses ARCH uses CONFIG_COMPRESS uses CONFIG_IOAPIC uses CONFIG_ROM_STREAM uses CONFIG_ROM_STREAM_START uses CONFIG_UDELAY_TSC uses CPU_FIXUP uses FALLBACK_SIZE uses HAVE_FALLBACK_BOOT uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses HAVE_HARD_RESET uses i586 uses i686 uses INTEL_PPRO_MTRR uses HEAP_SIZE uses IRQ_SLOT_COUNT uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses CONFIG_SMP uses CONFIG_MAX_CPUS uses MEMORY_HOLE uses PAYLOAD_SIZE uses _RAMBASE uses _ROMBASE uses ROM_IMAGE_SIZE uses ROM_SECTION_OFFSET uses ROM_SECTION_SIZE uses ROM_SIZE uses STACK_SIZE uses USE_FALLBACK_IMAGE uses USE_OPTION_TABLE uses HAVE_OPTION_TABLE uses MAXIMUM_CONSOLE_LOGLEVEL uses DEFAULT_CONSOLE_LOGLEVE uses CONFIG_CONSOLE_SERIAL8250 uses MAINBOARD uses CONFIG_CHIP_CONFIGURE uses XIP_ROM_SIZE uses XIP_ROM_BASE uses LINUXBIOS_EXTRA_VERSION uses TTYS0_BAUD uses MAX_REBOOT_CNT option TTYS0_BAUD=19200 option CONFIG_CHIP_CONFIGURE=1 option MAXIMUM_CONSOLE_LOGLEVEL=7 option DEFAULT_CONSOLE_LOGLEVEL=7 option CONFIG_CONSOLE_SERIAL8250=1 option CPU_FIXUP=1 option CONFIG_UDELAY_TSC=0 option i686=1 option i586=1 option INTEL_PPRO_MTRR=1 option ROM_SIZE=256*1024 option HAVE_OPTION_TABLE=1 option CONFIG_ROM_STREAM=1 option HAVE_FALLBACK_BOOT=1 # # More Options # option MAX_REBOOT_CNT=10 ### ### Compute the location and size of where this firmware image ### (linuxBIOS plus bootloader) will live in the boot rom chip. ### option FALLBACK_SIZE=131072 ## LinuxBIOS C code runs at this location in RAM option _RAMBASE=0x00004000 # ### ### Compute the start location and size size of ### The linuxBIOS bootloader. ### # # Arima hdama romimage "normal" option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x10000 option LINUXBIOS_EXTRA_VERSION=".0Normal" mainboard via/epia # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload ../../../../../lnxieepro100.ebi end romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x10000 option LINUXBIOS_EXTRA_VERSION=".0Fallback" mainboard via/epia # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf payload ../../../../../lnxieepro100.ebi end buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

3 3