coreboot March 2004

coreboot@coreboot.org

54 participants
166 discussions

EPIA-M "Magic Potion"?
by John Laur 11 Apr '04

11 Apr '04

Greetings, everyone. I am fairly new to LinuxBIOS, having fooled with it for only a couple of days. Needless to say, I've been learning a lot. I have had a lot of success with this great project, but recently have been meeting with some failures as well. I'm searching for the "Magic Potion" of CVS checkout date, patches, and config file that makes it work for me, even if only passably, until the v2 port can proceed and the VGA issues can be re-addressed. I am trying to use a VIA EPIA M-1000 (Ezra) board and I'm having limited success that at this point, I cannot decide are problems with my LinuxBIOS configuration/build or problems with the code I am using. I was able to successfully build and run LinuxBIOS with the serial console and using FILO or etherboot (via-rhine and ide-disk) payloads without. I am building code from a current (Mar. 25, 2004) v1 cvs checkout. 1) The machine has 512MB SDRAM, but LinuxBIOS only sets up 128MB. Is this a problem with my config file? I know that v1 has some limitations with memory on this platform. Was there a time when this worked better on epia-m? 2) I cannot for the life of me flash the BIOS under Linux. For now, I have to reboot to a DOS floppy and flash the original BIOS, then reboot again and flash the LinuxBIOS image (AWFLASH will for some reason not flash a LinuxBIOS image over a LinuxBIOS image already on the flash part) I have run 'setpci -s 0:11.0 40.b=54' as described in the docs and on the mailing list, but flash_rom still detects no flash device. 3) Despite my sincerest efforts, VGA is doing nothing. I have extracted the VGA bios from both /proc/kcore as described in the HOWTO and from a ROM image using CBROM (padded to 64k).. neither of these work. The VGA bios I'm trying is from the latest release of the BIOS from VIA. I understand that some people are having success on epia-m/vga using a checkout from last july and a patch from Dave Ashley.. I may have mistakenly believed that all that made it into CVS, but if not, what is the correct checkout date, and where can I find the patch? Thanks in advance to the list for any assistance! John Laur

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EPIA-M "Magic Potion"?
by Dave Ashley 11 Apr '04

11 Apr '04

I really should check this list more often. However I've been really busy... I think I gathered that the VGA isn't showing up in the lspci. I looked at the latest CVS and found my earlysetup.inc isn't getting included in the Config in src/mainboard/via/epia-m. Actually the earlysetup.inc isn't even there. Here's what I have. This can go after mainboardinit southbridge/via/vt8235/setup_misc.inc // enable VGA device movl $CONFIG_ADDR(0, 0x00, 0xe1), %eax movb $0xbd, %dl // enable vga with 8 megs PCI_WRITE_CONFIG_BYTE // The stupid firewire device (undocumented) steps on IO 0+ on reset movl $CONFIG_ADDR(0, 0x0d*8, 0x15), %eax movb $0x1c, %dl PCI_WRITE_CONFIG_BYTE Both of the above are *required*. The following is optional but works well for me. Our application has a pci card in the slot that can impose an interrupt even after a cpu reset, so this can cause a lockup. I got around this by doing a single hard pci bus reset. In order to know if I've already done the reset once, I store a flag in the CMOS memory. I think this is a good idea but my choice of where in the CMOS to store the flag is probably not kosher. // use CMOS byte 0x0e as marker so we only reboot once movb $0x0e, %al mov $0x70, %dx outb %al, %dx inc %dx inb %dx, %al cmpb $0xda, %al je 1f movl $0x100000, %ecx 0: movw $0x70,%dx mov $0x0e,%al outb %al, %dx inc %dx movb $0xda, %al outb %al, %dx inb %dx, %al cmpb $0xda, %al je 4f dec %ecx jne 0b 4: CONSOLE_INFO_TX_CHAR($'R') CONSOLE_INFO_TX_CHAR($'B') CONSOLE_INFO_TX_CHAR($'!') movl $CONFIG_ADDR(0, 0x88, 0x4f), %eax movb $0x09, %dl PCI_WRITE_CONFIG_BYTE 2: jmp 2b 1: sub %al,%al outb %al, %dx 3: Finally, I implemented the SMBUS io for being able to access the serial eeprom on the DDR module. I had it print out the contents of the serial eeprom on bootup. I had hoped Ron or Eric or cwlinux would run with this and implement the auto ddr memory config but that didn't happen. Anyway after the topmost fix the VGA will probably appear in lspci. -Dave

2 3

FILO 0.4
by SONE Takeshi 06 Apr '04

06 Apr '04

I just released FILO 0.4. http://te.to/~ts1/filo/ It can boot distro CDs if you give a proper command line. SuSE 8.2 LiveEval CD worked without a glitch, I enjoyed the KDE desktop, OpenOffice, etc, from the CD on an EPIA booted from LinuxBIOS. Also added support for booting from BIOS flash, to boot an alternative bootloader like Etherboot. PCI support in IDE driver is also added (or recovered), but the native PCI mode is not fully tested. I tried to configure EPIA (V1) code to use native mode, and the ports read something not 0xff, but the drive doesn't respond to soft reset. I don't know the bug is in FILO, LinuxBIOS, or the hardware. I'll work on config file support next time. Version 0.4 ts1 2003-10-15 * Support for ATAPI CD-ROM. * ISO-9660 filesystem is taken from a GRUB patch by Leonid Lisovskiy <lly(a)pisem.net>. The filesystem code was originally written by Kousuke Takai <tak(a)kmc.gr.jp> for GRUB/98 project. * Support for mounting boot disk image of El Torito bootable CD-ROM. ("hdc1" means the boot disk image of the CD-ROM at hdc.) * Support for memory as device, raw device as image, and user-specifiable device offset and length. (eg. boot: mem@0xfffd0000,0x10000) * PCI support in IDE driver. Now it by default uses PCI enumeration to find the PCI IDE controller, and can use native PCI mode if the controller is configured to this mode by BIOS. To disable this, turn off SUPPORT_PCI. * Fixed Linux loader to boot RedHat 9 kernel properly. -- Takeshi

8 23

Can I execute a linuxbios image from linux?
by Svante Signell 02 Apr '04

02 Apr '04

Hello, I'm trying to upgrade the CPU on a 440BX dual board MSI-6210 from dual Celerons (Mendocino) to a single Celeron2 (Tualatin) using a socket 370 to slot 1 adapter, SLOT-T from Upgradeware. On other 440BX based motherboards, this works perfectly. Two computers I have upgraded are a QDI BrillianX 1 based box and the Compaq 5670. The lates BIOS for the 6120 does not support Coppermine or Tualatin processors. With the 6120, I get a successful boot too, but the effective speed is 7 MHz as compared to expected 1.3GHz (measured with lmbench). I have made a small kernel module testing the level 2 cache activation code, without any improvements. Also mtrr seems to be set up correctly. Now I would like to execute a full linuxbios image after boot to linux, in order to avoid the problem of re-flashing the BIOS. Is this possible? The Upgradeware support pages mentions that the IO chips have to be of correct type for a similar single CPU board, the MSI-6119 to uork with the SLOT-T adapter. What function does the IO chip have, and how can in be tested? Thanks, Svante

5 8

unreliably booting off a BCM5701.
by Stefan Reinauer 01 Apr '04

01 Apr '04

Hi, 1.1.6 seems really picky when using etherboot for network booting. The link seems very often to go up and down at will, before a real boot happens. See attached log. Any idea? Regards, Stefan ----------------------------------------------------------------------- LinuxBIOS-1.1.6.0-Fallback Mo Mär 22 17:42:39 CET 2004 starting... setting up resource map....done. ht reset - LinuxBIOS-1.1.6.0-Fallback Mo Mär 22 17:42:39 CET 2004 starting... setting up resource map....done. Initializing memory: done Clearing LinuxBIOS memory: done Testing DRAM : 00000000-00100000 DRAM fill: 00000000-00100000 00100000 DRAM filled DRAM verify: 00000000-00100000 00100000 DRAM verified Done. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. Jumping to LinuxBIOS. ROM segment 0xb7fa length 0xff3e reloc 0x00020000 CPU 1650 Mhz Etherboot 5.3.6 (GPL) http://etherboot.org Tagged ELF for [TG3][IDE] Relocating _text from: [000264e0,00058510) to [1fecdfd0,1ff00000) Boot from (N)etwork or (Q)uit? ^TProbing pci nic... [tg3-5701]Ethernet addr: 00:04:76:E0:11:99 Tigon3 [partno(3C996B-T) rev 0105 PHY(5701)] (PCI:33MHz:32-bit) Link is up at 1000 Mbps, full duplex. TX RX flow control Searching for server (DHCP)... .Link is down. Link is up at 1000 Mbps, full duplex. TX RX flow control Link is down. Link is up at 1000 Mbps, full duplex. TX RX flow control Link is down. Link is up at 1000 Mbps, full duplex. TX RX flow control .Link is down. [..] Link is up at 1000 Mbps, full duplex. TX RX flow control ..Me: 192.168.0.2, Server: 192.168.0.1 Loading 192.168.0.1:kernel.elf ...(ELF)... ........... [..] ......done Firmware type: LinuxBIOS -- Stefan Reinauer, SUSE LINUX AG Head of Architecture Development

2 6

More n00by questions...
by Vic Berdin 01 Apr '04

01 Apr '04

Hi everyone, Which kernel patch should I apply having this hardware? Processor & southbridge: AMDGX2 + CS5535 BIOS chip: SST49LF008A FWH `lspci -n`: 00:01.0 Class 0600: 100b:0028 (rev 21) 00:01.1 Class 0300: 100b:0030 00:0e.0 Class 0200: 10ec:8139 (rev 10) 00:0f.0 Class 0601: 100b:002b (rev 13) 00:0f.2 Class 0101: 100b:002d 00:0f.3 Class 0401: 100b:002e 00:0f.4 Class 0c03: 100b:002f (rev 06) 00:0f.5 Class 0c03: 100b:002f (rev 06) TIA - Vic

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product using linuxbios
by Andre Dias 31 Mar '04

31 Mar '04

We have launched a product using linuxbios here in Brasil, its a jukebox for pubs, but we use ogg vorbis and we have developed the entire system (including a hard disk distribution based in debian and one for the bios based in busybox). I have been using sis730 motherboards, but they are pretty scarce in the market right now. We use linuxbios for a faster boot, for maintenance, in case there is a HD problem, to avoid CMOS reset problems and because its cool ;) Have a look at the machine: http://www.digipop.com.br/produtos.htm (website in portuguese).

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答复: S2885 ht reset multi chain.
by YhLu 31 Mar '04

31 Mar '04

You should ask Eric, because I just wrap the code to call scan_ht_chain several times. All the info should be removed and do it dynamically, but the problem the code is in auto.c, and romcc would produce large code. Unless romcc can produce the small code, I think we can let everything to be done dynamically. YH -----邮件原件----- 发件人: Li-Ta Lo [mailto:ollie@lanl.gov] 发送时间: 2004年3月31日 14:37 收件人: YhLu 抄送: 'ron minnich'; 'linuxbios(a)clustermatic.org' 主题: Re: S2885 ht reset multi chain. On Thu, 2004-03-25 at 21:42, YhLu wrote: > Stefan, > > Please try this one. Remove the mindev in struct. And use next_unitid to > calculate the dev min and max. > > Can you try that in AMD quartet to see if ht reset works. > > You may need to add several lines in auto.c > > > static const struct ht_chain ht_c[] = { > { > .udev = PCI_DEV(0, 0x18, 0), > .upos = 0xc0, > .devreg = 0xe0, > }, > { > .udev = PCI_DEV(0, 0x19, 0), > .upos = 0xa0, > .devreg = 0xe4, > }, > }; > Why don't you use LDT[-02] instead of register address like .upos ? It is much easier to understand. Ollie

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S2885 ht reset multi chain.
by YhLu 31 Mar '04

31 Mar '04

Stefan, Please try this one. Remove the mindev in struct. And use next_unitid to calculate the dev min and max. Can you try that in AMD quartet to see if ht reset works. You may need to add several lines in auto.c static const struct ht_chain ht_c[] = { { .udev = PCI_DEV(0, 0x18, 0), .upos = 0xc0, .devreg = 0xe0, }, { .udev = PCI_DEV(0, 0x19, 0), .upos = 0xa0, .devreg = 0xe4, }, }; Change calling to ht_setup_chain to ht_setup_chains needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0])); make sure resourcemap.c like this PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04010207, PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000110, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, The result would be PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04010207, PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050117, If you enable the print_pci_devices in auto.c, you may see 0:1.0 0:2.0 0:2.1 0:2.2 0:2.3 0:2.5 0:2.6 0:5.0 0:5.1 0:6.0 0:6.1 0:18:0 0:18:1 0:18:2 0:18:3 0:19:0 0:19:1 0:19:2 0:19:3 0:1a:0 0:1a:1 0:1a:2 0:1a:3 0:1b:0 0:1b:1 0:1b:2 0:1b:3 regards YH

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trying to etherboot via linuxbios a tyan S2885 motherboard
by gnandi＠angstrom.com 31 Mar '04

31 Mar '04

Hi I am trying to boot linux using etherboot/linuxbios and get the following error (last few lines of the console dump): (see below) Any idea what could be going wrong ? The etherboot+linux image boots fine on a arima/hdama mother board. I am using one of the latest linuxbios source snapshots Regards, Gautam LinuxBIOS-1.1.62.0_Fallback Wed Mar 31 11:40:34 EST 2004 starting... setting up resource map....done. bla , bla ... Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 23:stream_init() - rom_stream: 0xfffe0000 - 0xfffeffff Found ELF candiate at offset 0 Loading Etherboot version: 5.2.4 Dropping non PT_LOAD segment New segment addr 0x20000 size 0x37058 offset 0xb0 filesize 0x68a3 (cleaned up) New segment addr 0x20000 size 0x37058 offset 0xb0 filesize 0x68a3 Loading Segment: addr: 0x000000001ffb1f38 memsz: 0x0000000000019064 filesz: 0x00 000000000068a3 Clearing Segment: addr: 0x000000001ffb87db memsz: 0x00000000000127c1 Loading Segment: addr: 0x0000000000039064 memsz: 0x000000000001dff4 filesz: 0x00 00000000000000 39:stream_skip() - overflowed source buffer ERROR: Skip of 75713 bytes skiped 38573 bytes

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coreboot March 2004