coreboot April 2003

coreboot@coreboot.org

68 participants
177 discussions

Is cmos.layout generated?
by Shubhangi Jadhav 15 Apr '03

15 Apr '03

Hi, Is the cmos.layout file a standard file or is it generated? which is the utility that generates it? Thanks, Shubhangi

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Re: Are the additional experiences or porting help for LinuxBIOS
by dkotian3＠vsnl.net 15 Apr '03

15 Apr '03

I will surely contribute from my side once I know in and out of LinuxBIOS. For now, it is for other implementors to contribute more on this. rminnich(a)lanl.gov wrote On Tue, 15 Apr 2003 dkotian3(a)vsnl.net wrote: > Or is there some kind of Porting Guide or Porting Architecture > document for LinuxBIOS not yet, but we accept contributions. ron

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Are the additional experiences or porting help for LinuxBIOS
by dkotian3＠vsnl.net 15 Apr '03

15 Apr '03

Hi, Are the additional experiences or porting help for LinuxBIOS I checked up the following location http://www.linuxbios.org/developer/portguides/index.html But could only find two over here. They are mainly for Disk-On-chip, is there something for ADLO or etherboot or some more porting issues. Or is there some kind of Porting Guide or Porting Architecture document for LinuxBIOS Please let me know. Thanks and Regards Deepak

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[commit] tiger-i7501
by steven james 15 Apr '03

15 Apr '03

Greetings, Might as well join the party. I've comitted the tiger-i7501. For anyone working on a 7501 board, Eric's made some adjustments to the raminit code, it's worth updating your tree and trying the 533MHz FSB again. G'day, sjames -- -------------------------steven james, director of research, linux labs ... ........ ..... .... 230 peachtree st nw ste 2701 the original linux labs atlanta.ga.us 30303 -since 1995 http://www.linuxlabs.com office 404.577.7747 fax 404.577.7743 -----------------------------------------------------------------------

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Releases...
by ebiederman＠lnxi.com 15 Apr '03

15 Apr '03

Over the last several months I have been pushing Ron to start making stable releases of the LinuxBIOS tree. I have contributed the code for Version numbers, and I have been stable releases for boards I support from my own tree. Watching the LinuxBIOS tree one of the things I have seen is that change happens, and it breaks old ports. And as a developer I want more change so new ports are easier to do and simpler to maintain. The path forward as I see it is to freeze the core of the tree, and to have a stable 1.0 release series. With the goal being that from release to release, we do not break any existing port in the tree. To achieve this we need to freeze the core of the tree. And put any chipset code into at least a slush so fixing one board does not break an old board. Once all of the working boards are available in the stable tree, there is not a need to avoid breaking things in the development branch. A working even if someday antiquated version will always be available just be fetching an old stable release. So that is my plan for breaking everything without breaking anything:) Eric

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newbie - soyo SYK7ADA ?
by Balint Cristian 15 Apr '03

15 Apr '03

Is there chance to work on soyo SYK7ADA ? Here is full pcilist: 00:00.0 Host bridge: Acer Laboratories Inc. [ALi] M1647 Northbridge [MAGiK 1 / MobileMAGiK 1] (rev 02) 00:01.0 PCI bridge: Acer Laboratories Inc. [ALi] PCI to AGP Controller 00:02.0 USB Controller: Acer Laboratories Inc. [ALi] USB 1.1 Controller (rev 03) 00:03.0 Multimedia audio controller: Acer Laboratories Inc. [ALi] M5451 PCI AC-Link Controller Audio Device (rev 02) 00:04.0 IDE interface: Acer Laboratories Inc. [ALi] M5229 IDE (rev c4) 00:06.0 USB Controller: Acer Laboratories Inc. [ALi] USB 1.1 Controller (rev 03) 00:07.0 ISA bridge: Acer Laboratories Inc. [ALi] M1533 PCI to ISA Bridge [Aladdin IV] 00:0b.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) 00:11.0 Bridge: Acer Laboratories Inc. [ALi] M7101 PMU 01:00.0 VGA compatible controller: NVidia / SGS Thomson (Joint Venture) Riva128 (rev 10) Maybe can i recive some hints how to test/start amd makeup an linuxbios for this MB ? Thank You, cristian -- Unable to handle kernel paging request \|/ ____ \|/ "@'/ .. \`@" /_| \__/ |_\ \__U_/ setserial(104): Oops TSTATE: 0000004411f09605 TPC: 000000000051ba00 TNPC: 000000000051ba0c Y: 0600000 g0: 7001821070016068 g1: 00000000006bf5d0 g2: 0000000000000000 g3: 00000000006b4300 g4: fffff8001398f7a0 g5: 0000000000000000 g6: fffff80010638000 g7: 0000000000000000 o0: 000008810001ccb4 o1: fffff8001398f7a0 o2: 00000000005f8af4 o3: 00000000000000f8 o4: ffffffffffffffff o5: 0000000000000000 sp: fffff8001063a601 ret_pc: 000000000044a548 l0: 0000000000000043 l1: 0000000000000039 l2: 0000000000000000 l3: 0000000000000000 l4: 0000000000000000 l5: 000000000070c920 l6: 0000000000000000 l7: 0000000000000000 i0: fffff80013d55e50 i1: fffff8001063af9e i2: fffff8001063b0f0 i3: 0000000000000000 i4: 00000000006bf240 i5: ffffffffffffffff i6: fffff8001063a6e1 i7: 000000000051c34c Instruction DUMP: d05e2028 808ae001 02600004 <e05a2010> 9a102001 e64620b4 808ae080 0240000c 808ae040

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Intel 82810E GMCH northbridge implementation
by Shubhangi Jadhav 15 Apr '03

15 Apr '03

Hi, To port LinuxBIOS to our motherboard, we need to implement support for the northbridge. The northbridge is Intel 82810E GMCH. May I know how easy/difficult it would be to implement the northbridge? Any suggestions on how to go about implementing this ? Thanks, Shubhangi

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Significance of cpu p5/p6 in config file
by Shubhangi Jadhav 15 Apr '03

15 Apr '03

Hi, Could someone tell me the significance of cpu p5 cpu p6 I've found these in most of the mainboard config files. I'm trying to port LinuxBIOS to a motherboard with via C3 processor. Do I need to include the above statements in my config file. Thanks, Shubhangi

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flash_rom and tiger-i7501
by Will Dinkel 15 Apr '03

15 Apr '03

flash_rom experts: Has anyone managed to successfully flash a tiger-i7501 with flash_rom? On all of my attempts it can't manage to find an EEPROM: ---------------- Calibrating timer since microsleep sucks ... takes a second Setting up microsecond timing loop 485M loops per second OK, calibrated, now do the deed Enabling flash write on E7500...OK Trying Am29F040B, 512 KB probe_29f040b: id1 0x1f, id2 0x8b Trying At29C040A, 512 KB probe_jedec: id1 0xbf, id2 0x60 Trying Mx29f002, 256 KB probe_29f002: id1 191, id2 96 Trying SST29EE020A, 256 KB probe_jedec: id1 0xbf, id2 0x60 Trying SST28SF040A, 512 KB probe_28sf040: id1 0x1f, id2 0x8b Trying SST39SF020A, 256 KB probe_39sf020: id1 0xbf, id2 0x60 Trying SST39VF020, 256 KB probe_39sf020: id1 0xbf, id2 0x60 Trying W29C011, 128 KB probe_jedec: id1 0xbf, id2 0x60 Trying W29C020C, 256 KB probe_jedec: id1 0xbf, id2 0x60 Trying W49F002U, 256 KB probe_49f002: id1 0xbf, id2 0x60 Trying M29F400BT, 512 KB probe_m29f400bt: id1 0x1f, id2 0x8 Trying 82802ab, 512 KB probe_82802ab: id1 0x1f, id2 0x8b Trying 82802ac, 1024 KB probe_82802ab: id1 0x1f, id2 0x8b EEPROM not found ----------------- -- Will Dinkel Atipa Technologies wdinkel(a)atipa.com (785) 841-9513 x3111 http://www.atipa.com

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[COMMIT] sync up pass 3
by ebiederman＠lnxi.com 14 Apr '03

14 Apr '03

First stab at synchronizing the questionable code. The NLBConfig.py and getpir changes are safe simple changes. The read_bytes.h and rom_fill_inbuf.c removes tag support from LinuxBIOS altogether. The code is in the baremetal toolkit so we should not need it bloating the common code. Eric include/rom/read_bytes.h - Remove baremetal toolkit code src/rom/rom_fill_inbuf.c - Remove tag support util/config/NLBConfig.py - Remove crt0.o from OBJECTS-1 util/getpir/Makefile - set LINUXBSIOSROOT to an always working path

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coreboot April 2003