coreboot February 2003

coreboot@coreboot.org

54 participants
101 discussions

help!!!who can explain the interface between linuxbios and linux.
by �� 19 Feb '03

19 Feb '03

dear all: I have developed a linuxbios debug system succefully.I introduced gdb stub into my system. In my system ,developers can debug linuxbios at source code level. I setup the stub at the beginning of the begin of the function of hardwaremain, the first c function.Now the system can excute the function of "step",'step into" "step out" ,"breakpoint"and so on. but the system has not been tested fully. I wonder if my design is usefull to others. by the way, I have several question.I will appreciate anyone's any idea! my question are as follows: 1. As we know, traditonal BIOS not only do some initialization work, but also put some data about the hardware in somewhere.BIOS even offer some routine such as intx( I know that In linux souce file "setup.s",int10, int13and int15 are used),but linuxbios doesn't offer. my question is: what is the mininal need of linux kernel's starting? what data does It need in detail? where does the data need to be placed in detail? what routine does linux kernel need for it's starting ? how does linuxbios offer these data and routines? 2. the second question is about PCI. I found that in linuxbios, some PCI initialization work is done.as we know ,in linux kernel, the same work was be done.Some linuxbios PCI initialization code is even the same with linux kernel. my question is: if the initialization in linuxbios is necessary? 3. my third question is about etherboot. I get a ide-patch of etherboot, and I succefully boot my system via IDE .I have read the code for a long time,but still have no idea about it. I found it seems does not do the same as setup.s,the kernel loader of traditional linux.who can explain it to me? I know there are some clever and experienced man in this site.I am very interested in this topic and admire all the man with good skills.I am looking forward to some help. best regards! yours HaimingWang

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question about option parameter
by Terry B. Chen 19 Feb '03

19 Feb '03

Hi all: Because the payload for normal image is too big, so I have to make one 1MB Linuxbios rom. Then I change the option ROM_SIZE=1048576 but I get a rom of 1,343,488. someone can help me?

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via epia, pchips 787cl+
by Alexander Amelkin 19 Feb '03

19 Feb '03

Hello! The linuxbios status comments for via epia say "etherboot" only. Does that mean that epia won't be able to boot from a local ide hard drive? Are there any plans to implement the support for lilo/whatever booting from the hard drive on epia? Another question is about the pcchips 787cl+ 3.0 board. It's sis630e + it8705. I didn't find sis630e in the list of supported devices, but I found some discussion on how to enable or disable something on that chipset. That's confusing. Is sis630e supported, or is it not? With best regards, Alexander mailto:spirit@reactor.ru

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weighing in
by steven james 19 Feb '03

19 Feb '03

Greetings, Thinking about initialization where one device's init is required to make others show up: In the cases I have seen, any devices that require another device's setup, the new device either has a higher device or function number, or it is on a subordinate bus. The mose common case is the superIO devices which require both southbridge and PnP setup. Perhaps the best thing is a provision for a function call upon scanning a device. That function would init it far enough to reveal anything behind it and no further. It could then either scan any subordinate busses and dependant devices, or just return and let the scan that found it continue to higher dev/fn numbers. G'day, sjames -- -------------------------steven james, director of research, linux labs ... ........ ..... .... 230 peachtree st nw ste 701 the original linux labs atlanta.ga.us 30303 -since 1995 http://www.linuxlabs.com office 404.577.7747 fax 404.577.7743 -----------------------------------------------------------------------

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Blurring The Line Between BIOS And OS
by Bari Ari 19 Feb '03

19 Feb '03

Anyone else see this yesterday? The Register http://www.theregister.co.uk/content/3/29374.html and Slashdot had an article http://slashdot.org/article.pl?sid=03/02/18/2228255 about "software (that resides within the system firmware and a protected area of the hard drive) that allows users on anything from servers to embedded systems to run diagnostics, browse the web and other things without having to boot into a full fledged OS." Hey let's fix broken BIOS and hardware bugs with some broken bloatware. --Bari

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help!!!who can explain the interface between linuxbios and linux.
by 王海明 19 Feb '03

19 Feb '03

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RE: irq_table.c without a pirq table?
by Ulrik Forsgren (EAB) 19 Feb '03

19 Feb '03

Hi! Here is more information. Motherboard: Jetway 656HXA. Chipset: Intel 430HX, PIIX3 Superio: Winbond 83877f Original BIOS image: http://www.jetway.com.tw/evisn/download/bios/hxa/Hxa-b02.bin The motherboards was chosen because I needed something that I could experiment with and destory without loosing anything valuable. I have "successfully" booted a Linux kernel (mounted filesystem and running /bin/sh), but I ran into a similar problem as http://www.clustermatic.org/pipermail/linuxbios/2003-February/001904.html, I couldn't bring up the NIC. The reason was that the kernel couldn't assign an IRQ to it and I associate the problem with fact that I haven't implemented an irq table yet. So I started to search for one and getpir didn't result in a hit. Here I am search for all kind of information about PCI & interrupts and irq tables.... Best Regards, /UFo -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: den 19 februari 2003 02:54 To: Ulrik Forsgren (EAB) Cc: 'linuxbios(a)clustermatic.org' Subject: Re: irq_table.c without a pirq table? "Ulrik Forsgren (EAB)" <Ulrik.Forsgren(a)epl.ericsson.se> writes: > Hi! > > I'm am testing LinuxBIOS on a Pentium motherboard that doesn't have a pirq table > in BIOS and I suppose that Linux requires a pirq table to be able route the irqs > to the PCI boards. > > I have scanned the original BIOS without finding the PIRQ tag. > > How can I create an irq_table.c when I can't copy it from the original BIOS? > > PCIBIOS 2.1 calls? Or looking at the irqs assigned on the pci bus and at the irq router. Or looking at the MP table. Or looking through the information provided by ACPI. Eric

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winbond 83977ef problem
by zhu shi song 19 Feb '03

19 Feb '03

I'm using ec3 mainboard, it just like advantech pcm-5823, except ec3 use winbond 83977f as superio. the config file of the ec3 mainboard is as follows: # Copyright (c) 2002 Christer Weinigel <wingel(a)hack.org> # This is a config file for the evoc ec3 mainboard # The board is a National Semiconductor GX1 + CS5530 + winbond 83977f # design. It is a fairly complete PC with VGA, two serial port, one parallel port, two USB ports, a PS/2 Keyboard # connector (can also be used for a PS/2 Mouse using a splitter # cable), floppy, IDE and finally one ethernet port using a RTL8139C # ethernet chip. Other than that the board has a DiskOnChip socket # and a PC104 connector for expansion. arch i386 cpu p5 mainboardinit cpu/i386/entry16.inc mainboardinit cpu/i386/entry32.inc ldscript cpu/i386/entry16.lds ldscript cpu/i386/entry32.lds mainboardinit cpu/i386/reset16.inc ldscript cpu/i386/reset16.lds ######################################################################## option SERIAL_SUPERIO_BASEADDRESS=0x3f0 mainboardinit superio/winbond/w83977fa/setup_serial.inc mainboardinit pc80/serial.inc mainboardinit arch/i386/lib/console.inc ######################################################################## northbridge nsc/gx1 southbridge nsc/cs5530 nsuperio winbond/w83977ef keyboard=1 com1={1} com2={1} floppy=1 ######################################################################## # Lots of constans, you probably don't need to change anything here. "Config" 66 lines, 2139 characters # Lots of constans, you probably don't need to change anything here. # GX_BASE is the address of a configuration memory region for the GX1 # processor. You probably don't want to change this. option GX_BASE=0x40000000 ######################################################################## # Southbridge configuration # no need to assign INTA-D, since it is done by pirq table # option CS5530_INTA=9 # option CS5530_INTB=10 # option CS5530_INTC=11 # option CS5530_INTD=15 option CS5530_PRIMARY_IDE=1 option CS5530_SECONDARY_IDE=1 ######################################################################## option NO_KEYBOARD=1 option FINAL_MAINBOARD_FIXUP=1 object mainboard.o object irq_tables.o option ZKERNEL_START=0xfffc0000 option HAVE_PIRQ_TABLE=1 # Local variables: # compile-command: "make -C /export/bios/voyager2" # End: But when entering winbond configuration mode, ec3 halt. part of crt0.s as following: ........ movb $ 0x88 , %al ; outb %al, $0x80 /*work ok, can see it from pc diagnostic card*/ movb $0x87 , %al; movw 0x3f0 , %dx; outb %al, %dx ; outb %al,$0xeb /* halt*/ movb $ 0x89 , %al ; outb %al, $0x80 /*can't see it from pc dianostic card*/ movb $0x87 , %al; movw 0x3f0 , %dx; outb %al, %dx ; outb %al,$0xeb movb $ 0x90 , %al ; outb %al, $0x80 movb $7 , %al; movw 0x3f0 , %dx; outb %al, %dx ; outb %al,$0xeb movb $2 , %al; movw 0x3f0 +1 , %dx; outb %al, %dx ; outb %al,$0xeb movb $ 0x90 , %al ; outb %al, $0x80 movb $0x30 , %al; movw 0x3f0 , %dx; outb %al, %dx ; outb %al,$0xeb movb $1 , %al; movw 0x3f0 +1 , %dx; outb %al, %dx ; outb %al,$0xeb movb $0x24 , %al; movw 0x3f0 , %dx; outb %al, %dx ; outb %al,$0xeb movb $0xa4 , %al; movw 0x3f0 +1 , %dx; outb %al, %dx ; outb %al,$0xeb movb $0x2b , %al; movw 0x3f0 , %dx; outb %al, %dx ; outb %al,$0xeb movb $0x1 , %al; movw 0x3f0 +1 , %dx; outb %al, %dx ; outb %al,$0xeb what's the problem? zhu --------------------------------- Do you Yahoo!? Yahoo! Shopping - Send Flowers for Valentine's Day

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winbond 83977ef problem
by zhu shi song 19 Feb '03

19 Feb '03

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Re: 440BX/PIIX4E motherboard
by ebiederman＠lnxi.com 18 Feb '03

18 Feb '03

"Pye, Nick" <Nick.Pye(a)rexam.com> writes: > Hi What utils are available to burn the image directly to a DoC via the BIOS > socket on a 440BX/PIIX4E motherboard ? The mtd kernel drivers... Eric

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coreboot February 2003