coreboot October 2002

coreboot@coreboot.org

77 participants
164 discussions

DSP TI5402 kit simulator in linux
by Karthik Bala Guru 11 Oct '02

11 Oct '02

hi, Is it possible to run DSP kits using linux ?? Is there any simulator for these ??? is there any simulator for Texas instruments DSP kit(5402) ? How about ADSP kits ?? Thanking You, karthik bala guru ________________________________________________________________________ Missed your favourite TV serial last night? Try the new, Yahoo! TV. visit http://in.tv.yahoo.com

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ipl.S of sis735 code compile fail
by David Xiong 10 Oct '02

10 Oct '02

Hello everyone, I have a mainboard elite k7s5a, the chipset is sis735. When I make linuxbios for it, the compiler shows freebios/src/southnorthbridge/sis/735/ipl.S has errors. Can someone give me a patch? Thanks! David Xiong

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[COMMIT] batch 3 E7500 support...
by Eric W Biederman 10 Oct '02

10 Oct '02

src/northbridge/intel/E7500/{sync the directory} src/ram/ramtest.inc{Add movnti ... } src/southbridge/intel/82801ca/{sync the directory} src/southbridge/intel/82870/{sync the directory} src/southbridge/via/vt8231/southgbridge.c - Transform intel_conf_xxx into pcibios_xxxx src/southbridge/via/v82c686/southgbridge.c - Transform intel_conf_xxx into pcibios_xxxx src/winbond/w83627hf/Config - Enable the hardware monitor - Add support for turning on the power_led util/config/NLBConfig.py - Add support for object <something>.c - Add support for object <something>.S - recode how the list of source files is built up. util/lb-dump/dump_lb_table.c - Fix the memory size abreviations Eric

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[COMMIT] Batch 2
by Eric W Biederman 10 Oct '02

10 Oct '02

AUTHORS - Add myself src/cpu/p5/delay_tsc.c - Fix the indentation - Don't have the new calibrate_tsc function directly update global variables. src/include/smp/start_stop.h - Change #ifdef SMP to #if SMP == 1 src/include/string.h - Declare sprintf src/lib/elfboot.c - Minor fixes to verify_loaded_image - Change all of the new debugging messages to printk_spew src/lib/inflate.c - Remove sensless warning message fixes src/lib/linuxpci.c - move declaration of sprintf to string.h - Better detection of read only bars in pci_get_resource - Remove pci_noop - Remove warning about set_pci_dev_ops not being finished src/lib/src.c - change #ifdef SERIAL_POST to #if SERIAL_POST in post_code Eric

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[COMMIT] Start of merging my tree and the LinuxBIOS tree
by Eric W Biederman 10 Oct '02

10 Oct '02

A lot of small differences have accumulated between my tree and the main LinuxBIOS tree. Some of them are hacks that I need to generalize before putting them in the public tree. So I am taking this in small manageable chunks. Holler if anything looks to nasty. src/arch/i386/boot/boot.c - Tone down the severity of error messages src/arch/i386/lib/console.inc - Preserve morre registers in __CONSOLE_INLINE_TX_HEX8 src/arch/i386/lib/hardwaremain.c - Fixup the cmos option to handle multiple cpus - Move pci setup before ramsize initialization - Renable keyboard_on src/arch/i386/smp/Config Add secondary.S src/arch/i386/smp/secondary.S - add src/arch/i386/smp/secondary.inc - remove src/arch/i386/smp/start_stop.c - Remove unused variables src/config/Config - Cleanup the cross compiling options - Rename cmos.conf cmos.layout as the previous name was too confusing src/cpu/p6/mtrr.c - Create subroutines to enable/disable caching - Call them in all of the appropriate places - Add an extra argument to range_to_mtrr to allow for future optimizations Eric

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There is something odd going on with eepro-100
by Ronald G Minnich 10 Oct '02

10 Oct '02

Here is the scenario. This is a pre-release etherboot from Eric that has worked well on a number of platforms. The version is 5.1.2rc4.eb5. I take two identical advantech PCM-5283-2 systems, and put in a linuxbios flash that has worked fine for many months on a PCM-5823-1. The Etherboot I have built will boot preferentially from Compact Flash, loading a kernel and initrd which uses eepro100 to contact a server. If no flash is found, then it does a boot over Ethernet. System A System B CF boot Linux Works Works No CF, boot net Works Fails; sends DHCP but never sees reply. Packet is visible on network and dhcpd responds So, we have an interface which seems to work, and works on linux. It's basically the same board. etherboot correctly reads the MAC address from ROM. dhcpd sees packets from etherboot in both cases and responds. But System B never sees the reply ... this is really very odd. Here is the best part of all. An older flash, running etherboot 5.0.6, System B works fine. Yikes! I have no idea what relationship this has, if any, to the Smartcore problem I have been having, but it is at least pretty suspicious. The symptoms are almost identical. Anyway, I'm going to stick with CF for now but wanted to let the community know what was up. ron

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Ram problem
by steven james 10 Oct '02

10 Oct '02

Greetings, I'm trying to get ram working on an e7500 MCH. It seems to be actually initting, but when I run ramtest it, I consistantly see a single bit toggled when reading back such as: 00024ab4:00024a94 00024abc:00024a9c 00024ad4:00024af4 00024adc:00024afc 00024af4:00024ad4 00024afc:00024adc 00024b14:00024b34 00024b1c:00024b3c 00024b34:00024b14 00024b3c:00024b1c 00024b54:00024b74 00024b5c:00024b7c 00024b74:00024b54 00024b7c:00024b5c 00024b94:00024bb4 00024b9c:00024bbc 00024bb4:00024b94 00024bbc:00024b9c 00024bd4:00024bf4 00024bdc:00024bfc Other times, I see that the second read (in order to display the bad value) actually reads successfully such as 000127a8:000127a8 Does anyone have any ideas what might cause that? G'day, sjames -- -------------------------steven james, director of research, linux labs ... ........ ..... .... 230 peachtree st nw ste 701 the original linux labs atlanta.ga.us 30303 -since 1995 http://www.linuxlabs.com office 404.577.7747 fax 404.577.7743 -----------------------------------------------------------------------

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ServerWorks...
by Courchesne, Andre 10 Oct '02

10 Oct '02

Hi all, I am new to the list. I would like to know is there are any development done for the ServerWorks chipsets. Thanks, Andre Courchesne

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LinuxBios support for Via Mini-ITX motherboard
by Pierre-Yves Kerembellec 10 Oct '02

10 Oct '02

Hi all, I'm pretty sure this question has already been asked a thousand times, but I'd just like to know the status of the LinuxBios support on the VIA Mini-ITX motherboards (typically C3-based). I've seen things like mainboard/via/epia, src/northbridge/via/vt8601, src/southbridge/via/vt8231 or superio/via/vt8231 in the source tree but I don't know the exact status of the port ... the status on the web page does not state anything else ... Did anyone successfully used LinuxBios on the Eden platform ? Many thanks, Pierre-Yves

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PIRQ checksum drama
by John Usher (Maptek) 10 Oct '02

10 Oct '02

G'day all... I am currently having trouble with the irq_tables.c produced by getpir. I am receiving the following error from the linuxbios boot: Checking IRQ routing tables.../root/aug2002/lb/freebios/src/arch/i386/lib/pirq_routing.c: 24:check_pirq_routing_table() - irq_routing_table located at: 0x0000b0c0 /root/aug2002/lb/freebios/src/arch/i386/lib/pirq_routing.c: 31:check_pirq_routing_table() - checksum is: 0x26 but should be: 0x7a /root/aug2002/lb/freebios/src/arch/i386/lib/pirq_routing.c: 49:check_pirq_routing_table() - checksum error in irq routing table done. Copying IRQ routing tables to 0xf0000...done. As can be seen from irq_tables.c, the checksum internally is 0x26, and getpir did not report any errors when it downloaded the table. Does anyone have any ideas? John... irq_tables.c follows: /* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */ #include <arch/pirq_routing.h> const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ 32+16*8, /* there can be total 8 devices on the bus */ 0, /* Where the interrupt router lies (bus) */ 0x38, /* Where the interrupt router lies (dev) */ 0xe00, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x7000, /* Device */ 0, /* Crap (miniport) */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x26, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { {0,0x48, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0}, {0,0x50, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0}, {0,0x58, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x3, 0}, {0,0x60, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}}, 0x4, 0}, {0,0x68, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x5, 0}, {0,0x70, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x6, 0}, {0,0x39, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0, 0}, {0,0x8, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0, 0}, } };

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coreboot October 2002