Ok, I have put back the debug.c stuff for the i440lx chipset. Here is the result:
coreboot-4.0-1853-gf285e04-dirty Mon Nov 14 21:02:02 CET 2011 starting... Northbridge prior to SDRAM init: PCI: 00:00.00 00: 86 80 80 71 06 00 90 22 03 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 04 00 00 83 00 00 00 01 00 00 00 00 00 00 00 00 60: 01 01 01 01 01 01 01 01 00 00 00 00 55 55 55 55 70: 00 10 02 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: c0 00 00 00 10 18 00 00 00 00 00 00 00 00 00 00 a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 fd 03 20 0f 00 00 00 00 00 00 APBASE 000000a0 ******************* *** Here the first value is missing, because of compiler trouble ******************* Set register 0x to 0x84 readed 0x84 OK Set register 0x to 0xc3 readed 0xc3 OK Set register 0x to 0xff readed 0xff OK Set register 0x to 0xff readed 0xff OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x30 readed 0x30 OK Set register 0x to 0x33 readed 0x33 OK Set register 0x to 0x33 readed 0x33 OK Set register 0x to 0x33 readed 0x33 OK Set register 0x to 0x33 readed 0x33 OK Set register 0x to 0x33 readed 0x33 OK Set register 0x to 0x33 readed 0x33 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Set register 0x to 0x00 readed 0x00 OK Northbridge atexit sdram set registers PCI: 00:00.00 00: 86 80 80 71 06 00 90 22 03 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 04 84 00 c3 00 ff ff 00 00 30 33 33 33 33 33 33 60: 00 00 00 00 00 00 00 00 00 00 00 00 55 55 55 55 70: 00 10 02 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: c0 00 00 00 10 18 00 00 00 00 00 00 00 00 00 00 a0: 02 00 10 00 03 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 fd 03 20 0f 00 00 00 00 00 00 DIMM00 rows: 01 rowsize: 10 modulesize: 0008 DRT ffff fffe DIMM01 rows: ff rowsize: ff modulesize: 0000 DIMM02 rows: ff rowsize: ff modulesize: 0000 DIMM03 rows: ff rowsize: ff modulesize: 0000 RAM Enable 1: Apply NOP RAM Enable 2: Precharge all RAM Enable 3: CBR RAM Enable 4: Mode register set RAM Enable 5: Normal operation RAM Enable 6: Enable refresh spd_enable_refresh: dramc = 0x01 Northbridge following SDRAM init: Loading image. Searching for fallback/coreboot_ram Check pci1002,4742.rom Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (278528 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-1853-gf285e04-dirty Mon Nov 14 21:02:02 CET 2011 booting... clocks_per_usec: 402 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:07.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:07.1: enabled 1 PCI: 00:07.2: enabled 1 PCI: 00:07.3: enabled 1 PCI: 00:14.0: enabled 0 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:07.0: enabled 1 PNP: 03f0.0: enabled 1 PNP: 03f0.1: enabled 1 PNP: 03f0.2: enabled 1 PNP: 03f0.3: enabled 1 PNP: 03f0.5: enabled 1 PNP: 03f0.7: enabled 1 PNP: 03f0.8: enabled 1 PNP: 03f0.a: enabled 1 PCI: 00:07.1: enabled 1 PCI: 00:07.2: enabled 1 PCI: 00:07.3: enabled 1 PCI: 00:14.0: enabled 0 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/7180] ops PCI: 00:00.0 [8086/7180] enabled PCI: 00:01.0 [8086/7181] enabled PCI: 00:07.0 [8086/7110] bus ops PCI: 00:07.0 [8086/7110] enabled PCI: 00:07.1 [8086/7111] ops PCI: 00:07.1 [8086/7111] enabled PCI: 00:07.2 [8086/7112] ops PCI: 00:07.2 [8086/7112] enabled PCI: 00:07.3 [8086/7113] bus ops pwrmgt_enable: gpo default missing in devicetree.cb! PCI: 00:07.3 [8086/7113] enabled PCI: 00:14.0 [1274/1371] disabled PCI: 00:14.1, bad id 0x0 PCI: 00:14.2, bad id 0x0 PCI: 00:14.3, bad id 0x0 PCI: 00:14.4, bad id 0x0 PCI: 00:14.5, bad id 0x0 PCI: 00:14.6, bad id 0x0 PCI: 00:14.7, bad id 0x0 do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1002/4742] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:07.0 PNP: 03f0.0 enabled PNP: 03f0.1 enabled PNP: 03f0.2 enabled PNP: 03f0.3 enabled PNP: 03f0.5 enabled PNP: 03f0.7 enabled PNP: 03f0.8 enabled PNP: 03f0.a enabled scan_static_bus for PCI: 00:07.0 done scan_static_bus for PCI: 00:07.3 scan_static_bus for PCI: 00:07.3 done PCI: pci_scan_bus returning with max=001 scan_static_bus for Root Device done done Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0
*************************** And here it stops. What happens in this stage? Thanks for help.
chris