5 May
2009
5 May
'09
7:59 p.m.
On Tue, May 5, 2009 at 10:50 AM, Peter Stuge peter@stuge.se wrote:
No sir.
This is great!
None have single byte erase blocks, but most of the SPI flash chips can actually do 256 byte erase blocks.
Should we move to 256 byte default alignment?
I keep imagining how I will be able to safely update the coreboot normal image but keep fallback, stages and payloads untouched.
me too.
ron