Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/855
-gerrit
commit 5cc6cb3584fb6e662fcdf8a526ec2d289e248380 Author: Stefan Reinauer stefan.reinauer@coreboot.org Date: Wed Apr 4 00:09:50 2012 +0200
Add support for Intel Sandybridge CPU
Change-Id: I9f37e291c00c0640c6600d8fdd6dcc13c3e5b8d5 Signed-off-by: Duncan Laurie dlaurie@google.com Signed-off-by: Stefan Reinauer reinauer@google.com --- src/cpu/intel/Kconfig | 2 + src/cpu/intel/Makefile.inc | 3 + src/cpu/intel/microcode/update-microcodes.sh | 6 +- src/cpu/intel/model_206ax/Kconfig | 53 ++ src/cpu/intel/model_206ax/Makefile.inc | 8 + src/cpu/intel/model_206ax/acpi.c | 357 ++++++++++++ src/cpu/intel/model_206ax/acpi/cpu.asl | 91 +++ src/cpu/intel/model_206ax/bootblock.c | 152 +++++ src/cpu/intel/model_206ax/cache_as_ram.inc | 348 +++++++++++ src/cpu/intel/model_206ax/chip.h | 37 ++ src/cpu/intel/model_206ax/finalize.c | 60 ++ .../model_206ax/microcode-m12206a7_00000025.h | 611 ++++++++++++++++++++ src/cpu/intel/model_206ax/model_206ax.h | 98 ++++ src/cpu/intel/model_206ax/model_206ax_init.c | 558 ++++++++++++++++++ src/cpu/intel/model_206ax/x06_microcode.h | 31 + src/cpu/intel/socket_rPGA989/Kconfig | 16 + src/cpu/intel/socket_rPGA989/Makefile.inc | 8 + src/cpu/intel/socket_rPGA989/chip.h | 4 + src/cpu/intel/socket_rPGA989/socket_rPGA989.c | 6 + 19 files changed, 2446 insertions(+), 3 deletions(-)
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 81a834c..c6dab12 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -9,6 +9,7 @@ source src/cpu/intel/model_6ex/Kconfig source src/cpu/intel/model_6fx/Kconfig source src/cpu/intel/model_1067x/Kconfig source src/cpu/intel/model_106cx/Kconfig +source src/cpu/intel/model_206ax/Kconfig source src/cpu/intel/model_f0x/Kconfig source src/cpu/intel/model_f1x/Kconfig source src/cpu/intel/model_f2x/Kconfig @@ -29,3 +30,4 @@ source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_PGA370/Kconfig source src/cpu/intel/socket_441/Kconfig source src/cpu/intel/socket_LGA771/Kconfig +source src/cpu/intel/socket_rPGA989/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 05f947d..9e498f1 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -14,6 +14,9 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989 +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771 diff --git a/src/cpu/intel/microcode/update-microcodes.sh b/src/cpu/intel/microcode/update-microcodes.sh index 7a234a8..cd1428a 100755 --- a/src/cpu/intel/microcode/update-microcodes.sh +++ b/src/cpu/intel/microcode/update-microcodes.sh @@ -18,10 +18,10 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #
-MICROCODE_VERSION=20100914 +MICROCODE_VERSION=20111110 MICROCODE_ARCHIVE=microcode-$MICROCODE_VERSION.tgz -MICROCODE_FILE=microcode-$MICROCODE_VERSION.dat -INTEL_MICROCODE=http://downloadmirror.intel.com/19342/eng/$MICROCODE_ARCHIVE +MICROCODE_FILE=microcode.dat +INTEL_MICROCODE=http://downloadmirror.intel.com/20728/eng/$MICROCODE_ARCHIVE
# # Getting Intel(R) Microcode diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig new file mode 100644 index 0000000..c11f21a --- /dev/null +++ b/src/cpu/intel/model_206ax/Kconfig @@ -0,0 +1,53 @@ +config CPU_INTEL_MODEL_206AX + bool + +config CPU_INTEL_MODEL_306AX + bool + +if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX + +config CPU_SPECIFIC_OPTIONS + def_bool y + select SMP + select SSE2 + select UDELAY_LAPIC + select SMM_TSEG + #select AP_IN_SIPI_WAIT + +config BOOTBLOCK_CPU_INIT + string + default "cpu/intel/model_206ax/bootblock.c" + +config SERIAL_CPU_INIT + bool + default n + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + +endif + +if CPU_INTEL_MODEL_206AX + config CPU_MODEL_NAME + string + default "Intel SandyBridge CPU" + + config CPU_MODEL_INDEX + hex + default 0x2a +endif + +if CPU_INTEL_MODEL_306AX + config CPU_MODEL_NAME + string + default "Intel IvyBridge CPU" + + config CPU_MODEL_INDEX + hex + default 0x3a +endif diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc new file mode 100644 index 0000000..e9b8e6d --- /dev/null +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -0,0 +1,8 @@ +driver-y += model_206ax_init.c +subdirs-y += ../../x86/name + +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c + +cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c new file mode 100644 index 0000000..3a3a1fd --- /dev/null +++ b/src/cpu/intel/model_206ax/acpi.c @@ -0,0 +1,357 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/acpi.h> +#include <cpu/intel/speedstep.h> +#include <cpu/intel/turbo.h> +#include <device/device.h> +#include <device/pci.h> +#include "model_206ax.h" +#include "chip.h" + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + switch (c.x86_model) { + case CONFIG_CPU_MODEL_INDEX: + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + break; + default: + cores = (cpuid_ebx(1) >> 16) & 0xff; + break; + } + + return cores; +} + +static int generate_cstate_entries(acpi_cstate_t *cstates, + int c1, int c2, int c3) +{ + int length, cstate_count = 0; + + /* Count number of active C-states */ + if (c1 > 0) + ++cstate_count; + if (c2 > 0) + ++cstate_count; + if (c3 > 0) + ++cstate_count; + if (!cstate_count) + return 0; + + length = acpigen_write_package(cstate_count + 1); + length += acpigen_write_byte(cstate_count); + + /* Add an entry if the level is enabled */ + if (c1 > 0) + length += acpigen_write_CST_package(1, &cstates[c1]); + if (c2 > 0) + length += acpigen_write_CST_package(2, &cstates[c2]); + if (c3 > 0) + length += acpigen_write_CST_package(3, &cstates[c3]); + + acpigen_patch_len(length - 1); + return length; +} + +static int generate_C_state_entries(void) +{ + struct cpu_info *info; + struct cpu_driver *cpu; + int len, lenif; + device_t lapic; + struct cpu_intel_model_206ax_config *conf = NULL; + + /* Find the SpeedStep CPU in the device tree using magic APIC ID */ + lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); + if (!lapic) + return 0; + conf = lapic->chip_info; + if (!conf) + return 0; + + /* Find CPU map of supported C-states */ + info = cpu_info(); + if (!info) + return 0; + cpu = find_cpu_driver(info->cpu); + if (!cpu || !cpu->cstates) + return 0; + + len = acpigen_emit_byte(0x14); /* MethodOp */ + len += acpigen_write_len_f(); /* PkgLength */ + len += acpigen_emit_namestring("_CST"); + len += acpigen_emit_byte(0x00); /* No Arguments */ + + /* If running on AC power */ + len += acpigen_emit_byte(0xa0); /* IfOp */ + lenif = acpigen_write_len_f(); /* PkgLength */ + lenif += acpigen_emit_namestring("PWRS"); + lenif += acpigen_emit_byte(0xa4); /* ReturnOp */ + lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower, + conf->c2_acpower, conf->c3_acpower); + acpigen_patch_len(lenif - 1); + len += lenif; + + /* Else on battery power */ + len += acpigen_emit_byte(0xa4); /* ReturnOp */ + len += generate_cstate_entries(cpu->cstates, conf->c1_battery, + conf->c2_battery, conf->c3_battery); + acpigen_patch_len(len - 1); + return len; +} + +static acpi_tstate_t tss_table_fine[] = { + { 100, 1000, 0, 0x00, 0 }, + { 94, 940, 0, 0x1f, 0 }, + { 88, 880, 0, 0x1e, 0 }, + { 82, 820, 0, 0x1d, 0 }, + { 75, 760, 0, 0x1c, 0 }, + { 69, 700, 0, 0x1b, 0 }, + { 63, 640, 0, 0x1a, 0 }, + { 57, 580, 0, 0x19, 0 }, + { 50, 520, 0, 0x18, 0 }, + { 44, 460, 0, 0x17, 0 }, + { 38, 400, 0, 0x16, 0 }, + { 32, 340, 0, 0x15, 0 }, + { 25, 280, 0, 0x14, 0 }, + { 19, 220, 0, 0x13, 0 }, + { 13, 160, 0, 0x12, 0 }, +}; + +static acpi_tstate_t tss_table_coarse[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1f, 0 }, + { 75, 750, 0, 0x1e, 0 }, + { 63, 625, 0, 0x1d, 0 }, + { 50, 500, 0, 0x1c, 0 }, + { 38, 375, 0, 0x1b, 0 }, + { 25, 250, 0, 0x1a, 0 }, + { 13, 125, 0, 0x19, 0 }, +}; + +static int generate_T_state_entries(int core, int cores_per_package) +{ + int len; + + /* Indicate SW_ALL coordination for T-states */ + len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + len += acpigen_write_empty_PTC(); + + /* Set a T-state limit that can be modified in NVS */ + len += acpigen_write_TPC("\TLVL"); + + /* + * CPUID.(EAX=6):EAX[5] indicates support + * for extended throttle levels. + */ + if (cpuid_eax(6) & (1 << 5)) + len += acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_fine), tss_table_fine); + else + len += acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_coarse), tss_table_coarse); + + return len; +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + +static int generate_P_state_entries(int core, int cores_per_package) +{ + int len, len_pss; + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) + coord_type = SW_ANY; + else + coord_type = HW_ALL; + + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; /* Max Non-Turbo Ratio */ + clock_max = ratio_max * SANDYBRIDGE_BCLK; + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = rdmsr(MSR_PKG_POWER_SKU); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + len = acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + len += acpigen_write_PPC(0); + + /* Write PSD indicating configured coordination type */ + len += acpigen_write_PSD_package(core, cores_per_package, coord_type); + + /* Add P-state entries in _PSS table */ + len += acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = (ratio_max - ratio_min) / ratio_step; + while (num_entries > PSS_MAX_ENTRIES-1) { + ratio_step <<= 1; + num_entries >>= 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + len_pss = acpigen_write_package(num_entries + 2); + + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + len_pss += acpigen_write_PSS_package( + clock_max + 1, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_turbo << 8, /*control*/ + ratio_turbo << 8); /*status*/ + } else { + /* _PSS package count without Turbo */ + len_pss = acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + len_pss += acpigen_write_PSS_package( + clock_max, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_max << 8, /*control*/ + ratio_max << 8); /*status*/ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * SANDYBRIDGE_BCLK; + + len_pss += acpigen_write_PSS_package( + clock, /*MHz*/ + power, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio << 8, /*control*/ + ratio << 8); /*status*/ + } + + /* Fix package length */ + len_pss--; + acpigen_patch_len(len_pss); + + return len + len_pss; +} + +void generate_cpu_entries(void) +{ + int len_pr; + int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpuID=1; cpuID <=numcpus; cpuID++) { + for (coreID=1; coreID<=cores_per_package; coreID++) { + if (coreID>1) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor _PR.CPUx */ + len_pr = acpigen_write_processor( + (cpuID-1)*cores_per_package+coreID-1, + pcontrol_blk, plen); + + /* Generate P-state tables */ + len_pr += generate_P_state_entries( + cpuID-1, cores_per_package); + + /* Generate C-state tables */ + len_pr += generate_C_state_entries(); + + /* Generate T-state tables */ + len_pr += generate_T_state_entries( + cpuID-1, cores_per_package); + + len_pr--; + acpigen_patch_len(len_pr); + } + } +} + +struct chip_operations cpu_intel_model_206ax_ops = { + CHIP_NAME(CONFIG_CPU_MODEL_NAME) +}; diff --git a/src/cpu/intel/model_206ax/acpi/cpu.asl b/src/cpu/intel/model_206ax/acpi/cpu.asl new file mode 100644 index 0000000..a9d5eeb --- /dev/null +++ b/src/cpu/intel/model_206ax/acpi/cpu.asl @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* These devices are created at runtime */ +External (_PR.CPU0, DeviceObj) +External (_PR.CPU1, DeviceObj) +External (_PR.CPU2, DeviceObj) +External (_PR.CPU3, DeviceObj) +External (_PR.CPU4, DeviceObj) +External (_PR.CPU5, DeviceObj) +External (_PR.CPU6, DeviceObj) +External (_PR.CPU7, DeviceObj) + +/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ +Method (PNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (_PR.CPU0, 0x80) // _PPC + Notify (_PR.CPU0, 0x81) // _CST + Notify (_PR.CPU1, 0x80) // _PPC + Notify (_PR.CPU1, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (_PR.CPU2, 0x80) // _PPC + Notify (_PR.CPU2, 0x81) // _CST + Notify (_PR.CPU3, 0x80) // _PPC + Notify (_PR.CPU3, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (_PR.CPU4, 0x80) // _PPC + Notify (_PR.CPU4, 0x81) // _CST + Notify (_PR.CPU5, 0x80) // _PPC + Notify (_PR.CPU5, 0x81) // _CST + Notify (_PR.CPU6, 0x80) // _PPC + Notify (_PR.CPU6, 0x81) // _CST + Notify (_PR.CPU7, 0x80) // _PPC + Notify (_PR.CPU7, 0x81) // _CST + } +} + +/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ +Method (TNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (_PR.CPU0, 0x82) // _TPC + Notify (_PR.CPU1, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (_PR.CPU2, 0x82) // _TPC + Notify (_PR.CPU3, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 8)) { + Notify (_PR.CPU4, 0x82) // _TPC + Notify (_PR.CPU5, 0x82) // _TPC + Notify (_PR.CPU6, 0x82) // _TPC + Notify (_PR.CPU7, 0x82) // _TPC + } +} + +/* Return a package containing enabled processor entries */ +Method (PPKG) +{ + If (LGreaterEqual (\PCNT, 8)) { + Return (Package() {_PR.CPU0, _PR.CPU1, _PR.CPU2, _PR.CPU3, + _PR.CPU4, _PR.CPU5, _PR.CPU6, _PR.CPU7}) + } ElseIf (LGreaterEqual (\PCNT, 4)) { + Return (Package() {_PR.CPU0, _PR.CPU1, _PR.CPU2, _PR.CPU3}) + } ElseIf (LGreaterEqual (\PCNT, 2)) { + Return (Package() {_PR.CPU0, _PR.CPU1}) + } Else { + Return (Package() {_PR.CPU0}) + } +} diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c new file mode 100644 index 0000000..7925315 --- /dev/null +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> + +static const uint32_t microcode_updates[] = { + #include "x06_microcode.h" +}; + +struct microcode { + u32 hdrver; /* Header Version */ + u32 rev; /* Patch ID */ + u32 date; /* DATE */ + u32 sig; /* CPUID */ + + u32 cksum; /* Checksum */ + u32 ldrver; /* Loader Version */ + u32 pf; /* Platform ID */ + + u32 data_size; /* Data size */ + u32 total_size; /* Total size */ + + u32 reserved[3]; + u32 bits[1012]; +}; + +static inline u32 read_microcode_rev(void) +{ + /* Some Intel Cpus can be very finicky about the + * CPUID sequence used. So this is implemented in + * assembly so that it works reliably. + */ + msr_t msr; + __asm__ volatile ( + "wrmsr\n\t" + "xorl %%eax, %%eax\n\t" + "xorl %%edx, %%edx\n\t" + "movl $0x8b, %%ecx\n\t" + "wrmsr\n\t" + "movl $0x01, %%eax\n\t" + "cpuid\n\t" + "movl $0x08b, %%ecx\n\t" + "rdmsr \n\t" + : /* outputs */ + "=a" (msr.lo), "=d" (msr.hi) + : /* inputs */ + : /* trashed */ + "ecx" + ); + return msr.hi; +} + +void intel_update_microcode(const void *microcode_updates) +{ + unsigned int eax; + unsigned int pf, rev, sig; + unsigned int x86_model, x86_family; + const struct microcode *m; + const char *c; + msr_t msr; + + /* cpuid sets msr 0x8B iff a microcode update has been loaded. */ + msr.lo = 0; + msr.hi = 0; + wrmsr(0x8B, msr); + eax = cpuid_eax(1); + msr = rdmsr(0x8B); + rev = msr.hi; + x86_model = (eax >>4) & 0x0f; + x86_family = (eax >>8) & 0x0f; + sig = eax; + + pf = 0; + if ((x86_model >= 5)||(x86_family>6)) { + msr = rdmsr(0x17); + pf = 1 << ((msr.hi >> 18) & 7); + } + + m = microcode_updates; + for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { + if ((m->sig == sig) && (m->pf & pf)) { + unsigned int new_rev; + msr.lo = (unsigned long)(&m->bits) & 0xffffffff; + msr.hi = 0; + wrmsr(0x79, msr); + + /* Read back the new microcode version */ + new_rev = read_microcode_rev(); + break; + } + if (m->total_size) { + c += m->total_size; + } else { + c += 2048; + } + } +} + +static void set_var_mtrr( + unsigned reg, unsigned base, unsigned size, unsigned type) + +{ + /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ + /* FIXME: It only support 4G less range */ + msr_t basem, maskm; + basem.lo = base | type; + basem.hi = 0; + wrmsr(MTRRphysBase_MSR(reg), basem); + maskm.lo = ~(size - 1) | MTRRphysMaskValid; + maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRRphysMask_MSR(reg), maskm); +} + +static void enable_rom_caching(void) +{ + msr_t msr; + + disable_cache(); + set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); + enable_cache(); + + /* Enable Variable MTRRs */ + msr.hi = 0x00000000; + msr.lo = 0x00000800; + wrmsr(MTRRdefType_MSR, msr); +} + +static void bootblock_cpu_init(void) +{ + enable_rom_caching(); + intel_update_microcode(microcode_updates); +} diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc new file mode 100644 index 0000000..c4d3701 --- /dev/null +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -0,0 +1,348 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich rminnich@gmail.com + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/x86/stack.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/post_code.h> +#include <cbmem.h> + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +/* Cache 4GB - MRC_SIZE_KB for MRC */ +#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) +#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) + +#define CPU_MAXPHYSADDR 36 +#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1) + +#define NoEvictMod_MSR 0x2e0 + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* All CPUs need to be in Wait for SIPI state */ +wait_for_sipi: + movl (%esi), %eax + bt $12, %eax + jc wait_for_sipi + + post_code(0x21) + /* Zero out all fixed range and variable range MTRRs. */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + post_code(0x22) + /* Configure the default memory type to uncacheable. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + post_code(0x23) + /* Set Cache-as-RAM base address. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + post_code(0x24) + /* Set Cache-as-RAM mask. */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + post_code(0x25) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + invd + movl %eax, %cr0 + + /* enable the 'no eviction' mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $1, %eax + andl $~2, %eax + wrmsr + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + // movl $0x23322332, %eax + xorl %eax, %eax + rep stosl + + /* enable the 'no eviction run' state */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $3, %eax + wrmsr + + post_code(0x26) + /* Enable Cache-as-RAM mode by disabling cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRPROT, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $CPU_PHYSMASK_HI, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr + + post_code(0x27) +#if CONFIG_CACHE_MRC_BIN + /* Enable caching for ram init code to run faster */ + movl $MTRRphysBase_MSR(2), %ecx + movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(2), %ecx + movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr +#endif + + post_code(0x28) + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* Set up the stack pointer below MRC variable space. */ + movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \ + CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax + movl %eax, %esp + + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + +before_romstage: + post_code(0x29) + /* Call romstage.c main function. */ + call main + + post_code(0x2f) + + /* Copy global variable space (for USBDEBUG) to memory */ +#if CONFIG_USBDEBUG + cld + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi + movl $(CONFIG_RAMTOP - 24), %edi + movl $24, %ecx + rep movsb +#endif + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~MTRRdefTypeEn), %eax + wrmsr + + post_code(0x31) + + /* Disable the no eviction run state */ + movl $NoEvictMod_MSR, %ecx + rdmsr + andl $~2, %eax + wrmsr + + invd + + /* Disable the no eviction mode */ + rdmsr + andl $~1, %eax + wrmsr + +#if CONFIG_CACHE_MRC_BIN + /* Clear MTRR that was used to cache MRC */ + xorl %eax, %eax + xorl %edx, %edx + movl $MTRRphysBase_MSR(2), %ecx + wrmsr + movl $MTRRphysMask_MSR(2), %ecx + wrmsr +#endif + + post_code(0x33) + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x36) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + + /* Enable Write Back and Speculative Reads for the first MB + * and coreboot_ram. + */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx // 36bit address space + wrmsr + + /* Enable Caching and speculative Reads for the + * complete ROM now that we actually have RAM. + */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again. */ + invd + + post_code(0x3c) + +#if CONFIG_HAVE_ACPI_RESUME + movl CBMEM_BOOT_MODE, %eax + cmpl $0x2, %eax // Resume? + jne __acpi_resume_backup_done + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high + * tables memory completely, but that's a wonderful clean up task for + * another day. + */ + cld + movl $CONFIG_RAMBASE, %esi + movl CBMEM_RESUME_BACKUP, %edi + movl $HIGH_MEMORY_SAVE / 4, %ecx + rep movsl + +__acpi_resume_backup_done: +#endif + + post_code(0x3d) + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F + .word 0x210, 0x211, 0x212, 0x213 +mtrr_table_end: + diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h new file mode 100644 index 0000000..48e0c89 --- /dev/null +++ b/src/cpu/intel/model_206ax/chip.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_intel_model_206ax_ops; + +/* Magic value used to locate this chip in the device tree */ +#define SPEEDSTEP_APIC_MAGIC 0xACAC + +struct cpu_intel_model_206ax_config { + u8 disable_acpi; /* Do not generate CPU ACPI tables */ + + u8 pstate_coord_type; /* Processor Coordination Type */ + + int c1_battery; /* ACPI C1 on Battery Power */ + int c2_battery; /* ACPI C2 on Battery Power */ + int c3_battery; /* ACPI C3 on Battery Power */ + + int c1_acpower; /* ACPI C1 on AC Power */ + int c2_acpower; /* ACPI C2 on AC Power */ + int c3_acpower; /* ACPI C3 on AC Power */ +}; diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c new file mode 100644 index 0000000..9de94c4 --- /dev/null +++ b/src/cpu/intel/model_206ax/finalize.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include "model_206ax.h" + +static void msr_set_bit(unsigned reg, unsigned bit) +{ + msr_t msr = rdmsr(reg); + + if (bit < 32) { + if (msr.lo & (1 << bit)) + return; + msr.lo |= 1 << bit; + } else { + if (msr.hi & (1 << (bit - 32))) + return; + msr.hi |= 1 << (bit - 32); + } + + wrmsr(reg, msr); +} + +void intel_model_206ax_finalize_smm(void) +{ + msr_set_bit(IA32_FEATURE_CONTROL, 0); + msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); + + /* Lock AES-NI only if supported */ + if (cpuid_ecx(1) & (1 << 25)) + msr_set_bit(MSR_FEATURE_CONFIG, 0); + + msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); + msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); + msr_set_bit(MSR_PKG_POWER_LIMIT, 63); + msr_set_bit(MSR_PP0_POWER_LIMIT, 31); + msr_set_bit(MSR_PP1_POWER_LIMIT, 31); + msr_set_bit(MSR_MISC_PWR_MGMT, 22); + msr_set_bit(MSR_LT_LOCK_MEMORY, 0); +} diff --git a/src/cpu/intel/model_206ax/microcode-m12206a7_00000025.h b/src/cpu/intel/model_206ax/microcode-m12206a7_00000025.h new file mode 100644 index 0000000..229fba2 --- /dev/null +++ b/src/cpu/intel/model_206ax/microcode-m12206a7_00000025.h @@ -0,0 +1,611 @@ +//+++ +// Copyright (c) <1995-2011>, Intel Corporation. +// All rights reserved. +// +// Redistribution. Redistribution and use in binary form, without modification, are +// permitted provided that the following conditions are met: +// .Redistributions must reproduce the above copyright notice and the following +// disclaimer in the documentation and/or other materials provided with the +// distribution. +// .Neither the name of Intel Corporation nor the names of its suppliers may be used +// to endorse or promote products derived from this software without specific prior +// written permission. +// .No reverse engineering, decompilation, or disassembly of this software is +// permitted. +// ."Binary form" includes any format commonly used for electronic conveyance +// which is a reversible, bit-exact translation of binary representation to ASCII or +// ISO text, for example, "uuencode." +// +// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//--- +/* Thu Nov 10 10:30:59 CST 2011 */ +/* m12206a7_00000025.inc */ +0x00000001, 0x00000025, 0x10112011, 0x000206a7, +0x6aa14554, 0x00000001, 0x00000012, 0x000023d0, +0x00002400, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x000000a1, 0x00020001, 0x00000025, +0x00000000, 0x00000000, 0x20111011, 0x000008d1, +0x00000001, 0x000206a7, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00000000, 0x000008d1, 0x00000000, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x9d225b45, 0x6ab4c3b0, 0xebba1c32, 0x469a230a, +0x8a7d6315, 0x2fc24d3e, 0x82506f79, 0x18dbb9d6, +0x1a7bbeb1, 0x355a1d62, 0x2e7eb594, 0x09f8dea9, +0x432a49e4, 0xbf520253, 0xdafa4010, 0x893a858a, +0x766e0efb, 0xd91e196d, 0x838bd2ef, 0xe5146494, +0xd515f413, 0x29704828, 0xe85598b6, 0xdcbe6c51, +0x88eabbfa, 0xa1e8909f, 0xd8931721, 0x35386554, +0x089a78a7, 0xd9914775, 0xd4644748, 0x1556a4dc, +0xf44448f6, 0xd054d7db, 0xf30f2b7d, 0x5ae223d0, +0xcbbb48b0, 0x5c8b0383, 0x177de157, 0x9c1e5f73, +0x2ec28289, 0xd72a7b6c, 0x823b6eb2, 0x35e02171, +0xba8deae4, 0x06f4d468, 0x13dbafaa, 0x72b419f1, +0x033385b5, 0x05806920, 0x4c6034cf, 0x9bd117dc, +0x976e2d04, 0x250330f0, 0x7250b5e1, 0x184980c2, +0x12a9d7d6, 0x1bc808f9, 0xae79994f, 0xc6f87901, +0xc0e3132f, 0x671491c5, 0x236cad39, 0x37889d9c, +0x67f7c3f3, 0x964a6be5, 0xbcced7da, 0x57eeaa6e, +0x7bca1522, 0x654fee4c, 0x2a1ca5d9, 0xa1803cf3, +0x00000011, 0x3f96e33b, 0xbcc97e7d, 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0x9c09de46, 0xb022ec2b, +0xfa142272, 0xd1e1dcce, 0xc7c2f6c9, 0xd8e72fc1, diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h new file mode 100644 index 0000000..3343d11 --- /dev/null +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CPU_INTEL_MODEL_206AX_H +#define _CPU_INTEL_MODEL_206AX_H + +/* SandyBridge bus clock is fixed at 100MHz */ +#define SANDYBRIDGE_BCLK 100 + +#define IA32_FEATURE_CONTROL 0x3a +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +#define MSR_FEATURE_CONFIG 0x13c +#define IA32_PLATFORM_DCA_CAP 0x1f8 +#define IA32_MISC_ENABLE 0x1a0 +#define IA32_PERF_CTL 0x199 +#define IA32_THERM_INTERRUPT 0x19b +#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 +#define ENERGY_POLICY_PERFORMANCE 0 +#define ENERGY_POLICY_NORMAL 6 +#define ENERGY_POLICY_POWERSAVE 15 +#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 +#define MSR_LT_LOCK_MEMORY 0x2e7 +#define IA32_MC0_STATUS 0x401 + +#define MSR_PIC_MSG_CONTROL 0x2e +#define MSR_PLATFORM_INFO 0xce +#define PLATFORM_INFO_SET_TDP (1 << 29) +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 + +#define MSR_MISC_PWR_MGMT 0x1aa +#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_POWER_CTL 0x1fc + +#define MSR_PKGC3_IRTL 0x60a +#define MSR_PKGC6_IRTL 0x60b +#define MSR_PKGC7_IRTL 0x60c +#define IRTL_VALID (1 << 15) +#define IRTL_1_NS (0 << 10) +#define IRTL_32_NS (1 << 10) +#define IRTL_1024_NS (2 << 10) +#define IRTL_32768_NS (3 << 10) +#define IRTL_1048576_NS (4 << 10) +#define IRTL_33554432_NS (5 << 10) +#define IRTL_RESPONSE_MASK (0x3ff) + +/* long duration in low dword, short duration in high dword */ +#define MSR_PKG_POWER_LIMIT 0x610 +#define PKG_POWER_LIMIT_MASK 0x7fff +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK 0x7f + +#define MSR_PP0_CURRENT_CONFIG 0x601 +#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ +#define MSR_PP1_CURRENT_CONFIG 0x602 +#define PP1_CURRENT_LIMIT (35 << 3) /* 35 A */ +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_SKU 0x614 +#define MSR_PP0_POWER_LIMIT 0x638 +#define MSR_PP1_POWER_LIMIT 0x640 + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#ifdef __SMM__ +/* Lock MSRs */ +void intel_model_206ax_finalize_smm(void); +#else +/* Configure power limits for turbo mode */ +void set_power_limits(u8 power_limit_1_time); +#endif + +#endif diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c new file mode 100644 index 0000000..874ce4d --- /dev/null +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -0,0 +1,558 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <arch/acpi.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> +#include <cpu/intel/speedstep.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/name.h> +#include <pc80/mc146818rtc.h> +#include <usbdebug.h> +#include "model_206ax.h" + +/* + * List of suported C-states in this processor + * + * Latencies are typical worst-case package exit time in uS + * taken from the SandyBridge BIOS specification. + */ +static acpi_cstate_t cstate_map[] = { + { /* 0: C0 */ + },{ /* 1: C1 */ + .latency = 1, + .power = 1000, + .resource = { + .addrl = 0x00, /* MWAIT State 0 */ + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, + .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, + } + }, + { /* 2: C1E */ + .latency = 1, + .power = 1000, + .resource = { + .addrl = 0x01, /* MWAIT State 0 Sub-state 1 */ + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, + .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, + } + }, + { /* 3: C3 */ + .latency = 63, + .power = 500, + .resource = { + .addrl = 0x10, /* MWAIT State 1 */ + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, + .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, + } + }, + { /* 4: C6 */ + .latency = 87, + .power = 350, + .resource = { + .addrl = 0x20, /* MWAIT State 2 */ + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, + .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, + } + }, + { /* 5: C7 */ + .latency = 90, + .power = 200, + .resource = { + .addrl = 0x30, /* MWAIT State 3 */ + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, + .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, + } + }, + { /* 6: C7S */ + .latency = 90, + .power = 200, + .resource = { + .addrl = 0x31, /* MWAIT State 3 Sub-state 1 */ + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, + .resv = ACPI_FFIXEDHW_FLAG_HW_COORD, + } + }, + { 0 } +}; + +static const uint32_t microcode_updates[] = { + #include "x06_microcode.h" +}; + +static void enable_vmx(void) +{ + struct cpuid_result regs; + msr_t msr; + int enable = CONFIG_ENABLE_VMX; + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + printk(BIOS_ERR, "VMX is locked, so enable_vmx will do nothing\n"); + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + regs = cpuid(1); + printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + if (regs.ecx & CPUID_VMX) { + if (enable) + msr.lo |= (1 << 2); + else + msr.lo &= ~(1 << 2); + + if (regs.ecx & CPUID_SMX) { + if (enable) + msr.lo |= (1 << 1); + else + msr.lo &= ~(1 << 1); + } + } + + wrmsr(IA32_FEATURE_CONTROL, msr); +} + +/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ +static const u8 power_limit_time_sec_to_msr[] = { + [0] = 0x00, + [1] = 0x0a, + [2] = 0x0b, + [3] = 0x4b, + [4] = 0x0c, + [5] = 0x2c, + [6] = 0x4c, + [7] = 0x6c, + [8] = 0x0d, + [10] = 0x2d, + [12] = 0x4d, + [14] = 0x6d, + [16] = 0x0e, + [20] = 0x2e, + [24] = 0x4e, + [28] = 0x6e, + [32] = 0x0f, + [40] = 0x2f, + [48] = 0x4f, + [56] = 0x6f, + [64] = 0x10, + [80] = 0x30, + [96] = 0x50, + [112] = 0x70, + [128] = 0x11, +}; + +/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ +static const u8 power_limit_time_msr_to_sec[] = { + [0x00] = 0, + [0x0a] = 1, + [0x0b] = 2, + [0x4b] = 3, + [0x0c] = 4, + [0x2c] = 5, + [0x4c] = 6, + [0x6c] = 7, + [0x0d] = 8, + [0x2d] = 10, + [0x4d] = 12, + [0x6d] = 14, + [0x0e] = 16, + [0x2e] = 20, + [0x4e] = 24, + [0x6e] = 28, + [0x0f] = 32, + [0x2f] = 40, + [0x4f] = 48, + [0x6f] = 56, + [0x10] = 64, + [0x30] = 80, + [0x50] = 96, + [0x70] = 112, + [0x11] = 128, +}; + +/* + * Configure processor power limits if possible + * This must be done AFTER set of BIOS_RESET_CPL + */ +void set_power_limits(u8 power_limit_1_time) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + msr_t limit; + unsigned power_unit; + unsigned tdp, min_power, max_power, max_time; + u8 power_limit_1_val; + + if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) + return; + + if (!(msr.lo & PLATFORM_INFO_SET_TDP)) + return; + + /* Get units */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + + /* Get power defaults for this SKU */ + msr = rdmsr(MSR_PKG_POWER_SKU); + tdp = msr.lo & 0x7fff; + min_power = (msr.lo >> 16) & 0x7fff; + max_power = msr.hi & 0x7fff; + max_time = (msr.hi >> 16) & 0x7f; + + printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); + + if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) + power_limit_1_time = power_limit_time_msr_to_sec[max_time]; + + if (min_power > 0 && tdp < min_power) + tdp = min_power; + + if (max_power > 0 && tdp > max_power) + tdp = max_power; + + power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; + + /* Set long term power limit to TDP */ + limit.lo = 0; + limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + limit.lo |= PKG_POWER_LIMIT_EN; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << + PKG_POWER_LIMIT_TIME_SHIFT; + + /* Set short term power limit to 1.25 * TDP */ + limit.hi = 0; + limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + /* Power limit 2 time is only programmable on SNB EP/EX */ + + wrmsr(MSR_PKG_POWER_LIMIT, limit); +} + +static void configure_c_states(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr.lo |= (1 << 28); // C1 Auto Undemotion Enable + msr.lo |= (1 << 27); // C3 Auto Undemotion Enable + msr.lo |= (1 << 26); // C1 Auto Demotion Enable + msr.lo |= (1 << 25); // C3 Auto Demotion Enable + msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection + msr.lo |= 7; // No package C-state limit + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + + msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); + msr.lo &= ~0x7ffff; + msr.lo |= (PMB0_BASE + 4); // LVL_2 base address + msr.lo |= (2 << 16); // CST Range: C7 is max C-state + wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); + + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination + wrmsr(MSR_MISC_PWR_MGMT, msr); + + msr = rdmsr(MSR_POWER_CTL); + msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 + msr.lo |= (1 << 1); // C1E Enable + msr.lo |= (1 << 0); // Bi-directional PROCHOT# + wrmsr(MSR_POWER_CTL, msr); + + /* C3 Interrupt Response Time Limit */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50; + wrmsr(MSR_PKGC3_IRTL, msr); + + /* C6 Interrupt Response Time Limit */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68; + wrmsr(MSR_PKGC6_IRTL, msr); + + /* C7 Interrupt Response Time Limit */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D; + wrmsr(MSR_PKGC7_IRTL, msr); + + /* Primary Plane Current Limit */ + msr = rdmsr(MSR_PP0_CURRENT_CONFIG); + msr.lo &= ~0x1fff; + msr.lo |= PP0_CURRENT_LIMIT; + wrmsr(MSR_PP0_CURRENT_CONFIG, msr); + + /* Secondary Plane Current Limit */ + msr = rdmsr(MSR_PP1_CURRENT_CONFIG); + msr.lo &= ~0x1fff; + msr.lo |= PP1_CURRENT_LIMIT; + wrmsr(MSR_PP1_CURRENT_CONFIG, msr); +} + +static void configure_misc(void) +{ + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + wrmsr(IA32_MISC_ENABLE, msr); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + + /* Enable package critical interrupt only */ + msr.lo = 1 << 4; + msr.hi = 0; + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); +} + +static void enable_lapic_tpr(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PIC_MSG_CONTROL); + msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + wrmsr(MSR_PIC_MSG_CONTROL, msr); +} + +static void configure_dca_cap(void) +{ + struct cpuid_result cpuid_regs; + msr_t msr; + + /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ + cpuid_regs = cpuid(1); + if (cpuid_regs.ecx & (1 << 18)) { + msr = rdmsr(IA32_PLATFORM_DCA_CAP); + msr.lo |= 1; + wrmsr(IA32_PLATFORM_DCA_CAP, msr); + } +} + +static void set_max_ratio(void) +{ + msr_t msr; + + /* Platform Info bits 15:8 give max ratio */ + msr = rdmsr(MSR_PLATFORM_INFO); + msr.hi = 0; + msr.lo &= 0xff00; + wrmsr(IA32_PERF_CTL, msr); + + printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", + ((msr.lo >> 8) & 0xff) * 100); +} + +static void set_energy_perf_bias(u8 policy) +{ + msr_t msr; + + /* Energy Policy is bits 3:0 */ + msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr.lo &= ~0xf; + msr.lo |= policy & 0xf; + wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + + printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", + policy); +} + +static void configure_mca(void) +{ + msr_t msr; + int i; + + msr.lo = msr.hi = 0; + /* This should only be done on a cold boot */ + for (i = 0; i < 7; i++) + wrmsr(IA32_MC0_STATUS + (i * 4), msr); +} + +#if CONFIG_USBDEBUG +static unsigned ehci_debug_addr; +#endif + +/* + * Initialize any extra cores/threads in this package. + */ +static void intel_cores_init(device_t cpu) +{ + struct cpuid_result result; + unsigned cores, threads, i; + + result = cpuid_ext(0xb, 0); /* Threads per core */ + threads = result.ebx & 0xff; + + result = cpuid_ext(0xb, 1); /* Cores per package */ + cores = result.ebx & 0xff; + + /* Only initialize extra cores from BSP */ + if (cpu->path.apic.apic_id) + return; + + printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n", + cpu->path.apic.apic_id, cores, threads); + + for (i = 1; i < cores; ++i) { + struct device_path cpu_path; + device_t new; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = + cpu->path.apic.apic_id + i; + + /* Update APIC ID if no hyperthreading */ + if (threads == 1) + cpu_path.apic.apic_id <<= 1; + + /* Allocate the new cpu device structure */ + new = alloc_dev(cpu->bus, &cpu_path); + if (!new) + continue; + + printk(BIOS_DEBUG, "CPU: %u has core %u\n", + cpu->path.apic.apic_id, + new->path.apic.apic_id); + + /* Start the new cpu */ + if (!start_cpu(new)) { + /* Record the error in cpu? */ + printk(BIOS_ERR, "CPU %u would not start!\n", + new->path.apic.apic_id); + } + } +} + +static void model_206ax_init(device_t cpu) +{ + char processor_name[49]; + struct cpuid_result cpuid_regs; + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + + /* Update the microcode */ + intel_update_microcode(microcode_updates); + + /* Clear out pending MCEs */ + configure_mca(); + + /* Print processor name */ + fill_processor_name(processor_name); + printk(BIOS_INFO, "CPU: %s.\n", processor_name); + +#if CONFIG_USBDEBUG + // Is this caution really needed? + if(!ehci_debug_addr) + ehci_debug_addr = get_ehci_debug(); + set_ehci_debug(0); +#endif + + /* Setup MTRRs based on physical address size */ + cpuid_regs = cpuid(0x80000008); + x86_setup_fixed_mtrrs(); + x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2); + x86_mtrr_check(); + + /* Setup Page Attribute Tables (PAT) */ + // TODO set up PAT + +#if CONFIG_USBDEBUG + set_ehci_debug(ehci_debug_addr); +#endif + + /* Enable the local cpu apics */ + enable_lapic_tpr(); + setup_lapic(); + + /* Enable virtualization if enabled in CMOS */ + enable_vmx(); + + /* Configure C States */ + configure_c_states(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* Enable Direct Cache Access */ + configure_dca_cap(); + + /* Set energy policy */ + set_energy_perf_bias(ENERGY_POLICY_NORMAL); + + /* Set Max Ratio */ + set_max_ratio(); + + /* Enable Turbo */ + enable_turbo(); + + /* Start up extra cores */ + intel_cores_init(cpu); +} + +static struct device_operations cpu_dev_ops = { + .init = model_206ax_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */ + { X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */ + { X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */ + { X86_VENDOR_INTEL, 0x306a2 }, /* Intel IvyBridge */ + { X86_VENDOR_INTEL, 0x306a4 }, /* Intel IvyBridge */ + { X86_VENDOR_INTEL, 0x306a5 }, /* Intel IvyBridge */ + { X86_VENDOR_INTEL, 0x306a6 }, /* Intel IvyBridge */ + { X86_VENDOR_INTEL, 0x306a8 }, /* Intel IvyBridge */ + { X86_VENDOR_INTEL, 0x306a9 }, /* Intel IvyBridge */ + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, + .cstates = cstate_map, +}; + diff --git a/src/cpu/intel/model_206ax/x06_microcode.h b/src/cpu/intel/model_206ax/x06_microcode.h new file mode 100644 index 0000000..d055b2e --- /dev/null +++ b/src/cpu/intel/model_206ax/x06_microcode.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE + #include "microcode-m12206a7_00000025.h" +#elif CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE +#else +#error "Which microcode to use?" +#endif + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, diff --git a/src/cpu/intel/socket_rPGA989/Kconfig b/src/cpu/intel/socket_rPGA989/Kconfig new file mode 100644 index 0000000..11ac25f --- /dev/null +++ b/src/cpu/intel/socket_rPGA989/Kconfig @@ -0,0 +1,16 @@ +config CPU_INTEL_SOCKET_RPGA989 + bool + +if CPU_INTEL_SOCKET_RPGA989 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select MMX + select SSE + select CACHE_AS_RAM + +config CACHE_MRC_BIN + bool + default n + +endif diff --git a/src/cpu/intel/socket_rPGA989/Makefile.inc b/src/cpu/intel/socket_rPGA989/Makefile.inc new file mode 100644 index 0000000..b5d679a --- /dev/null +++ b/src/cpu/intel/socket_rPGA989/Makefile.inc @@ -0,0 +1,8 @@ +ramstage-y += socket_rPGA989.c +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../turbo diff --git a/src/cpu/intel/socket_rPGA989/chip.h b/src/cpu/intel/socket_rPGA989/chip.h new file mode 100644 index 0000000..f843e74 --- /dev/null +++ b/src/cpu/intel/socket_rPGA989/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_intel_socket_rPGA989_ops; + +struct cpu_intel_socket_rPGA989_config { +}; diff --git a/src/cpu/intel/socket_rPGA989/socket_rPGA989.c b/src/cpu/intel/socket_rPGA989/socket_rPGA989.c new file mode 100644 index 0000000..2484571 --- /dev/null +++ b/src/cpu/intel/socket_rPGA989/socket_rPGA989.c @@ -0,0 +1,6 @@ +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_intel_socket_rPGA989_ops = { + CHIP_NAME("Socket rPGA989 CPU") +};