On 08.08.2008 17:18, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
On 06.08.2008 18:54, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
- "Errata 193: Disable clean copybacks to L3 cache to allow cached
ROM." Erratum 193 seems to be unlisted in public data sheets. If it is the famous L3 problem, we might want to enable the workaround only on affected revisions.
This is an errata for early silicon which is why it isn't in the public rev guide. It is a fix for caching instructions while in CAR mode. It can be removed. All Ax support could be removed.
Does that removal suggestion really mean all Ax support including the newly committed Ax microcode updates and the (older) Ax memory controller stuff?
Yes, It is there for completeness. I don't think it needs to be carried forward to v3.
Thanks for the info.
Remove Family 10h revision Ax support from v3 CAR code.
Signed-off-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2006@gmx.net
Index: corebootv3-CAR_no_10h_rev_Ax/arch/x86/amd/stage0.S =================================================================== --- corebootv3-CAR_no_10h_rev_Ax/arch/x86/amd/stage0.S (Revision 724) +++ corebootv3-CAR_no_10h_rev_Ax/arch/x86/amd/stage0.S (Arbeitskopie) @@ -212,15 +212,6 @@
#endif
-#ifdef CONFIG_CPU_AMD_K10 - /* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM. - Re-enable it in after RAM is initialized and before CAR is disabled */ - movl $0xc001102a, %ecx - rdmsr - bts $15, %eax - wrmsr -#endif - /* Set MtrrFixDramModEn for clear fixed mtrr */ enable_fixed_mtrr_dram_modify: movl $SYSCFG_MSR, %ecx