Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2617
-gerrit
commit 50eba130d507a3c875f0618b925a800bb1e65e7f Author: Aaron Durbin adurbin@chromium.org Date: Wed Oct 31 22:57:16 2012 -0500
haswell: always use MMIO PCI config accesses
Add a bootblock.c file for the northbridge and setup the PCIEXBAR as the first thing using IO PCI config acceses. After that all PCI config accesses can use MMIO.
Change-Id: I51d229c626c45705dda1757c2f14265cbc0e6183 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/northbridge/intel/haswell/Kconfig | 5 +++++ src/northbridge/intel/haswell/bootblock.c | 27 +++++++++++++++++++++++++++ src/northbridge/intel/haswell/early_init.c | 3 --- 3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 7e27cfd..a7f1f9b 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -22,9 +22,14 @@ config NORTHBRIDGE_INTEL_HASWELL select CACHE_MRC_BIN select CPU_INTEL_HASWELL select REQUIRES_BLOB + select MMCONF_SUPPORT_DEFAULT
if NORTHBRIDGE_INTEL_HASWELL
+config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/haswell/bootblock.c" + config VGA_BIOS_ID string default "8086,0166" diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c new file mode 100644 index 0000000..35f357f --- /dev/null +++ b/src/northbridge/intel/haswell/bootblock.c @@ -0,0 +1,27 @@ +#include <arch/io.h> +#include <arch/romcc_io.h> + +/* Just re-define this instead of including haswell.h. It blows up romcc. */ +#define PCIEXBAR 0x60 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = 0; + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); +} diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index b524f2e..4d17474 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -26,7 +26,6 @@ #include <device/pci_def.h> #include <elog.h> #include "haswell.h" -#include "pcie_config.c"
static void haswell_setup_bars(void) { @@ -50,8 +49,6 @@ static void haswell_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);