* yuen@klacno.sk yuen@klacno.sk [110401 20:59]:
Hi, I'm working on port coreboot to Asus Eee Box B202 (http://www.asus.com/product.aspx?P_ID=QUObl5lSRQQ3lSqJ). Code is based on Intel d945gclf target.
So far I have console running. Boot halts on sdram initialization before "Extended Mode Register Set(2)", sometime goes one or two steps ahead.
Any idea how to move on?
Dump the MCHBAR registers before jedec init and compare them against an inteltool dump running with the original vendor bios.
Cheers Marek Becka
coreboot-4.0-r6469M Fri Apr 1 18:17:34 CEST 2011 starting...
Mobile Intel(R) 82945GMS/GU Express Chipset (G)MCH capable of up to FSB 667 MHz (G)MCH capable of up to DDR2-533
Setting up static southbridge registers... GPIOS... done. Disabling Watchdog reboot... done. Setting up static northbridge registers... done. Waiting for MCHBAR to come up...ok SMBus controller enabled. Setting up RAM controller. This mainboard supports only Single Channel Operation. DDR II Channel 0 Socket 0: x16DS lowest common cas = 3 Probing Speed 1 DIMM: 0 Current CAS mask: 0038; idx=2, tCLK=50, tAC=60: Not fast enough! Current CAS mask: 0030; idx=1, tCLK=3d, tAC=50: OK DIMM: 1 DIMM: 2 DIMM: 3 freq_cas_mask for speed 1: 0030 Memory will be driven at 533MHz with CAS=4 clocks tRAS = 12 cycles tRP = 4 cycles tRCD = 4 cycles Refresh: 7.8us tWR = 4 cycles DIMM 0 side 0 = 512 MB DIMM 0 side 1 = 512 MB tRFC = 34 cycles Setting Graphics Frequency... FSB: 533 MHz Voltage: 1.05V Render: 166Mhz Display: 200MHz
Hm.. FSB supports up to 667
Setting Memory Frequency... CLKCFG=0x00010021, CLKCFG=0x00010031, ok Setting mode of operation for memory channels...Single Channel 0 only. DCC=0x00000400 Programming Clock Crossing...MEM=667 FSB=533... ok
This looks suspicious. It MEM=667 is not supported.
Setting RAM size... C0DRB = 0x20202010 C1DRB = 0x00000000 TOLUD = 0x0040 Setting row attributes... C0DRA = 0x0033 C1DRA = 0x0000 DIMM0 has 8 banks. one dimm per channel config.. Initializing System Memory IO... Programming Single Channel RCOMP Table Index: 4 Programming DLL Timings... Enabling System Memory IO... jedec enable sequence: bank 0 Apply NOP Sending RAM command 0x00010400...done ram read: 00000000 All Banks Precharge Sending RAM command 0x00020400...done ram read: 00000000