On Wed, May 7, 2008 at 11:45 PM, Viswesh S viswesh_vichu@yahoo.com wrote:
Hi,
I understand that before the node ids are being assigned, each AP node is considered as Node7. We will just go through the sequence of code in setup_smp2() in coherent_ht.c.
From the link type register 0x98, in Node0, it is seen that link1 is coherent and connected.
setup_row_local(0, 0); /* it will update the broadcast RT*/ // value is 0x50101 in F0 register 0x40
val = get_row(0,0); byte = (val>>16) & 0xfe; // byte = 0xf4 if(byte<0x2) { /* no coherent connection so get out.*/ nodes = 1; return nodes; } /* Setup and check a temporary connection to node 1 */ #if TRY_HIGH_FIRST == 1 byte = get_linkn_last(byte); /* Max Link to node1 */ #else // TRY_HIGH_FIRST = 0 here byte = get_linkn_first(byte); /*Min Link to node1 --- according to AMD*/ #endif // byte = 1
print_linkn("(0,1) link=", byte); setup_row_direct(0,1, byte); // ( We are modifying the routing register 0x44, which is for the connection between Node0 and Node1. So here itself we consider Node1 itself and node7, though we copy the value from register 0x44 to 0x5c in the next function.
setup_temp_row(0, 1); // As mentioned, we copy the value from 0x44 to 0x5c, ie setting up of routing register for connection between node0 and node7 --> which is actually AP
verify_connection(7); // Here is where I get confused.See verify the connection tries to read the 0x0 register from Node7, which doesnt exist at all.ie in our case node0 has device address 0x18 and hence node7 will have 0x18+7 = 0x1f and such a device doesnt exist at all if you do lspci.
00:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12) 00:01.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC (rev 01) 00:02.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12) 00:02.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC (rev 01) 00:06.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8111 PCI (rev 07) 00:07.0 ISA bridge: Advanced Micro Devices [AMD] AMD-8111 LPC (rev 05) 00:07.1 IDE interface: Advanced Micro Devices [AMD] AMD-8111 IDE (rev 03) 00:07.3 Bridge: Advanced Micro Devices [AMD] AMD-8111 ACPI (rev 05) 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:19.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:19.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:00.0 USB Controller: Advanced Micro Devices [AMD] AMD-8111 USB (rev 0b) 01:00.1 USB Controller: Advanced Micro Devices [AMD] AMD-8111 USB (rev 0b) 01:06.0 VGA compatible controller: ATI Technologies Inc Rage XL (rev 27)
So then what value do we read..The same question arises for the next function also - /* We found 2 nodes so far */ val = pci_read_config32(NODE_HT(7), 0x6c); // Here also the same issues arises byte = (val>>2) & 0x3; /*get default link on node7 to node0*/ print_linkn("(1,0) link=", byte); setup_row_local(7,1); setup_remote_row_direct(1, 0, byte);
before enable_routing(), that node is still node 7.
after enable_routing, the node will start to use routing table in it, and core0 in that node will start to fetch code from reset vector and start to run...
YH