Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2688
-gerrit
commit 620e2cead22e5c48b54f052d5a8a6a953529a64c Author: Aaron Durbin adurbin@chromium.org Date: Wed Dec 19 17:15:43 2012 -0600
haswell: reserve default SMRAM space
Currently the OS is free to use the memory located at the default SMRAM space because it is not marked reserved in the e820. This can lead to memory corruption on S3 resume because SMM setup doesn't save this range before using it to relocate SMRAM.
Resulting tables:
coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000002ffff: RAM 2. 0000000000030000-000000000003ffff: RESERVED 3. 0000000000040000-000000000009ffff: RAM 4. 00000000000a0000-00000000000fffff: RESERVED 5. 0000000000100000-0000000000efffff: RAM 6. 0000000000f00000-0000000000ffffff: RESERVED 7. 0000000001000000-00000000acebffff: RAM 8. 00000000acec0000-00000000acffffff: CONFIGURATION TABLES 9. 00000000ad000000-00000000af9fffff: RESERVED 10. 00000000f0000000-00000000f3ffffff: RESERVED 11. 00000000fed10000-00000000fed19fff: RESERVED 12. 00000000fed84000-00000000fed84fff: RESERVED 13. 0000000100000000-000000018f5fffff: RAM
e820 map has 13 items: 0: 0000000000000000 - 0000000000030000 = 1 RAM 1: 0000000000030000 - 0000000000040000 = 2 RESERVED 2: 0000000000040000 - 000000000009f400 = 1 RAM 3: 000000000009f400 - 00000000000a0000 = 2 RESERVED 4: 00000000000f0000 - 0000000000100000 = 2 RESERVED 5: 0000000000100000 - 0000000000f00000 = 1 RAM 6: 0000000000f00000 - 0000000001000000 = 2 RESERVED 7: 0000000001000000 - 00000000acec0000 = 1 RAM 8: 00000000acec0000 - 00000000afa00000 = 2 RESERVED 9: 00000000f0000000 - 00000000f4000000 = 2 RESERVED 10: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED 11: 00000000fed84000 - 00000000fed85000 = 2 RESERVED 12: 0000000100000000 - 000000018f600000 = 1 RAM
Booted and checked e820 as well as coreboot table information.
Change-Id: Ie4985c748b591bf8c0d6a2b59549b698c9ad6cfe Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/include/cpu/x86/smm.h | 3 +++ src/northbridge/intel/haswell/northbridge.c | 40 ++++++++++++++++++++++++----- 2 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 302873f..b6a6c4e 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -24,6 +24,9 @@ #ifndef CPU_X86_SMM_H #define CPU_X86_SMM_H
+#define SMM_DEFAULT_BASE 0x30000 +#define SMM_DEFAULT_SIZE 0x10000 + /* used only by C programs so far */ #define SMM_BASE 0xa0000
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e97ef55..7059e2c 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -32,6 +32,7 @@ #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> +#include <cpu/x86/smm.h> #include <boot/tables.h> #include <cbmem.h> #include "chip.h" @@ -333,29 +334,54 @@ static void mc_add_dram_resources(device_t dev) mc_report_map_entries(dev, &mc_values[0]);
/* - * There are 4 host memory ranges that should be added: - * - 0 -> 0xa0000 : cacheable + * These are the host memory ranges that should be added: + * - 0 -> SMM_DEFAULT_BASE : cacheable + * - SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE : + * cacheable and reserved + * - SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 : cacheable * - 0xc0000 -> TSEG : cacheable * - TESG -> TOLUD: not cacheable with standard MTRRs and reserved * - 4GiB -> TOUUD: cacheable * + * The default SMRAM space is reserved so that the range doesn't + * have to be saved during S3 Resume. Once marked reserved the OS + * cannot use the memory. This is a bit of an odd place to reserve + * the region, but the CPU devices don't have dev_ops->read_resources() + * called on them. + * * The range 0xa0000 -> 0xc0000 does not have any resources * associated with it to handle legacy VGA memory. If this range * is not omitted the mtrr code will setup the area as cacheable * causing VGA access to not work. * + * It should be noted that cacheable entry types need to be added in + * order. The reason is that the current MTRR code assumes this and + * falls over itself if it isn't. + * * The resource index starts low and should not meet or exceed - * PCI_BASE_ADDRESS_0. In this case there are only 3 entries so there - * are no conflicts in the index space. + * PCI_BASE_ADDRESS_0. */ index = 0;
- /* 0 - > 0xa0000 */ + /* 0 - > SMM_DEFAULT_BASE */ base_k = 0; - size_k = 0xa0000 >> 10; + size_k = SMM_DEFAULT_BASE >> 10; + ram_resource(dev, index++, base_k, size_k); + + /* SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE */ + resource = new_resource(dev, index++); + resource->base = SMM_DEFAULT_BASE; + resource->size = SMM_DEFAULT_SIZE; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_CACHEABLE | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + + /* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 */ + base_k = (SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE) >> 10; + size_k = (0xa0000 >> 10) - base_k; ram_resource(dev, index++, base_k, size_k);
- /* 0xa0000 -> TSEG */ + /* 0xc0000 -> TSEG */ base_k = 0xc0000 >> 10; size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; ram_resource(dev, index++, base_k, size_k);