On Wed, Aug 10, 2016 at 3:34 AM Zoran Stojsavljevic < zoran.stojsavljevic@gmail.com> wrote:
Basically, in the classic car we got in 2005, the steps on x86 are: enable cache
*> do references to set tags*
disable cache (really!) then cache as ram works.
I am interested how this is implemented, in *RED* (if you can point to some Coreboot implementation)?
It varies with CPU. In most cases, it involves enabling the cache, sometimes messing around with an MSR, then reading/writing memory which is not functional, but the write sets the tags, so later when you set CD you can use cache and it won't try to load lines/writeback lines. Some chipsets need to be told not to wedge or reset or go crazy when that happens, but it works one way or another.
It's all very weird and not nearly as clean as the power pc. Power PC is where we first used CAR for linuxbios, ca. 2001. It took us another 4 years to learn how to do it on x86, and the vendors keep changing it on us :-)
I like the ARM SRAM approach. I asked the RISCV vendors to do the same thing. As can be seen with the various x86 CPUs, CAR just gets messy over time.
oh, and, that paper? https://www.coreboot.org/images/6/6c/LBCar.pdf It's a great writeup. See page 21. Note how simple that code is. Compare it to the newer chipsets.
Note that CD really means "no fill". At the same I commented that the words "Cache Disable" were, to many, evocative of "disabling the cache". My bet is CD used to mean cache disable, and the alternative meaning came later when CAR was implemented.
ron