Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2683
-gerrit
commit 1427523f2c1e7f87c3ca7ae193254513ae3c2144 Author: Duncan Laurie dlaurie@chromium.org Date: Wed Dec 19 13:17:06 2012 -0800
lynxpoint: Move a bit of generic RCBA into early_pch
Rather than have to repeat this bit in every mainboard.
Also, remove the reset of the RTC power status from here. We had done this in TOT for current platforms but did not carry it back to emeraldlake2 where this branched from.
If we clear the status here then we don't get an event logged later which can be important for the devices that do not have a CMOS battery.
Change-Id: Ia7131e9d9e7cf86228a285df652a96bcabf05260 Signed-off-by: Duncan Laurie dlaurie@chromium.org --- src/mainboard/intel/baskingridge/romstage.c | 5 ----- src/southbridge/intel/lynxpoint/early_pch.c | 20 +++++++++++++------- 2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 9561456..d47fbf1 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -79,11 +79,6 @@ const struct rcba_config_instruction rcba_config[] = { /* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
- /* Enable IOAPIC (generic) */ - RCBA_SET_REG_16(OIC, 0x0100), - /* PCH BWG says to read back the IOAPIC enable register */ - RCBA_READ_REG_16(OIC), - RCBA_END_CONFIG, };
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 9757d8a..c87da27 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -31,6 +31,15 @@ #include "gpio.h" #endif
+const struct rcba_config_instruction pch_early_config[] = { + /* Enable IOAPIC */ + RCBA_SET_REG_16(OIC, 0x0100), + /* PCH BWG says to read back the IOAPIC enable register */ + RCBA_READ_REG_16(OIC), + + RCBA_END_CONFIG, +}; + static void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ @@ -48,17 +57,10 @@ static void pch_enable_bars(void)
static void pch_generic_setup(void) { - u8 reg8; - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); - - // reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); - reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); }
static int sleep_type_s3(void) @@ -158,6 +160,10 @@ int early_pch_init(const void *gpio_map, /* Enable SMBus for reading SPDs. */ enable_smbus();
+ /* Early PCH RCBA settings */ + pch_config_rcba(pch_early_config); + + /* Mainboard RCBA settings */ pch_config_rcba(rcba_config);
wake_from_s3 = sleep_type_s3();