Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/385
-gerrit
commit ebc5b921fba6e032f18350a9f62adbc1df2db1f2 Author: Florian Zumbiehl florz@florz.de Date: Tue Nov 1 20:19:35 2011 +0100
implement usb2 termination and dpll delay setting for vt8237r
Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769 Signed-off-by: Florian Zumbiehl florz@florz.de --- src/southbridge/via/vt8237r/chip.h | 13 +++++++++++++ src/southbridge/via/vt8237r/usb.c | 24 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index f05d3c0..2e24fac 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -56,6 +56,19 @@ struct southbridge_via_vt8237r_config { /* 1 = 80-pin cable, 0 = 40-pin cable */ u8 ide0_80pin_cable; u8 ide1_80pin_cable; + + u8 usb2_termination_set; + u8 usb2_termination_a; + u8 usb2_termination_b; + u8 usb2_termination_c; + u8 usb2_termination_d; + u8 usb2_termination_e; + u8 usb2_termination_f; + u8 usb2_termination_g; + u8 usb2_termination_h; + + u8 usb2_dpll_set; + u8 usb2_dpll_delay; };
#endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index 6e8d9e5..2bdcf9d 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -22,6 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "chip.h" #include "vt8237r.h"
#if CONFIG_EPIA_VT8237R_INIT @@ -94,6 +95,7 @@ static void vt8237_usb_i_read_resources(struct device *dev)
static void usb_ii_init(struct device *dev) { + struct southbridge_via_vt8237r_config *cfg; #if CONFIG_EPIA_VT8237R_INIT u8 reg8;
@@ -112,6 +114,28 @@ static void usb_ii_init(struct device *dev) pci_write_config16(dev, 0x06, 0x7A10); #endif
+ cfg = dev->chip_info; + + if (cfg) { + if (cfg->usb2_termination_set) { + /* High Speed Port Pad Termination Resistor Fine Tune */ + pci_write_config8(dev, 0x5a, cfg->usb2_termination_c | + (cfg->usb2_termination_d << 4)); + pci_write_config8(dev, 0x5b, cfg->usb2_termination_a | + (cfg->usb2_termination_b << 4)); + pci_write_config8(dev, 0x5d, cfg->usb2_termination_e | + (cfg->usb2_termination_f << 4)); + pci_write_config8(dev, 0x5e, cfg->usb2_termination_g | + (cfg->usb2_termination_h << 4)); + } + + if (cfg->usb2_dpll_set) { + /* Delay DPLL Input Data Control */ + pci_write_config8(dev, 0x5c, + (pci_read_config8(dev, 0x5c) & ~0x70) | + (cfg->usb2_dpll_delay << 4)); + } + } }
static void vt8237_usb_ii_read_resources(struct device *dev)