Hi,
Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan.
59 new defect(s) introduced to coreboot found with Coverity Scan. 3 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan Showing 20 of 59 defect(s)
** CID 1370600: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 184 in ivybridge_dump_timings()
________________________________________________________________________________________________________ *** CID 1370600: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 184 in ivybridge_dump_timings() 178 if (tWTR[0] != tWTR[1] && two_channels) 179 printf("/* tWTR mismatch: %d, %d */\n", tWTR[0], tWTR[1]); 180 print_time("tWTR", tWTR[0], tCK); 181 if (tCKE[0] != tCKE[1] && two_channels) 182 printf("/* tCKE mismatch: %d, %d */\n", tCKE[0], tCKE[1]); 183 print_time("tCKE", tCKE[0], tCK);
CID 1370600: Uninitialized variables (UNINIT) Using uninitialized value "tRTP[0]".
184 if (tRTP[0] != tRTP[1] && two_channels) 185 printf("/* tRTP mismatch: %d, %d */\n", tRTP[0], tRTP[1]); 186 print_time("tRTP", tRTP[0], tCK); 187 if (tRRD[0] != tRRD[1] && two_channels) 188 printf("/* tRRD mismatch: %d, %d */\n", tRRD[0], tRRD[1]); 189 print_time("tRRD", tRRD[0], tCK);
** CID 1370599: (UNINIT) /src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c: 585 in MemTRdPosWithRxEnDlySeeds3() /src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c: 579 in MemTRdPosWithRxEnDlySeeds3() /src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c: 580 in MemTRdPosWithRxEnDlySeeds3() /src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c: 578 in MemTRdPosWithRxEnDlySeeds3()
________________________________________________________________________________________________________ *** CID 1370599: (UNINIT) /src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c: 585 in MemTRdPosWithRxEnDlySeeds3() 579 for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { 580 if (RxEnDlyTargetFound[ByteLane] == FALSE) { 581 // Check if the current BL has found its target 582 if (ByteLanePass[ByteLane] == TRUE && ByteLaneFail[ByteLane] == TRUE) { 583 RxEnDlyTargetFound[ByteLane] = TRUE; 584 NumBLWithTargetFound++;
CID 1370599: (UNINIT) Using uninitialized value "FinalRxEnCycle[ByteLane]".
585 RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane]; 586 } else { 587 RxEnDlyTargetFound[ByteLane] = FALSE; 588 } 589 } else { 590 // BL has already failed and passed, so increment both flags /src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mtthrcSeedTrain.c: 579 in MemTRdPosWithRxEnDlySeeds3() 573 for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { 574 if (RxEnDlyTargetFound[ByteLane] == FALSE) { 575 // Check if the current BL has found its target 576 if (ByteLanePass[ByteLane] == TRUE && ByteLaneFail[ByteLane] == TRUE) { 577 RxEnDlyTargetFound[ByteLane] = TRUE; 578 NumBLWithTargetFound++;
CID 1370599: (UNINIT) Using uninitialized value "FinalRxEnCycle[ByteLane]".
579 RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane]; 580 } else { 581 RxEnDlyTargetFound[ByteLane] = FALSE; 582 } 583 } else { 584 // BL has already failed and passed, so increment both flags /src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c: 580 in MemTRdPosWithRxEnDlySeeds3() 574 for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { 575 if (RxEnDlyTargetFound[ByteLane] == FALSE) { 576 // Check if the current BL has found its target 577 if (ByteLanePass[ByteLane] == TRUE && ByteLaneFail[ByteLane] == TRUE) { 578 RxEnDlyTargetFound[ByteLane] = TRUE; 579 NumBLWithTargetFound++;
CID 1370599: (UNINIT) Using uninitialized value "FinalRxEnCycle[ByteLane]".
580 RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane]; 581 } else { 582 RxEnDlyTargetFound[ByteLane] = FALSE; 583 } 584 } else { 585 // BL has already failed and passed, so increment both flags /src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c: 578 in MemTRdPosWithRxEnDlySeeds3() 572 for (ByteLane = 0; ByteLane < MaxByteLanes; ByteLane++) { 573 if (RxEnDlyTargetFound[ByteLane] == FALSE) { 574 // Check if the current BL has found its target 575 if (ByteLanePass[ByteLane] == TRUE && ByteLaneFail[ByteLane] == TRUE) { 576 RxEnDlyTargetFound[ByteLane] = TRUE; 577 NumBLWithTargetFound++;
CID 1370599: (UNINIT) Using uninitialized value "FinalRxEnCycle[ByteLane]".
578 RxEnDlyTargetValue[ByteLane] = FinalRxEnCycle[ByteLane]; 579 } else { 580 RxEnDlyTargetFound[ByteLane] = FALSE; 581 } 582 } else { 583 // BL has already failed and passed, so increment both flags
** CID 1370598: Code maintainability issues (UNUSED_VALUE) /src/soc/intel/sch/raminit.c: 162 in program_sch_dram_data()
________________________________________________________________________________________________________ *** CID 1370598: Code maintainability issues (UNUSED_VALUE) /src/soc/intel/sch/raminit.c: 162 in program_sch_dram_data() 156 */ 157 reg32 = 158 sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4); 159 reg32 &= ~(DCO_FIELDS); /* Clear all DTR fields we'll change. */ 160 161 if (sysinfo->fsb_frequency == 533)
CID 1370598: Code maintainability issues (UNUSED_VALUE) Assigning value from "reg32 | 1U" to "reg32" here, but that stored value is overwritten before it can be used.
162 reg32 |= 1; 163 else 164 reg32 &= ~(BIT(0)); 165 reg32 = 0x006911c; // FIXME ? 166 167 sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4,
** CID 1370597: Uninitialized variables (UNINIT) /src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/TABLE/mftds.c: 291 in SetTableValues()
________________________________________________________________________________________________________ *** CID 1370597: Uninitialized variables (UNINIT) /src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/TABLE/mftds.c: 291 in SetTableValues() 285 if (MTPtr.attr == MTAdd) { 286 Temp2Val[DqsOffset] += (UINT16)MTPtr.data.s.value; 287 } 288 NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_NBBL_ACCESS (i, j), (UINT16)Temp2Val[DqsOffset]); 289 if (SaveDqs) { 290 if (DqsSavePtr == NULL) {
CID 1370597: Uninitialized variables (UNINIT) Using uninitialized value "TempVal[DqsOffset]".
291 NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset]; 292 } else { 293 DqsSavePtr[DqsOffset] = (UINT8)Temp2Val[DqsOffset]; 294 } 295 } 296 }
** CID 1370596: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 215 in ivybridge_dump_timings()
________________________________________________________________________________________________________ *** CID 1370596: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 215 in ivybridge_dump_timings() 209 print_time("tXPDLL", tXPDLL[0], tCK); 210 211 if (tXP[0] != tXP[1] && two_channels) 212 printf("/* tXP mismatch: %d, %d */\n", tXP[0], tXP[1]); 213 print_time("tXP", tXP[0], tCK); 214
CID 1370596: Uninitialized variables (UNINIT) Using uninitialized value "tAONPD[0]".
215 if (tAONPD[0] != tAONPD[1] && two_channels) 216 printf("/* tAONPD mismatch: %d, %d */\n", tAONPD[0], tAONPD[1]); 217 print_time("tAONPD", tAONPD[0], tCK); 218 219 reg = read_mchbar32(0x4298); 220 if (reg != read_mchbar32(0x4698) && two_channels)
** CID 1370595: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 195 in ivybridge_dump_timings()
________________________________________________________________________________________________________ *** CID 1370595: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 195 in ivybridge_dump_timings() 189 print_time("tRRD", tRRD[0], tCK); 190 191 if (tRAS[0] != tRAS[1] && two_channels) 192 printf("/* tRAS mismatch: %d, %d */\n", tRAS[0], tRAS[1]); 193 print_time("tRAS", tRAS[0], tCK); 194
CID 1370595: Uninitialized variables (UNINIT) Using uninitialized value "tCWL[0]".
195 if (tCWL[0] != tCWL[1] && two_channels) 196 printf("/* tCWL mismatch: %d, %d */\n", tCWL[0], tCWL[1]); 197 print_time("tCWL", tCWL[0], tCK); 198 199 if (tRP[0] != tRP[1] && two_channels) 200 printf("/* tRP mismatch: %d, %d */\n", tRP[0], tRP[1]);
** CID 1370594: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 203 in ivybridge_dump_timings()
________________________________________________________________________________________________________ *** CID 1370594: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 203 in ivybridge_dump_timings() 197 print_time("tCWL", tCWL[0], tCK); 198 199 if (tRP[0] != tRP[1] && two_channels) 200 printf("/* tRP mismatch: %d, %d */\n", tRP[0], tRP[1]); 201 print_time("tRP", tRP[0], tCK); 202
CID 1370594: Uninitialized variables (UNINIT) Using uninitialized value "tRCD[0]".
203 if (tRCD[0] != tRCD[1] && two_channels) 204 printf("/* tRCD mismatch: %d, %d */\n", tRCD[0], tRCD[1]); 205 print_time("tRCD", tRCD[0], tCK); 206 207 if (tXPDLL[0] != tXPDLL[1] && two_channels) 208 printf("/* tXPDLL mismatch: %d, %d */\n", tXPDLL[0], tXPDLL[1]);
** CID 1370593: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 199 in ivybridge_dump_timings()
________________________________________________________________________________________________________ *** CID 1370593: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 199 in ivybridge_dump_timings() 193 print_time("tRAS", tRAS[0], tCK); 194 195 if (tCWL[0] != tCWL[1] && two_channels) 196 printf("/* tCWL mismatch: %d, %d */\n", tCWL[0], tCWL[1]); 197 print_time("tCWL", tCWL[0], tCK); 198
CID 1370593: Uninitialized variables (UNINIT) Using uninitialized value "tRP[0]".
199 if (tRP[0] != tRP[1] && two_channels) 200 printf("/* tRP mismatch: %d, %d */\n", tRP[0], tRP[1]); 201 print_time("tRP", tRP[0], tCK); 202 203 if (tRCD[0] != tRCD[1] && two_channels) 204 printf("/* tRCD mismatch: %d, %d */\n", tRCD[0], tRCD[1]);
** CID 1370592: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 207 in ivybridge_dump_timings()
________________________________________________________________________________________________________ *** CID 1370592: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 207 in ivybridge_dump_timings() 201 print_time("tRP", tRP[0], tCK); 202 203 if (tRCD[0] != tRCD[1] && two_channels) 204 printf("/* tRCD mismatch: %d, %d */\n", tRCD[0], tRCD[1]); 205 print_time("tRCD", tRCD[0], tCK); 206
CID 1370592: Uninitialized variables (UNINIT) Using uninitialized value "tXPDLL[0]".
207 if (tXPDLL[0] != tXPDLL[1] && two_channels) 208 printf("/* tXPDLL mismatch: %d, %d */\n", tXPDLL[0], tXPDLL[1]); 209 print_time("tXPDLL", tXPDLL[0], tCK); 210 211 if (tXP[0] != tXP[1] && two_channels) 212 printf("/* tXP mismatch: %d, %d */\n", tXP[0], tXP[1]);
** CID 1370591: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 187 in ivybridge_dump_timings()
________________________________________________________________________________________________________ *** CID 1370591: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 187 in ivybridge_dump_timings() 181 if (tCKE[0] != tCKE[1] && two_channels) 182 printf("/* tCKE mismatch: %d, %d */\n", tCKE[0], tCKE[1]); 183 print_time("tCKE", tCKE[0], tCK); 184 if (tRTP[0] != tRTP[1] && two_channels) 185 printf("/* tRTP mismatch: %d, %d */\n", tRTP[0], tRTP[1]); 186 print_time("tRTP", tRTP[0], tCK);
CID 1370591: Uninitialized variables (UNINIT) Using uninitialized value "tRRD[0]".
187 if (tRRD[0] != tRRD[1] && two_channels) 188 printf("/* tRRD mismatch: %d, %d */\n", tRRD[0], tRRD[1]); 189 print_time("tRRD", tRRD[0], tCK); 190 191 if (tRAS[0] != tRAS[1] && two_channels) 192 printf("/* tRAS mismatch: %d, %d */\n", tRAS[0], tRAS[1]);
** CID 1370590: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 211 in ivybridge_dump_timings()
________________________________________________________________________________________________________ *** CID 1370590: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 211 in ivybridge_dump_timings() 205 print_time("tRCD", tRCD[0], tCK); 206 207 if (tXPDLL[0] != tXPDLL[1] && two_channels) 208 printf("/* tXPDLL mismatch: %d, %d */\n", tXPDLL[0], tXPDLL[1]); 209 print_time("tXPDLL", tXPDLL[0], tCK); 210
CID 1370590: Uninitialized variables (UNINIT) Using uninitialized value "tXP[0]".
211 if (tXP[0] != tXP[1] && two_channels) 212 printf("/* tXP mismatch: %d, %d */\n", tXP[0], tXP[1]); 213 print_time("tXP", tXP[0], tCK); 214 215 if (tAONPD[0] != tAONPD[1] && two_channels) 216 printf("/* tAONPD mismatch: %d, %d */\n", tAONPD[0], tAONPD[1]);
** CID 1370589: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 191 in ivybridge_dump_timings()
________________________________________________________________________________________________________ *** CID 1370589: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 191 in ivybridge_dump_timings() 185 printf("/* tRTP mismatch: %d, %d */\n", tRTP[0], tRTP[1]); 186 print_time("tRTP", tRTP[0], tCK); 187 if (tRRD[0] != tRRD[1] && two_channels) 188 printf("/* tRRD mismatch: %d, %d */\n", tRRD[0], tRRD[1]); 189 print_time("tRRD", tRRD[0], tCK); 190
CID 1370589: Uninitialized variables (UNINIT) Using uninitialized value "tRAS[0]".
191 if (tRAS[0] != tRAS[1] && two_channels) 192 printf("/* tRAS mismatch: %d, %d */\n", tRAS[0], tRAS[1]); 193 print_time("tRAS", tRAS[0], tCK); 194 195 if (tCWL[0] != tCWL[1] && two_channels) 196 printf("/* tCWL mismatch: %d, %d */\n", tCWL[0], tCWL[1]);
** CID 1370588: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 178 in ivybridge_dump_timings()
________________________________________________________________________________________________________ *** CID 1370588: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 178 in ivybridge_dump_timings() 172 173 printf(".reg_4004_b30 = { %d, %d },\n", reg_4004_b30[0], 174 reg_4004_b30[1]); 175 if (tFAW[0] != tFAW[1] && two_channels) 176 printf("/* tFAW mismatch: %d, %d */\n", tFAW[0], tFAW[1]); 177 print_time("tFAW", tFAW[0], tCK);
CID 1370588: Uninitialized variables (UNINIT) Using uninitialized value "tWTR[0]".
178 if (tWTR[0] != tWTR[1] && two_channels) 179 printf("/* tWTR mismatch: %d, %d */\n", tWTR[0], tWTR[1]); 180 print_time("tWTR", tWTR[0], tCK); 181 if (tCKE[0] != tCKE[1] && two_channels) 182 printf("/* tCKE mismatch: %d, %d */\n", tCKE[0], tCKE[1]); 183 print_time("tCKE", tCKE[0], tCK);
** CID 1370587: Uninitialized variables (UNINIT) /src/northbridge/intel/x4x/raminit_ddr2.c: 1485 in rcven_ddr2()
________________________________________________________________________________________________________ *** CID 1370587: Uninitialized variables (UNINIT) /src/northbridge/intel/x4x/raminit_ddr2.c: 1485 in rcven_ddr2() 1479 /* TODO: Resume support using this */ 1480 FOR_EACH_CHANNEL(ch) { 1481 for (lane = 0; lane < 8; lane++) { 1482 MCHBAR8(0x400*ch + 0x560 + (lane*4)) = 1483 (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0xf) | pitap[ch][lane]; 1484 }
CID 1370587: Uninitialized variables (UNINIT) Using uninitialized value "coarsectrl[ch]".
1485 MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | 1486 (coarsectrl[ch] << 16); 1487 MCHBAR16(0x400*ch + 0x5fa) = coarsedelay[ch]; 1488 MCHBAR16(0x400*ch + 0x58c) = mediumphase[ch]; 1489 } 1490 printk(BIOS_DEBUG, "End rcven\n");
** CID 1370586: (UNINIT) /src/mainboard/asus/kfsn4-dre/romstage.c: 123 in ck804_control() /src/mainboard/asus/kfsn4-dre/romstage.c: 123 in ck804_control() /src/mainboard/asus/kfsn4-dre_k8/romstage.c: 129 in ck804_control() /src/mainboard/asus/kfsn4-dre_k8/romstage.c: 129 in ck804_control()
________________________________________________________________________________________________________ *** CID 1370586: (UNINIT) /src/mainboard/asus/kfsn4-dre/romstage.c: 123 in ck804_control() 117 static const unsigned int ctrl_conf_enable_msi_mapping[] = { 118 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ 119 }; 120 121 static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) 122 {
CID 1370586: (UNINIT) Declaring variable "io_base" without initializer.
123 unsigned busn[4], io_base[4]; 124 int i, ck804_num = 0; 125 126 for (i = 0; i < 4; i++) { 127 u32 id; 128 pci_devfn_t dev; /src/mainboard/asus/kfsn4-dre/romstage.c: 123 in ck804_control() 117 static const unsigned int ctrl_conf_enable_msi_mapping[] = { 118 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ 119 }; 120 121 static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) 122 {
CID 1370586: (UNINIT) Declaring variable "io_base" without initializer.
123 unsigned busn[4], io_base[4]; 124 int i, ck804_num = 0; 125 126 for (i = 0; i < 4; i++) { 127 u32 id; 128 pci_devfn_t dev; /src/mainboard/asus/kfsn4-dre_k8/romstage.c: 129 in ck804_control() 123 static const unsigned int ctrl_conf_enable_msi_mapping[] = { 124 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ 125 }; 126 127 static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) 128 {
CID 1370586: (UNINIT) Declaring variable "io_base" without initializer.
129 unsigned busn[4], io_base[4]; 130 int i, ck804_num = 0; 131 132 for (i = 0; i < 4; i++) { 133 u32 id; 134 pci_devfn_t dev; /src/mainboard/asus/kfsn4-dre_k8/romstage.c: 129 in ck804_control() 123 static const unsigned int ctrl_conf_enable_msi_mapping[] = { 124 RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */ 125 }; 126 127 static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id) 128 {
CID 1370586: (UNINIT) Declaring variable "io_base" without initializer.
129 unsigned busn[4], io_base[4]; 130 int i, ck804_num = 0; 131 132 for (i = 0; i < 4; i++) { 133 u32 id; 134 pci_devfn_t dev;
** CID 1370585: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 181 in ivybridge_dump_timings()
________________________________________________________________________________________________________ *** CID 1370585: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 181 in ivybridge_dump_timings() 175 if (tFAW[0] != tFAW[1] && two_channels) 176 printf("/* tFAW mismatch: %d, %d */\n", tFAW[0], tFAW[1]); 177 print_time("tFAW", tFAW[0], tCK); 178 if (tWTR[0] != tWTR[1] && two_channels) 179 printf("/* tWTR mismatch: %d, %d */\n", tWTR[0], tWTR[1]); 180 print_time("tWTR", tWTR[0], tCK);
CID 1370585: Uninitialized variables (UNINIT) Using uninitialized value "tCKE[0]".
181 if (tCKE[0] != tCKE[1] && two_channels) 182 printf("/* tCKE mismatch: %d, %d */\n", tCKE[0], tCKE[1]); 183 print_time("tCKE", tCKE[0], tCK); 184 if (tRTP[0] != tRTP[1] && two_channels) 185 printf("/* tRTP mismatch: %d, %d */\n", tRTP[0], tRTP[1]); 186 print_time("tRTP", tRTP[0], tCK);
** CID 1370584: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 175 in ivybridge_dump_timings()
________________________________________________________________________________________________________ *** CID 1370584: Uninitialized variables (UNINIT) /util/inteltool/ivy_memory.c: 175 in ivybridge_dump_timings() 169 printf(".mobile = %d,\n", (mr0[0] >> 12) & 1); 170 print_time("CAS", CAS, tCK); 171 print_time("tWR", tWR, tCK); 172 173 printf(".reg_4004_b30 = { %d, %d },\n", reg_4004_b30[0], 174 reg_4004_b30[1]);
CID 1370584: Uninitialized variables (UNINIT) Using uninitialized value "tFAW[0]".
175 if (tFAW[0] != tFAW[1] && two_channels) 176 printf("/* tFAW mismatch: %d, %d */\n", tFAW[0], tFAW[1]); 177 print_time("tFAW", tFAW[0], tCK); 178 if (tWTR[0] != tWTR[1] && two_channels) 179 printf("/* tWTR mismatch: %d, %d */\n", tWTR[0], tWTR[1]); 180 print_time("tWTR", tWTR[0], tCK);
** CID 1370583: Uninitialized variables (UNINIT) /src/southbridge/nvidia/ck804/early_setup_car.c: 350 in ck804_early_setup_x()
________________________________________________________________________________________________________ *** CID 1370583: Uninitialized variables (UNINIT) /src/southbridge/nvidia/ck804/early_setup_car.c: 350 in ck804_early_setup_x() 344 busn[ck804_num] = i * 0x40; 345 io_base[ck804_num] = i * 0x4000; 346 ck804_num++; 347 } 348 } 349
CID 1370583: Uninitialized variables (UNINIT) Using uninitialized value "busn[0]" when calling "do_printk".
350 printk(BIOS_DEBUG, "ck804_early_set_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); 351 ck804_early_set_port(ck804_num, busn, io_base); 352 printk(BIOS_DEBUG, "ck804_early_setup(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); 353 ck804_early_setup(ck804_num, busn, io_base); 354 printk(BIOS_DEBUG, "ck804_early_clear_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); 355 ck804_early_clear_port(ck804_num, busn, io_base);
** CID 1370582: Uninitialized variables (UNINIT) /src/cpu/x86/mtrr/mtrr.c: 346 in commit_fixed_mtrrs()
________________________________________________________________________________________________________ *** CID 1370582: Uninitialized variables (UNINIT) /src/cpu/x86/mtrr/mtrr.c: 346 in commit_fixed_mtrrs() 340 fixed_mtrr_types[type_index++] << 24; 341 msr_num++; 342 } 343 } 344 345 for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++)
CID 1370582: Uninitialized variables (UNINIT) Using uninitialized value "msr_index[i]" when calling "do_printk".
346 printk(BIOS_DEBUG, "MTRR: Fixed MSR 0x%lx 0x%08x%08x\n", 347 msr_index[i], fixed_msrs[i].hi, fixed_msrs[i].lo); 348 349 disable_cache(); 350 for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++) 351 wrmsr(msr_index[i], fixed_msrs[i]);
** CID 1370581: Uninitialized variables (UNINIT) /src/southbridge/nvidia/ck804/early_setup_car.c: 350 in ck804_early_setup_x()
________________________________________________________________________________________________________ *** CID 1370581: Uninitialized variables (UNINIT) /src/southbridge/nvidia/ck804/early_setup_car.c: 350 in ck804_early_setup_x() 344 busn[ck804_num] = i * 0x40; 345 io_base[ck804_num] = i * 0x4000; 346 ck804_num++; 347 } 348 } 349
CID 1370581: Uninitialized variables (UNINIT) Using uninitialized value "io_base[0]" when calling "do_printk".
350 printk(BIOS_DEBUG, "ck804_early_set_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); 351 ck804_early_set_port(ck804_num, busn, io_base); 352 printk(BIOS_DEBUG, "ck804_early_setup(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); 353 ck804_early_setup(ck804_num, busn, io_base); 354 printk(BIOS_DEBUG, "ck804_early_clear_port(%d, %d, %d)\n", ck804_num, busn[0], io_base[0]); 355 ck804_early_clear_port(ck804_num, busn, io_base);
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