Author: rminnich Date: 2008-11-12 23:23:46 +0100 (Wed, 12 Nov 2008) New Revision: 1007
Added: coreboot-v3/southbridge/intel/i82801gx/pcie1.dts Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts coreboot-v3/mainboard/kontron/986lcd-m/stage1.c coreboot-v3/northbridge/intel/i945/bus.dts coreboot-v3/northbridge/intel/i945/mc.dts coreboot-v3/northbridge/intel/i945/northbridge.dts Log: more cleanup, and an attempt at a mainboard dts for the kontron.
Signed-off-by: Ronald G. Minnich rminnich@gmail.com Acked-by: Ronald G. Minnich rminnich@gmail.com
Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-12 18:30:13 UTC (rev 1006) +++ coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-11-12 22:23:46 UTC (rev 1007) @@ -35,7 +35,7 @@ end device pci 02.1 on end # display controller
- chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx/i82801gx register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x1" @@ -138,53 +138,52 @@ */
/{ - device_operations="dbm690t"; - mainboard_vendor = "AMD"; - mainboard_name = "Serengeti"; + mainboard_vendor = "kontron"; + mainboard_name = "986lcd-m"; cpus { }; apic@0 { }; domain@0 { - /config/("northbridge/amd/k8/domain"); - pci@1,0{ - }; + /config/("northbridge/intel/i945/northbridge.dts"); /* guesses; we need a real lspci */ - pci0@18,0 { - /config/("northbridge/amd/k8/pci"); - /* make sure that the ht device is first, as it controls many other things. */ - pci0 { - /config/("southbridge/amd/rs690/ht.dts"); - }; - pci1{ - /config/("southbridge/amd/rs690/gfx.dts"); - }; - pci2{ - /config/("southbridge/amd/rs690/pcie.dts"); - }; - pci4{ - /config/("southbridge/amd/sb600/hda.dts"); - }; - pci5{ - /config/("southbridge/amd/sb600/usb.dts"); - }; - pci6{ - /config/("southbridge/amd/sb600/usb2.dts"); - }; + pci@0,0 { + /config/("northbridge/intel/i945/bus.dts"); + pci@1b,0 { + /config/("southbridge/intel/i82801gx/ac97audio.dts"); + }; + pci@1c,0 { + /config/("southbridge/intel/i82801gx/pcie1.dts"); + }; + pci@1c,1 { + /config/("southbridge/intel/i82801gx/pcie2.dts"); + }; + pci@1c,2{ + /config/("southbridge/intel/i82801gx/pcie3.dts"); + }; + pci@1d,0{ + /config/("southbridge/intel/i82801gx/usb1.dts"); + }; + pci@1d,1{ + /config/("southbridge/intel/i82801gx/usb2.dts"); + }; + pci@1d,2{ + /config/("southbridge/intel/i82801gx/usb3.dts"); + }; + pci@1d,3{ + /config/("southbridge/intel/i82801gx/usb4.dts"); + }; + pci@1d,7{ + /config/("southbridge/intel/i82801gx/usb_ehci.dts"); + }; + pci@1e,0{ + /config/("southbridge/intel/i82801gx/pci.dts"); + }; + pci@1f,0{/* which ich? */ + /config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts"); + }; }; - pci1@18,0 { - /config/("northbridge/amd/k8/pci"); - }; - pci2@18,0 { - /config/("northbridge/amd/k8/pci"); - /* just for illustrating link #2 */ - pci@2,0{ - }; - }; - pci@18,1 {}; - pci@18,2 {}; - pci@18,3 {}; ioport@2e { - /config/("superio/ite/it8712f/dts"); + /config/("superio/winbond/w83627thg/dts"); com1enable = "1"; }; };
Modified: coreboot-v3/mainboard/kontron/986lcd-m/stage1.c =================================================================== --- coreboot-v3/mainboard/kontron/986lcd-m/stage1.c 2008-11-12 18:30:13 UTC (rev 1006) +++ coreboot-v3/mainboard/kontron/986lcd-m/stage1.c 2008-11-12 22:23:46 UTC (rev 1007) @@ -287,7 +287,6 @@ reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } -#warning need to fix up hardware_stage1 and move parts to initram.c void hardware_stage1(void) { void early_superio_config_w83627thg(void);
Modified: coreboot-v3/northbridge/intel/i945/bus.dts =================================================================== --- coreboot-v3/northbridge/intel/i945/bus.dts 2008-11-12 18:30:13 UTC (rev 1006) +++ coreboot-v3/northbridge/intel/i945/bus.dts 2008-11-12 22:23:46 UTC (rev 1007) @@ -17,7 +17,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -\ { device_operations = "i945_bus_ops"; };
Modified: coreboot-v3/northbridge/intel/i945/mc.dts =================================================================== --- coreboot-v3/northbridge/intel/i945/mc.dts 2008-11-12 18:30:13 UTC (rev 1006) +++ coreboot-v3/northbridge/intel/i945/mc.dts 2008-11-12 22:23:46 UTC (rev 1007) @@ -17,7 +17,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -\ { device_operations = "i945_mc_ops"; };
Modified: coreboot-v3/northbridge/intel/i945/northbridge.dts =================================================================== --- coreboot-v3/northbridge/intel/i945/northbridge.dts 2008-11-12 18:30:13 UTC (rev 1006) +++ coreboot-v3/northbridge/intel/i945/northbridge.dts 2008-11-12 22:23:46 UTC (rev 1007) @@ -17,7 +17,6 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -\ { device_operations = "i945_pci_domain_ops"; };
Added: coreboot-v3/southbridge/intel/i82801gx/pcie1.dts =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/pcie1.dts (rev 0) +++ coreboot-v3/southbridge/intel/i82801gx/pcie1.dts 2008-11-12 22:23:46 UTC (rev 1007) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich rminnich@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "i82801gx_pcie_port1"; +};