Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2798
-gerrit
commit 049c4e5c6cff3bca43d1aea8818076bd50f1de56 Author: Aaron Durbin adurbin@chromium.org Date: Tue Feb 12 00:46:17 2013 -0600
haswell: cbmem_get_table_location() implementation
Provide the implemenation of cbmem_get_table_location() so that cbmem can be initialized early in ramstage when CONFIG_EARLY_CBMEM_INIT is enabled. The cbmem tables are located just below the TSEG region.
Change-Id: Ia160ac6aff583fc52bf403d047529aaa07088085 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/northbridge/intel/haswell/northbridge.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index c8c1704..23bbd29 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -418,10 +418,6 @@ static void mc_add_dram_resources(device_t dev) mmio_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); #endif - - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_size = HIGH_MEMORY_SIZE; - high_tables_base = mc_values[TSEG_REG] - high_tables_size; }
static void mc_read_resources(device_t dev) @@ -546,6 +542,21 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; }
+#if CONFIG_EARLY_CBMEM_INIT +int cbmem_get_table_location(uint64_t *tables_base, uint64_t *tables_size) +{ + uint32_t tseg; + + /* Put the CBMEM location just below TSEG. */ + *tables_size = HIGH_MEMORY_SIZE; + tseg = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), + TSEG) & ~((1 << 20) - 1)) - HIGH_MEMORY_SIZE; + *tables_base = tseg; + + return 0; +} +#endif + static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME