On 10.10.2009 17:31, Peter Stuge wrote:
Stefan Reinauer wrote:
Enabling MMX and SSE per socket is only needed because romcc ne to work without cache or memory.
So far that's the only use, but that can change of course.
I don't think it can. Nor should it. Any other use of SSE or MMX in the firmware would be a very bad move.
Hm, why is that? If some code for a component which is known to have SSE - why not? It would basically mean -msse for gcc.
MOVNTQ and family, MMX memory ops and SSE memory ops are not allowed in CAR unless you deliberately want to access RAM instead of CAR. The AMD BKDG has the details.
Oh, just saw something at Apple. http://developer.apple.com/hardwaredrivers/ve/sse.html#ISA_Overview in the SSE section:
"SSE is enabled by default on gcc-4.0."
Don't know if that applies also to upstream gcc. Probably not.
Does that mean we have to disable SSE explicitly if we compile the CAR stage of coreboot on such GCC versions?
Regards, Carl-Daniel