Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2531
-gerrit
commit da80a7a93e81c735cc832889c0563e2cfec45450 Author: Ronald G. Minnich rminnich@gmail.com Date: Tue Feb 26 10:07:40 2013 -0800
Google Link: Add remaining code to support native graphics
The Link native graphics commit 49428d84 [1]
Add support for Google's Chromebook Pixel
was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot.
1. Add options to src/device/Kconfig to enable native graphics. 2. Export the MTRR function for setting variable MTRRs. 3. Clean up some of the comments and white space.
While I realize that the product name is Pixel, the mainboard in the coreboot tree is called Link, and that name is what we will use in our commits.
[1] http://review.coreboot.org/2482
Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich rminnich@gmail.com --- src/arch/x86/boot/coreboot_table.c | 2 +- src/cpu/x86/mtrr/mtrr.c | 2 +- src/device/Kconfig | 32 +++++++++++++++++----- src/include/cpu/x86/mtrr.h | 7 +++++ src/northbridge/intel/sandybridge/gma.c | 47 +++++++++++++++++++++++++++------ 5 files changed, 73 insertions(+), 17 deletions(-)
diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index ebeef2d..ab0f7ef 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -172,7 +172,7 @@ static void lb_console(struct lb_header *header)
static void lb_framebuffer(struct lb_header *header) { -#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE +#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE || CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int vbe_mode_info_valid(void);
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index a061b54..5051904 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -83,7 +83,7 @@ static void enable_var_mtrr(void) }
/* setting variable mtrr, comes from linux kernel source */ -static void set_var_mtrr( +void set_var_mtrr( unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type, unsigned address_bits) { diff --git a/src/device/Kconfig b/src/device/Kconfig index 8e1265f..159bc0e 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -19,12 +19,29 @@ ##
menu "Devices" + +# Only set this in the mainboard +config MAINBOARD_HAS_NATIVE_VGA_INIT + bool + default n + +config MAINBOARD_DO_NATIVE_VGA_INIT + bool "Use native graphics initialization" + depends on MAINBOARD_HAS_NATIVE_VGA_INIT + default n + help + Some mainboards, such as the Google Link, allow initializing the display + without the need of a binary only VGA OPROM. Enabling this option may be + faster, but also lack flexibility in setting modes. + + If unsure, say N. + # TODO: Explain differences (if any) for onboard cards. config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS || EXPERT + depends on PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT || EXPERT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -282,19 +299,19 @@ config MBI_FILE endmenu
menu "Display" - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT
config FRAMEBUFFER_SET_VESA_MODE - prompt "Set VESA framebuffer mode" + prompt "Set framebuffer graphics resolution" bool depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE help - Set VESA framebuffer mode (needed for bootsplash) + Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
choice - prompt "VESA framebuffer video mode" + prompt "framebuffer graphics resolution" default FRAMEBUFFER_VESA_MODE_117 - depends on FRAMEBUFFER_SET_VESA_MODE + depends on FRAMEBUFFER_SET_VESA_MODE || MAINBOARD_DO_NATIVE_VGA_INIT help This option sets the resolution used for the coreboot framebuffer (and bootsplash screen). @@ -385,6 +402,7 @@ config FRAMEBUFFER_VESA_MODE_11B
config FRAMEBUFFER_VESA_MODE_USER bool "Manually select VESA mode" + depends on !MAINBOARD_DO_NATIVE_VGA_INIT
endchoice
@@ -425,7 +443,7 @@ config FRAMEBUFFER_VESA_MODE config FRAMEBUFFER_KEEP_VESA_MODE prompt "Keep VESA framebuffer" bool - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || !MAINBOARD_DO_NATIVE_VGA_INIT help This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 58bee04..dcb7075 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -40,6 +40,13 @@
#if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) #include <device/device.h> +/* You should almost NEVER use this function. + * N.B. We worked on a lot of ways to make this continue as static, + * but just making it available ended up being the simplest solution. + */ +void set_var_mtrr( + unsigned int reg, unsigned long basek, unsigned long sizek, + unsigned char type, unsigned address_bits); void enable_fixed_mtrr(void); void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); void x86_setup_mtrrs(void); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f35299e..4a043eb 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -23,6 +23,9 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h>
#include "chip.h" #include "sandybridge.h" @@ -619,20 +622,47 @@ static void gma_pm_init_post_vbios(struct device *dev) static void gma_func0_init(struct device *dev) { u32 reg32; + u32 graphics_base, graphics_size;
/* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32);
+ /* Set up an MTRR for the graphics memory BAR to vastly improve + * speed of VGA initialization (and later access). To stay out of + * the way of the MTRR init code, we are using MTRR #8 to cover + * that range. + */ + graphics_base = dev->resource_list[1].base; + graphics_size = dev->resource_list[1].size; + printk(BIOS_DEBUG, "Setting up MTRR for graphics 0x%08x (%dK)\n", + graphics_base, graphics_size / 1024); + set_var_mtrr(8, graphics_base >> 10, graphics_size >> 10, + MTRR_TYPE_WRCOMB, 0x24); + /* Init graphics power management */ gma_pm_init_pre_vbios(dev);
+#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* PCI Init, will run VBIOS */ pci_dev_init(dev); +#endif
/* Post VBIOS init */ gma_pm_init_post_vbios(dev); + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + /* This should probably run before post VBIOS init. */ + printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); + u32 iobase, mmiobase, physbase; + iobase = dev->resource_list[2].base; + mmiobase = dev->resource_list[0].base; + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + + int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); + i915lightup(physbase, iobase, mmiobase, graphics_base); +#endif }
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -660,12 +690,13 @@ static struct device_operations gma_func0_ops = { .ops_pci = &gma_pci_ops, };
-static const unsigned short gma_ids[] = { - 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x0156, 0x166, - 0, -}; -static const struct pci_driver gma_gt1_desktop __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices= gma_ids, +static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112, + 0x0116, 0x0122, 0x0126, 0x0156, + 0x0166, + 0 }; + +static const struct pci_driver gma __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, };