Buy another chip, make a breakout board, remove onboard chip, connect probes to breakout board, connect breakout board to mainboard.
Thanks, but this is a pretty time-consuming method if I need to tap four consecutive legs out of one hundred. Also BBs adding extra crosstalk which could lead to erroneous behavior even for tens of megahertz when scheme is coupled with high-impedance logic analyzer.
This is documented behavior of the chipset.
"SLP S4# Assertion Width Violation" is the hardware telling the firmware (you) that the hardware has not been in S4# long enough, and simply isn't ready just yet.
Chipset docs specify how long firmware should wait, before it can try to power the platform up again.
Awesome, thank you, I never had a single thought that this could be a documented behavior - EEPROM read stage takes a plenty of time (something around sixty milliseconds) and I`ve automatically threw all time-related chipset initialization stuff out of scope.