Author: eswierk Date: 2008-08-25 16:41:11 +0200 (Mon, 25 Aug 2008) New Revision: 3534
Added: trunk/coreboot-v2/src/cpu/intel/ep80579/ trunk/coreboot-v2/src/cpu/intel/ep80579/Config.lb trunk/coreboot-v2/src/cpu/intel/ep80579/chip.h trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579.c trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579_init.c Log: This patch implements support for the CPU core of the Intel EP80579 Integrated Processor.
Signed-off-by: Ed Swierk eswierk@arastra.com Acked-by: Uwe Hermann uwe@hermann-uwe.de
Added: trunk/coreboot-v2/src/cpu/intel/ep80579/Config.lb =================================================================== --- trunk/coreboot-v2/src/cpu/intel/ep80579/Config.lb (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/ep80579/Config.lb 2008-08-25 14:41:11 UTC (rev 3534) @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Arastra, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License version 2 as +## published by the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h +object ep80579.o +dir /cpu/x86/tsc +dir /cpu/x86/mtrr +dir /cpu/x86/fpu +dir /cpu/x86/mmx +dir /cpu/x86/sse +dir /cpu/x86/lapic +dir /cpu/x86/cache +dir /cpu/intel/microcode +driver ep80579_init.o
Added: trunk/coreboot-v2/src/cpu/intel/ep80579/chip.h =================================================================== --- trunk/coreboot-v2/src/cpu/intel/ep80579/chip.h (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/ep80579/chip.h 2008-08-25 14:41:11 UTC (rev 3534) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_intel_ep80579_ops; + +struct cpu_intel_ep80579_config { +};
Added: trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579.c 2008-08-25 14:41:11 UTC (rev 3534) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_intel_ep80579_ops = { + CHIP_NAME("EP80579 CPU") +};
Added: trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579_init.c (rev 0) +++ trunk/coreboot-v2/src/cpu/intel/ep80579/ep80579_init.c 2008-08-25 14:41:11 UTC (rev 3534) @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> + +static u32 microcode_updates[] = { + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; + +static void ep80579_init(device_t dev) +{ + /* Turn on caching if we haven't already */ + x86_enable_cache(); + x86_setup_mtrrs(36); + x86_mtrr_check(); + + /* Update the microcode */ + intel_update_microcode(microcode_updates); + + /* Enable the local cpu apics */ + setup_lapic(); +}; + +static struct device_operations cpu_dev_ops = { + .init = ep80579_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x10650 }, /* EP80579 */ + { 0, 0 }, +}; + +static struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +};