Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2747
-gerrit
commit 47a75d1a734d5dc67dc5bd196cd6ce40795bd942 Author: Aaron Durbin adurbin@chromium.org Date: Tue Jan 15 15:34:08 2013 -0600
haswell: lapic timer support
Haswell's BCLK is fised at 100MHz like Sandy/Ivy. Add Haswell's model to the switch statement.
Change-Id: Ib9e2afc04eba940bfcee92a6ee5402759b21cc45 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/cpu/x86/lapic/apic_timer.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index cd6e472..b60da27 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -62,6 +62,8 @@ static int set_timer_fsb(void) break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ + case 0x3c: /* Haswell BCLK fixed at 100MHz */ + case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ timer_fsb = 100; break; default: